February 2023 - flashrom-gerrit

[S] Change in flashrom[master]: jedec.c: Fold up mask param into func
by Edward O'Callaghan (Code Review) 21 Feb '23

21 Feb '23

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/72631 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: jedec.c: Fold up mask param into func ...................................................................... jedec.c: Fold up mask param into func Change-Id: Iee4b1d5bc850cbeec0de9a1603fe04a3a1855330 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72631 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M jedec.c 1 file changed, 21 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/jedec.c b/jedec.c index 7f72e53..1ba7b63 100644 --- a/jedec.c +++ b/jedec.c @@ -110,10 +110,11 @@ } } -static void start_program_jedec_common(const struct flashctx *flash, unsigned int mask) +static void start_program_jedec_common(const struct flashctx *flash) { - chipaddr bios = flash->virtual_memory; - bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED); + const chipaddr bios = flash->virtual_memory; + const bool shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED); + const unsigned int mask = getaddrmask(flash->chip); chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); @@ -345,7 +346,7 @@ } static int write_byte_program_jedec_common(const struct flashctx *flash, const uint8_t *src, - chipaddr dst, unsigned int mask) + chipaddr dst) { int tries = 0; @@ -357,7 +358,7 @@ for (; tries < MAX_REFLASH_TRIES; tries++) { const chipaddr bios = flash->virtual_memory; /* Issue JEDEC Byte Program command */ - start_program_jedec_common(flash, mask); + start_program_jedec_common(flash); /* transfer data from source to destination */ chip_writeb(flash, *src, dst); @@ -378,11 +379,10 @@ int failed = 0; chipaddr dst = flash->virtual_memory + start; chipaddr olddst; - const unsigned int mask = getaddrmask(flash->chip); olddst = dst; for (i = 0; i < len; i++) { - if (write_byte_program_jedec_common(flash, src, dst, mask)) + if (write_byte_program_jedec_common(flash, src, dst)) failed = 1; dst++, src++; update_progress(flash, FLASHROM_PROGRESS_WRITE, i + 1, len); @@ -401,11 +401,10 @@ const chipaddr bios = flash->virtual_memory; chipaddr dst = bios + start; chipaddr d = dst; - const unsigned int mask = getaddrmask(flash->chip); for (; tries < MAX_REFLASH_TRIES; tries++) { /* Issue JEDEC Start Program command */ - start_program_jedec_common(flash, mask); + start_program_jedec_common(flash); /* transfer data from source to destination */ for (unsigned int i = 0; i < page_size; i++) { -- To view, visit https://review.coreboot.org/c/flashrom/+/72631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iee4b1d5bc850cbeec0de9a1603fe04a3a1855330 Gerrit-Change-Number: 72631 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in flashrom[master]: jedec.c: Rewrite control flow procedurally
by Edward O'Callaghan (Code Review) 21 Feb '23

21 Feb '23

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/72608 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: jedec.c: Rewrite control flow procedurally ...................................................................... jedec.c: Rewrite control flow procedurally Drop goto usage in fav of loop constructs. Change-Id: I0927ed40e54cc7e114a57dc40e3614f4825a0ca9 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72608 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M jedec.c 1 file changed, 47 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/jedec.c b/jedec.c index db01c08..7f72e53 100644 --- a/jedec.c +++ b/jedec.c @@ -347,30 +347,27 @@ static int write_byte_program_jedec_common(const struct flashctx *flash, const uint8_t *src, chipaddr dst, unsigned int mask) { - int tried = 0, failed = 0; - chipaddr bios = flash->virtual_memory; + int tries = 0; /* If the data is 0xFF, don't program it and don't complain. */ if (*src == 0xFF) { return 0; } -retry: - /* Issue JEDEC Byte Program command */ - start_program_jedec_common(flash, mask); + for (; tries < MAX_REFLASH_TRIES; tries++) { + const chipaddr bios = flash->virtual_memory; + /* Issue JEDEC Byte Program command */ + start_program_jedec_common(flash, mask); - /* transfer data from source to destination */ - chip_writeb(flash, *src, dst); - toggle_ready_jedec(flash, bios); + /* transfer data from source to destination */ + chip_writeb(flash, *src, dst); + toggle_ready_jedec(flash, bios); - if (chip_readb(flash, dst) != *src && tried++ < MAX_REFLASH_TRIES) { - goto retry; + if (chip_readb(flash, dst) == *src) + break; } - if (tried >= MAX_REFLASH_TRIES) - failed = 1; - - return failed; + return (tries >= MAX_REFLASH_TRIES) ? 1 : 0; } /* chunksize is 1 */ @@ -399,40 +396,41 @@ static int write_page_write_jedec_common(struct flashctx *flash, const uint8_t *src, unsigned int start, unsigned int page_size) { - unsigned int i; - int tried = 0, failed; + int tries = 0, failed; const uint8_t *s = src; - chipaddr bios = flash->virtual_memory; + const chipaddr bios = flash->virtual_memory; chipaddr dst = bios + start; chipaddr d = dst; const unsigned int mask = getaddrmask(flash->chip); -retry: - /* Issue JEDEC Start Program command */ - start_program_jedec_common(flash, mask); + for (; tries < MAX_REFLASH_TRIES; tries++) { + /* Issue JEDEC Start Program command */ + start_program_jedec_common(flash, mask); - /* transfer data from source to destination */ - for (i = 0; i < page_size; i++) { - /* If the data is 0xFF, don't program it */ - if (*src != 0xFF) - chip_writeb(flash, *src, dst); - dst++; - src++; - } + /* transfer data from source to destination */ + for (unsigned int i = 0; i < page_size; i++) { + /* If the data is 0xFF, don't program it */ + if (*src != 0xFF) + chip_writeb(flash, *src, dst); + dst++; + src++; + } - toggle_ready_jedec(flash, dst - 1); + toggle_ready_jedec(flash, dst - 1); - dst = d; - src = s; - failed = verify_range(flash, src, start, page_size); + dst = d; + src = s; + failed = verify_range(flash, src, start, page_size); + if (!failed) + break; - if (failed && tried++ < MAX_REFLASH_TRIES) { msg_cerr("retrying.\n"); - goto retry; } + if (failed) { msg_cerr(" page 0x%" PRIxPTR " failed!\n", (d - bios) / page_size); } + return failed; } -- To view, visit https://review.coreboot.org/c/flashrom/+/72608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0927ed40e54cc7e114a57dc40e3614f4825a0ca9 Gerrit-Change-Number: 72608 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in flashrom[master]: jedec.c: Move printlock stuff into printlock.c
by Edward O'Callaghan (Code Review) 21 Feb '23

21 Feb '23

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/72607 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: jedec.c: Move printlock stuff into printlock.c ...................................................................... jedec.c: Move printlock stuff into printlock.c Change-Id: Iacaa16c81e141aac30feb6871700c4fdc9eec8e9 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72607 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Thomas Heijligen <src(a)posteo.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Makefile M jedec.c M meson.build A printlock.c 4 files changed, 229 insertions(+), 190 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved Thomas Heijligen: Looks good to me, but someone else must approve diff --git a/Makefile b/Makefile index 25c01e0..69818ce 100644 --- a/Makefile +++ b/Makefile @@ -379,7 +379,7 @@ ############################################################################### # Flash chip drivers and bus support infrastructure. -CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \ +CHIP_OBJS = jedec.o printlock.o stm50.o w39.o w29ee011.o \ sst28sf040.o 82802ab.o \ sst49lfxxxc.o sst_fwhub.o edi.o flashchips.o spi.o spi25.o spi25_statusreg.o \ spi95.o opaque.o sfdp.o en29lv640b.o at45db.o s25f.o \ diff --git a/jedec.c b/jedec.c index e33ce93..db01c08 100644 --- a/jedec.c +++ b/jedec.c @@ -478,192 +478,3 @@ return 0; } - -struct unlockblock { - unsigned int size; - unsigned int count; -}; - -typedef int (*unlockblock_func)(const struct flashctx *flash, chipaddr offset); -static int regspace2_walk_unlockblocks(const struct flashctx *flash, const struct unlockblock *block, unlockblock_func func) -{ - chipaddr off = flash->virtual_registers + 2; - while (block->count != 0) { - unsigned int j; - for (j = 0; j < block->count; j++) { - if (func(flash, off)) - return -1; - off += block->size; - } - block++; - } - return 0; -} - -#define REG2_RWLOCK ((1 << 2) | (1 << 0)) -#define REG2_LOCKDOWN (1 << 1) -#define REG2_MASK (REG2_RWLOCK | REG2_LOCKDOWN) - -static int printlock_regspace2_block(const struct flashctx *flash, chipaddr lockreg) -{ - uint8_t state = chip_readb(flash, lockreg); - msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, lockreg); - switch (state & REG2_MASK) { - case 0: - msg_cdbg("Full Access.\n"); - break; - case 1: - msg_cdbg("Write Lock (Default State).\n"); - break; - case 2: - msg_cdbg("Locked Open (Full Access, Locked Down).\n"); - break; - case 3: - msg_cdbg("Write Lock, Locked Down.\n"); - break; - case 4: - msg_cdbg("Read Lock.\n"); - break; - case 5: - msg_cdbg("Read/Write Lock.\n"); - break; - case 6: - msg_cdbg("Read Lock, Locked Down.\n"); - break; - case 7: - msg_cdbg("Read/Write Lock, Locked Down.\n"); - break; - } - return 0; -} - -static int printlock_regspace2_uniform(struct flashctx *flash, unsigned long block_size) -{ - const unsigned int elems = flash->chip->total_size * 1024 / block_size; - struct unlockblock blocks[2] = {{.size = block_size, .count = elems}}; - return regspace2_walk_unlockblocks(flash, blocks, &printlock_regspace2_block); -} - -int printlock_regspace2_uniform_64k(struct flashctx *flash) -{ - return printlock_regspace2_uniform(flash, 64 * 1024); -} - -int printlock_regspace2_block_eraser_0(struct flashctx *flash) -{ - // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). - const struct unlockblock *unlockblocks = - (const struct unlockblock *)flash->chip->block_erasers[0].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &printlock_regspace2_block); -} - -int printlock_regspace2_block_eraser_1(struct flashctx *flash) -{ - // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). - const struct unlockblock *unlockblocks = - (const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &printlock_regspace2_block); -} - -/* Try to change the lock register at address lockreg from cur to new. - * - * - Try to unlock the lock bit if requested and it is currently set (although this is probably futile). - * - Try to change the read/write bits if requested. - * - Try to set the lockdown bit if requested. - * Return an error immediately if any of this fails. */ -static int changelock_regspace2_block(const struct flashctx *flash, chipaddr lockreg, uint8_t cur, uint8_t new) -{ - /* Only allow changes to known read/write/lockdown bits */ - if (((cur ^ new) & ~REG2_MASK) != 0) { - msg_cerr("Invalid lock change from 0x%02x to 0x%02x requested at 0x%0*" PRIxPTR "!\n" - "Please report a bug at flashrom(a)flashrom.org\n", - cur, new, PRIxPTR_WIDTH, lockreg); - return -1; - } - - /* Exit early if no change (of read/write/lockdown bits) was requested. */ - if (((cur ^ new) & REG2_MASK) == 0) { - msg_cdbg2("Lock bits at 0x%0*" PRIxPTR " not changed.\n", PRIxPTR_WIDTH, lockreg); - return 0; - } - - /* Normally the lockdown bit can not be cleared. Try nevertheless if requested. */ - if ((cur & REG2_LOCKDOWN) && !(new & REG2_LOCKDOWN)) { - chip_writeb(flash, cur & ~REG2_LOCKDOWN, lockreg); - cur = chip_readb(flash, lockreg); - if ((cur & REG2_LOCKDOWN) == REG2_LOCKDOWN) { - msg_cwarn("Lockdown can't be removed at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", - PRIxPTR_WIDTH, lockreg, cur); - return -1; - } - } - - /* Change read and/or write bit */ - if ((cur ^ new) & REG2_RWLOCK) { - /* Do not lockdown yet. */ - uint8_t wanted = (cur & ~REG2_RWLOCK) | (new & REG2_RWLOCK); - chip_writeb(flash, wanted, lockreg); - cur = chip_readb(flash, lockreg); - if (cur != wanted) { - msg_cerr("Changing lock bits failed at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", - PRIxPTR_WIDTH, lockreg, cur); - return -1; - } - msg_cdbg("Changed lock bits at 0x%0*" PRIxPTR " to 0x%02x.\n", - PRIxPTR_WIDTH, lockreg, cur); - } - - /* Eventually, enable lockdown if requested. */ - if (!(cur & REG2_LOCKDOWN) && (new & REG2_LOCKDOWN)) { - chip_writeb(flash, new, lockreg); - cur = chip_readb(flash, lockreg); - if (cur != new) { - msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", - PRIxPTR_WIDTH, lockreg, cur); - return -1; - } - msg_cdbg("Enabled lockdown at 0x%0*" PRIxPTR ".\n", PRIxPTR_WIDTH, lockreg); - } - - return 0; -} - -static int unlock_regspace2_block_generic(const struct flashctx *flash, chipaddr lockreg) -{ - uint8_t old = chip_readb(flash, lockreg); - /* We don't care for the lockdown bit as long as the RW locks are 0 after we're done */ - return changelock_regspace2_block(flash, lockreg, old, old & ~REG2_RWLOCK); -} - -static int unlock_regspace2_uniform(struct flashctx *flash, unsigned long block_size) -{ - const unsigned int elems = flash->chip->total_size * 1024 / block_size; - struct unlockblock blocks[2] = {{.size = block_size, .count = elems}}; - return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block_generic); -} - -int unlock_regspace2_uniform_64k(struct flashctx *flash) -{ - return unlock_regspace2_uniform(flash, 64 * 1024); -} - -int unlock_regspace2_uniform_32k(struct flashctx *flash) -{ - return unlock_regspace2_uniform(flash, 32 * 1024); -} - -int unlock_regspace2_block_eraser_0(struct flashctx *flash) -{ - // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). - const struct unlockblock *unlockblocks = - (const struct unlockblock *)flash->chip->block_erasers[0].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); -} - -int unlock_regspace2_block_eraser_1(struct flashctx *flash) -{ - // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). - const struct unlockblock *unlockblocks = - (const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); -} diff --git a/meson.build b/meson.build index 2f11c3f..baa1084 100644 --- a/meson.build +++ b/meson.build @@ -61,6 +61,7 @@ 'helpers_fileio.c', 'ich_descriptors.c', 'jedec.c', + 'printlock.c', 'layout.c', 'libflashrom.c', 'opaque.c', diff --git a/printlock.c b/printlock.c new file mode 100644 index 0000000..d05251e --- /dev/null +++ b/printlock.c @@ -0,0 +1,213 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2000 Silicon Integrated System Corporation + * Copyright (C) 2006 Giampiero Giancipoli <gianci(a)email.it> + * Copyright (C) 2006 coresystems GmbH <info(a)coresystems.de> + * Copyright (C) 2007-2012 Carl-Daniel Hailfinger + * Copyright (C) 2009 Sean Nelson <audiohacked(a)gmail.com> + * Copyright (C) 2014 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "flash.h" +#include "chipdrivers.h" + + +struct unlockblock { + unsigned int size; + unsigned int count; +}; + +typedef int (*unlockblock_func)(const struct flashctx *flash, chipaddr offset); +static int regspace2_walk_unlockblocks(const struct flashctx *flash, const struct unlockblock *block, unlockblock_func func) +{ + chipaddr off = flash->virtual_registers + 2; + while (block->count != 0) { + unsigned int j; + for (j = 0; j < block->count; j++) { + if (func(flash, off)) + return -1; + off += block->size; + } + block++; + } + return 0; +} + +#define REG2_RWLOCK ((1 << 2) | (1 << 0)) +#define REG2_LOCKDOWN (1 << 1) +#define REG2_MASK (REG2_RWLOCK | REG2_LOCKDOWN) + +static int printlock_regspace2_block(const struct flashctx *flash, chipaddr lockreg) +{ + uint8_t state = chip_readb(flash, lockreg); + msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, lockreg); + switch (state & REG2_MASK) { + case 0: + msg_cdbg("Full Access.\n"); + break; + case 1: + msg_cdbg("Write Lock (Default State).\n"); + break; + case 2: + msg_cdbg("Locked Open (Full Access, Locked Down).\n"); + break; + case 3: + msg_cdbg("Write Lock, Locked Down.\n"); + break; + case 4: + msg_cdbg("Read Lock.\n"); + break; + case 5: + msg_cdbg("Read/Write Lock.\n"); + break; + case 6: + msg_cdbg("Read Lock, Locked Down.\n"); + break; + case 7: + msg_cdbg("Read/Write Lock, Locked Down.\n"); + break; + } + return 0; +} + +static int printlock_regspace2_uniform(struct flashctx *flash, unsigned long block_size) +{ + const unsigned int elems = flash->chip->total_size * 1024 / block_size; + struct unlockblock blocks[2] = {{.size = block_size, .count = elems}}; + return regspace2_walk_unlockblocks(flash, blocks, &printlock_regspace2_block); +} + +int printlock_regspace2_uniform_64k(struct flashctx *flash) +{ + return printlock_regspace2_uniform(flash, 64 * 1024); +} + +int printlock_regspace2_block_eraser_0(struct flashctx *flash) +{ + // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). + const struct unlockblock *unlockblocks = + (const struct unlockblock *)flash->chip->block_erasers[0].eraseblocks; + return regspace2_walk_unlockblocks(flash, unlockblocks, &printlock_regspace2_block); +} + +int printlock_regspace2_block_eraser_1(struct flashctx *flash) +{ + // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). + const struct unlockblock *unlockblocks = + (const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks; + return regspace2_walk_unlockblocks(flash, unlockblocks, &printlock_regspace2_block); +} + +/* Try to change the lock register at address lockreg from cur to new. + * + * - Try to unlock the lock bit if requested and it is currently set (although this is probably futile). + * - Try to change the read/write bits if requested. + * - Try to set the lockdown bit if requested. + * Return an error immediately if any of this fails. */ +static int changelock_regspace2_block(const struct flashctx *flash, chipaddr lockreg, uint8_t cur, uint8_t new) +{ + /* Only allow changes to known read/write/lockdown bits */ + if (((cur ^ new) & ~REG2_MASK) != 0) { + msg_cerr("Invalid lock change from 0x%02x to 0x%02x requested at 0x%0*" PRIxPTR "!\n" + "Please report a bug at flashrom(a)flashrom.org\n", + cur, new, PRIxPTR_WIDTH, lockreg); + return -1; + } + + /* Exit early if no change (of read/write/lockdown bits) was requested. */ + if (((cur ^ new) & REG2_MASK) == 0) { + msg_cdbg2("Lock bits at 0x%0*" PRIxPTR " not changed.\n", PRIxPTR_WIDTH, lockreg); + return 0; + } + + /* Normally the lockdown bit can not be cleared. Try nevertheless if requested. */ + if ((cur & REG2_LOCKDOWN) && !(new & REG2_LOCKDOWN)) { + chip_writeb(flash, cur & ~REG2_LOCKDOWN, lockreg); + cur = chip_readb(flash, lockreg); + if ((cur & REG2_LOCKDOWN) == REG2_LOCKDOWN) { + msg_cwarn("Lockdown can't be removed at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); + return -1; + } + } + + /* Change read and/or write bit */ + if ((cur ^ new) & REG2_RWLOCK) { + /* Do not lockdown yet. */ + uint8_t wanted = (cur & ~REG2_RWLOCK) | (new & REG2_RWLOCK); + chip_writeb(flash, wanted, lockreg); + cur = chip_readb(flash, lockreg); + if (cur != wanted) { + msg_cerr("Changing lock bits failed at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); + return -1; + } + msg_cdbg("Changed lock bits at 0x%0*" PRIxPTR " to 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); + } + + /* Eventually, enable lockdown if requested. */ + if (!(cur & REG2_LOCKDOWN) && (new & REG2_LOCKDOWN)) { + chip_writeb(flash, new, lockreg); + cur = chip_readb(flash, lockreg); + if (cur != new) { + msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); + return -1; + } + msg_cdbg("Enabled lockdown at 0x%0*" PRIxPTR ".\n", PRIxPTR_WIDTH, lockreg); + } + + return 0; +} + +static int unlock_regspace2_block_generic(const struct flashctx *flash, chipaddr lockreg) +{ + uint8_t old = chip_readb(flash, lockreg); + /* We don't care for the lockdown bit as long as the RW locks are 0 after we're done */ + return changelock_regspace2_block(flash, lockreg, old, old & ~REG2_RWLOCK); +} + +static int unlock_regspace2_uniform(struct flashctx *flash, unsigned long block_size) +{ + const unsigned int elems = flash->chip->total_size * 1024 / block_size; + struct unlockblock blocks[2] = {{.size = block_size, .count = elems}}; + return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block_generic); +} + +int unlock_regspace2_uniform_64k(struct flashctx *flash) +{ + return unlock_regspace2_uniform(flash, 64 * 1024); +} + +int unlock_regspace2_uniform_32k(struct flashctx *flash) +{ + return unlock_regspace2_uniform(flash, 32 * 1024); +} + +int unlock_regspace2_block_eraser_0(struct flashctx *flash) +{ + // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). + const struct unlockblock *unlockblocks = + (const struct unlockblock *)flash->chip->block_erasers[0].eraseblocks; + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); +} + +int unlock_regspace2_block_eraser_1(struct flashctx *flash) +{ + // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). + const struct unlockblock *unlockblocks = + (const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks; + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); +} -- To view, visit https://review.coreboot.org/c/flashrom/+/72607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iacaa16c81e141aac30feb6871700c4fdc9eec8e9 Gerrit-Change-Number: 72607 Gerrit-PatchSet: 4 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in flashrom[master]: cli_classic: include a fallback inplementation of getopt.
by Thomas Heijligen (Code Review) 21 Feb '23

21 Feb '23

Attention is currently required from: Angel Pons. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/73102 ) Change subject: cli_classic: include a fallback inplementation of getopt. ...................................................................... Patch Set 1: (3 comments) Patchset: PS1: > Code style is completely different, is this intentional? Are there plans to keep this in sync with m […] Not really. I just copied and tested it. I will adapt it File cli_getopt.c: https://review.coreboot.org/c/flashrom/+/73102/comment/f9207839_b86b1c56 PS1, Line 13: #if 0 > Hmmmm Yea, this should be replaces by flashroms error message. File include/cli_classic.h: https://review.coreboot.org/c/flashrom/+/73102/comment/ed210e62_5c5c655f PS1, Line 5: __has_include > Interesting, is this standard in the C version we use? This is an extension supported by GCC >=5, clang, Apple clang, MSVC 19.11 (Microsoft VS2017). From c23 it is also in the standard. I started to use it to make the headers simpler. -- To view, visit https://review.coreboot.org/c/flashrom/+/73102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6ebbde075014e3b45b0f9e04b34b72aa969e1197 Gerrit-Change-Number: 73102 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 21 Feb 2023 09:33:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashchips.c: Add reg_bits for W25Q256JW_DTR
by Anastasia Klimchuk (Code Review) 21 Feb '23

21 Feb '23

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/70549 ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: flashchips.c: Add reg_bits for W25Q256JW_DTR ...................................................................... flashchips.c: Add reg_bits for W25Q256JW_DTR Add reg_bits for W25Q256JW_DTR as per the datasheet. BUG=b:263410331 TEST=Verified on google/rex. w/o this patch: Failed to get WP status: WP operations are not implemented for this chip w/ this patch: flashrom -p internal --wp-range 0x0,0x2000000 flashrom -p internal --wp-enable flashrom -p internal --wp-status flashrom -p internal -E <---- failed to erase the flash as WP (which is expected) Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I8ac23f706d4293a7d7d11ad6b2f62526fb075367 Reviewed-on: https://review.coreboot.org/c/flashrom/+/70549 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M flashchips.c 1 file changed, 42 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index 625fe62..c24e264 100644 --- a/flashchips.c +++ b/flashchips.c @@ -18108,8 +18108,9 @@ .page_size = 256, /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, - .tested = TEST_OK_PREW, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_WRSR2 + | FEATURE_WRSR3, + .tested = TEST_OK_PREWB, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, .block_erasers = @@ -18142,6 +18143,16 @@ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, .voltage = {1700, 1950}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + .wps = {STATUS3, 2, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { -- To view, visit https://review.coreboot.org/c/flashrom/+/70549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8ac23f706d4293a7d7d11ad6b2f62526fb075367 Gerrit-Change-Number: 70549 Gerrit-PatchSet: 9 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in flashrom[master]: MAINTAINERS: flashrom_tester: Change email
by Anastasia Klimchuk (Code Review) 21 Feb '23

21 Feb '23

Attention is currently required from: Felix Singer, Evan Benn. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/73175 ) Change subject: MAINTAINERS: flashrom_tester: Change email ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File MAINTAINERS: https://review.coreboot.org/c/flashrom/+/73175/comment/a71b664b_000ba2f9 PS1, Line 173: S: Supported > This is probably still supported, but not by me Edward, do you think someone else can take this? Thank you! -- To view, visit https://review.coreboot.org/c/flashrom/+/73175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic1a53ddbc38e7d63f7b15aa2b31c63a5b65746f9 Gerrit-Change-Number: 73175 Gerrit-PatchSet: 1 Gerrit-Owner: Evan Benn <evanbenn(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Evan Benn <evanbenn(a)gmail.com> Gerrit-Comment-Date: Tue, 21 Feb 2023 06:34:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Evan Benn <evanbenn(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: MAINTAINERS: flashrom_tester: Change email
by Evan Benn (Code Review) 21 Feb '23

21 Feb '23

Attention is currently required from: Felix Singer, Anastasia Klimchuk. Evan Benn has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/73175 ) Change subject: MAINTAINERS: flashrom_tester: Change email ...................................................................... Patch Set 1: (1 comment) File MAINTAINERS: https://review.coreboot.org/c/flashrom/+/73175/comment/5fcf1f6d_25a28db2 PS1, Line 173: S: Supported This is probably still supported, but not by me -- To view, visit https://review.coreboot.org/c/flashrom/+/73175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic1a53ddbc38e7d63f7b15aa2b31c63a5b65746f9 Gerrit-Change-Number: 73175 Gerrit-PatchSet: 1 Gerrit-Owner: Evan Benn <evanbenn(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Tue, 21 Feb 2023 06:16:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in flashrom[master]: MAINTAINERS: flashrom_tester: Change email
by Evan Benn (Code Review) 21 Feb '23

21 Feb '23

Evan Benn has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/73175 ) Change subject: MAINTAINERS: flashrom_tester: Change email ...................................................................... MAINTAINERS: flashrom_tester: Change email Change-Id: Ic1a53ddbc38e7d63f7b15aa2b31c63a5b65746f9 Signed-off-by: Evan Benn <evanbenn(a)gmail.com> --- M MAINTAINERS 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/75/73175/1 diff --git a/MAINTAINERS b/MAINTAINERS index a8a6203..258a29f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -169,7 +169,7 @@ F: test_build.sh FLASHROM TESTER -M: Evan Benn <evanbenn(a)chromium.org> +R: Evan Benn <evanbenn(a)gmail.com> S: Supported F: util/flashrom_tester/ -- To view, visit https://review.coreboot.org/c/flashrom/+/73175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic1a53ddbc38e7d63f7b15aa2b31c63a5b65746f9 Gerrit-Change-Number: 73175 Gerrit-PatchSet: 1 Gerrit-Owner: Evan Benn <evanbenn(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in flashrom[master]: jedec.c: Fold up dst into toggle_ready_jedec()
by Edward O'Callaghan (Code Review) 21 Feb '23

21 Feb '23

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/72691 ) Change subject: jedec.c: Fold up dst into toggle_ready_jedec() ...................................................................... jedec.c: Fold up dst into toggle_ready_jedec() Change-Id: Ib7a3fdbc6e0a888093dc8da6f5567a7301ec5040 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72691 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M jedec.c 1 file changed, 19 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved diff --git a/jedec.c b/jedec.c index 3f27337..e33ce93 100644 --- a/jedec.c +++ b/jedec.c @@ -67,8 +67,9 @@ * Given that erase is slow on all chips, it is recommended to use * toggle_ready_jedec_slow in erase functions. */ -static void toggle_ready_jedec_slow(const struct flashctx *flash, chipaddr dst) +static void toggle_ready_jedec_slow(const struct flashctx *flash) { + const chipaddr dst = flash->virtual_memory; toggle_ready_jedec_common(flash, dst, 8 * 1000); } @@ -300,14 +301,12 @@ int erase_sector_jedec(struct flashctx *flash, unsigned int page, unsigned int size) { - const chipaddr bios = flash->virtual_memory; - /* Issue the Sector Erase command */ issuecmd(flash, 0x80, 0); issuecmd(flash, 0x30, page); /* wait for Toggle bit ready */ - toggle_ready_jedec_slow(flash, bios); + toggle_ready_jedec_slow(flash); /* FIXME: Check the status register for errors. */ return 0; @@ -315,14 +314,12 @@ int erase_block_jedec(struct flashctx *flash, unsigned int block, unsigned int size) { - const chipaddr bios = flash->virtual_memory; - /* Issue the Sector Erase command */ issuecmd(flash, 0x80, 0); issuecmd(flash, 0x50, block); /* wait for Toggle bit ready */ - toggle_ready_jedec_slow(flash, bios); + toggle_ready_jedec_slow(flash); /* FIXME: Check the status register for errors. */ return 0; @@ -331,8 +328,6 @@ /* erase chip with block_erase() prototype */ int erase_chip_block_jedec(struct flashctx *flash, unsigned int addr, unsigned int blocksize) { - const chipaddr bios = flash->virtual_memory; - if ((addr != 0) || (blocksize != flash->chip->total_size * 1024)) { msg_cerr("%s called with incorrect arguments\n", __func__); @@ -343,7 +338,7 @@ issuecmd(flash, 0x80, 0); issuecmd(flash, 0x10, 0); - toggle_ready_jedec_slow(flash, bios); + toggle_ready_jedec_slow(flash); /* FIXME: Check the status register for errors. */ return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/72691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib7a3fdbc6e0a888093dc8da6f5567a7301ec5040 Gerrit-Change-Number: 72691 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in flashrom[master]: Add support for AMD Ryzen flashing
by ChrisEric1 CECL (Code Review) 21 Feb '23

21 Feb '23

Attention is currently required from: Arthur Heymans, Nicholas Chin. Hello build bot (Jenkins), Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/72058 to look at the new patch set (#8). Change subject: Add support for AMD Ryzen flashing ...................................................................... Add support for AMD Ryzen flashing Tested AMD Ryzen Support on HP Pavilion 590-p0077c, I am able to flash using F.15 or older, but I can downgrade if a newer Firmware is installed using afuwinx64 which is a vendor tool This is due to flashrom SPI lockdown on newer firmwares by HP. It seems HP UEFI Diags uses AFU Flash embedded in. It also comes with a AMD Ryzen 3 2200G with 16MB, so it may not work with chips more that 16MB, it is currently untested by me, since this is the only AMD PC I own. Change-Id: Ife51f7dec31b51a7416e417112b0eedb21fae6a0 Signed-off-by: Christopher Lentocha <christopherericlentocha(a)gmail.com> --- M sb600spi.c 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/58/72058/8 -- To view, visit https://review.coreboot.org/c/flashrom/+/72058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ife51f7dec31b51a7416e417112b0eedb21fae6a0 Gerrit-Change-Number: 72058 Gerrit-PatchSet: 8 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newpatchset

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