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Kevin Yu has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/79287?usp=email )
Change subject: Add Idaville platform into chipset enable list and add update IRC region support
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I also found there is an earlier patch that you sent CB:67438 which very sadly got missed :\ I apolo […]
Hi Anastasia Klimchuk
I only need this code change, you can ignore that one.
Thanks
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Change subject: erasure_layout: Remove redundant verifications from `erase_write`
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Anastasia,
Here are the changes to removing verification 2 and 3 as discussed. Thank you so much for your help in reviewing and discussing these changes. Testing information is posted below, with timing improvements obtained from comparing this data to the `New Erase Path` group from patchset 1's testing summary.
```
Testing summary:
Verifications:
Inside erase block
1. check_erased_range in erasure_layout.c lines 341-345
2. check_erased_range in erasure_layout.c lines 353-359
After erasing
3. verify_range in erasure_layout.c lines 388-394
4. verify block in flashrom.c lines 2329-2348 (only when writing)
New Erase Path Sans Verification 2 and 3:
1. Erase entire chip
Erase chip contents: 85.622
Write to chip: 0.080 (artifact from timing capture location)
Total execution time: 86.269
Timing improvements:
- 40% faster to erase the chip contents due to the removal of verification 2
- 57% faster overall from the removal of 2 and 3
2. Program flash starting with empty contents
Read previous contents: 57.133
Erase relevant parts: 0 (already empty)
Write time: 25.201
Verify contents: 58.840
Total execution time: 142.349
Timing improvements:
- 29% faster overall from the removal of verification 3
3. Program different contents
Read previous contents: 57.128
Erase relevant parts: 21.019
Write time: 10.322
Verify contents: 58.824
Total execution time: 148.380
Timing improvements:
- 18% faster to erase relevant contents from removing verification 2
- 29% faster overall from the removal of 2 and 3
```
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Hello Aarya, Anastasia Klimchuk, Vincent Fazio, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/79354?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: erasure_layout: Remove redundant verifications from `erase_write`
......................................................................
erasure_layout: Remove redundant verifications from `erase_write`
Previously, in the worst-case scenario of erasing region content then
writing new data, three rounds of verification were performed inside of
the `erase_write` function through calls to:
1. `check_erased_range` when erasing with respect to region boundaries
2. `check_erased_range` for the entire erase block after the loop
containing verification 1 completed
3. `verify_range` when all erases/writes were complete
Verification 2 duplicated verification 1 and was orphaned by commit
fa8808595a, which dropped its paired erasefn call but missed this
related step.
Verification 3 duplicated verification which occurs in
`flashrom_image_write` based on `flashctx flags`.
Now, these 2 redundant verifications are removed to improve the
performance of `erase_write`.
This change was tested using the linux_spi programmer to erase and write
to an MT25QL512 chip.
Change-Id: I638835facd9311979c4991cc4ca41a4b9e174bd5
Signed-off-by: Carly Zlabek <carlyzlabek(a)gmail.com>
Signed-off-by: Vincent Fazio <vfazio(a)gmail.com>
---
M erasure_layout.c
1 file changed, 0 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/79354/2
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Change subject: flashrom_tester: Align WP output format with upstream
......................................................................
Patch Set 2: Code-Review+2
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Change subject: buspirate_spi: add support for hiz output with pullups=off
......................................................................
Patch Set 12:
(1 comment)
Patchset:
PS12:
David, I submitted this, congrats with the first patch. I understand you are using bispirate programmer, this is great. If you ever have more ideas, you are always welcome to send more patches!
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Change subject: buspirate_spi: add support for hiz output with pullups=off
......................................................................
buspirate_spi: add support for hiz output with pullups=off
When working with low-voltage chips, the internal 10k pull-ups
of the Bus Pirate might be too high. In such cases, it's necessary
to create an external pull-up using lower-value resistors. For this,
you can use the 'hiz' parameter. This way, the Bus Pirate will
operate as an open drain with 'pullups=off'
So, why not just use the 'pullups=on' option for this scenario? I'm
trying to prevent a very typical human error in the training sessions
I conduct.
For example, in the previous session, a user might have left the VPU
(vextern) connected to 5V, and now they need to access a 1.8V chip.
If 'pullups=on' is used, the following will happen:
5V (VPU) --> CD4060 --> 2K (internal Bus Pirate) --> MOSI target chip.
By having the option to set a 'hiz=on', this can be avoided. Since the
pull-ups will remain deactivated while the Bus Pirate will function in
an open-drain mode
Return init error for invalid values of pullups, hiz, psus. Previously,
invalid values of the params pullups, hiz, psus were handled as "off"
(i.e. disabled). This created a potential human error when users were
running flashrom with e.g. pullups=1 and expected pullups to be on,
while the value 1 was handled as invalid and off.
Change-Id: I6d9909b23782ef3fcb1428fd127dae0d6b211855
Signed-off-by: David Reguera Garcia <dreg(a)rootkit.es>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/79299
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org>
---
M buspirate_spi.c
M doc/classic_cli_manpage.rst
2 files changed, 45 insertions(+), 10 deletions(-)
Approvals:
build bot (Jenkins): Verified
Anastasia Klimchuk: Looks good to me, approved
Dreg: Looks good to me, but someone else must approve
diff --git a/buspirate_spi.c b/buspirate_spi.c
index 72c28b0..3a1e414 100644
--- a/buspirate_spi.c
+++ b/buspirate_spi.c
@@ -325,6 +325,7 @@
int spispeed = 0x7;
int serialspeed_index = -1;
int ret = 0;
+ bool hiz = false;
bool pullup = false;
bool psu = false;
bool aux = true;
@@ -370,23 +371,49 @@
tmp = extract_programmer_param_str(cfg, "pullups");
if (tmp) {
- if (strcasecmp("on", tmp) == 0)
+ if (strcasecmp("on", tmp) == 0) {
pullup = true;
- else if (strcasecmp("off", tmp) == 0)
+ } else if (strcasecmp("off", tmp) == 0) {
; // ignore
- else
- msg_perr("Invalid pullups state, not using them.\n");
+ } else {
+ msg_perr("Invalid pullups state. Use on/off.\n");
+ free(tmp);
+ return 1;
+ }
+ }
+ free(tmp);
+
+ tmp = extract_programmer_param_str(cfg, "hiz");
+ if (tmp) {
+ if (strcasecmp("on", tmp) == 0) {
+ hiz = true;
+ } else if (strcasecmp("off", tmp) == 0) {
+ if (pullup) {
+ msg_perr("Invalid combination: pullups=on & hiz=off at same time is not possible.\n");
+ free(tmp);
+ return 1;
+ } else {
+ ; // ignore
+ }
+ } else {
+ msg_perr("Invalid hiz state. Use on/off.\n");
+ free(tmp);
+ return 1;
+ }
}
free(tmp);
tmp = extract_programmer_param_str(cfg, "psus");
if (tmp) {
- if (strcasecmp("on", tmp) == 0)
+ if (strcasecmp("on", tmp) == 0) {
psu = true;
- else if (strcasecmp("off", tmp) == 0)
+ } else if (strcasecmp("off", tmp) == 0) {
; // ignore
- else
- msg_perr("Invalid psus state, not enabling.\n");
+ } else {
+ msg_perr("Invalid psus state. Use on/off.\n");
+ free(tmp);
+ return 1;
+ }
}
free(tmp);
@@ -692,9 +719,9 @@
/* Set SPI config: output type, idle, clock edge, sample */
bp_commbuf[0] = 0x80 | 0xa;
- if (pullup) {
+ if (pullup || hiz) {
bp_commbuf[0] &= ~(1 << 3);
- msg_pdbg("Pull-ups enabled, so using HiZ pin output! (Open-Drain mode)\n");
+ msg_pdbg("Pull-ups or HiZ enabled, so using HiZ pin output! (Open-Drain mode)\n");
}
ret = buspirate_sendrecv(bp_commbuf, 1, 1);
if (ret)
diff --git a/doc/classic_cli_manpage.rst b/doc/classic_cli_manpage.rst
index 5d6b7ef..0cd45ca 100644
--- a/doc/classic_cli_manpage.rst
+++ b/doc/classic_cli_manpage.rst
@@ -772,6 +772,14 @@
More information about the Bus Pirate pull-up resistors and their purpose is available
`in a guide by dangerousprototypes <http://dangerousprototypes.com/docs/Practical_guide_to_Bus_Pirate_pull-up_r…>`_.
+When working with low-voltage chips, the internal 10k pull-ups of the Bus Pirate might be too high. In such cases, it's necessary to create an external pull-up using lower-value resistors.
+
+For this, you can use the ``hiz`` parameter. This way, the Bus Pirate will operate as an open drain. Syntax is::
+
+ flashrom -p buspirate_spi:hiz=state
+
+where ``state`` can be ``on`` or ``off``.
+
The state of the Bus Pirate power supply pins is controllable through an optional ``psus`` parameter. Syntax is::
flashrom -p buspirate_spi:psus=state
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Change subject: tree: rename sb600spi.c to amd_spi.c
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
I have rebased on head and combined together two chains with amd patches, so it should be ready for testing... I need help with testing! (can be tested at the end of the chain)
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Change subject: tree: Update 'sb600' references to 'amd'
......................................................................
Patch Set 2:
(1 comment)
File amd_spi.c:
https://review.coreboot.org/c/flashrom/+/74953/comment/7b5eb5a8_ee92af7f :
PS1, Line 156: amd_spibar
> Minor: Since these function parameters are stack local to the working function, how about just dropp […]
I think it's a good idea, would you agree if I do it later in another patch? It's much easier to review this patch when it changes all sb600 into amd.
But I agree with you idea.
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Anastasia Klimchuk has uploaded a new patch set (#3) to the change originally created by Edward O'Callaghan. ( https://review.coreboot.org/c/flashrom/+/65238?usp=email )
Change subject: amd_spi.c: Combine CHIPSET_YANGTZE and CHIPSET_PROMONTORY
......................................................................
amd_spi.c: Combine CHIPSET_YANGTZE and CHIPSET_PROMONTORY
Both `CHIPSET_YANGTZE` and `CHIPSET_PROMONTORY` are simply
the SPI100 ctrl ip core therefore combine them.
BUG=b:228502547
https://ticket.coreboot.org/issues/370
Change-Id: I6a3fcc23c1e5fbe5d9e365e2e5f864655aee873f
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M amd_spi.c
1 file changed, 14 insertions(+), 53 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/38/65238/3
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