December 2023 - flashrom-gerrit

[S] Change in flashrom[main]: flashchips: Add write-protect support for GD25LQ255E
by Hsuan-ting Chen (Code Review) 27 Dec '23

27 Dec '23

Attention is currently required from: Anastasia Klimchuk, David Wu, Kapil Porwal, Lean Sheng Tan, Nikolai Artemiev, Tyler Wang. Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/79460?usp=email ) Change subject: flashchips: Add write-protect support for GD25LQ255E ...................................................................... Patch Set 5: Code-Review+2 (1 comment) File flashchips.c: https://review.coreboot.org/c/flashrom/+/79460/comment/5103dae7_ab328104 : PS5, Line 6559: FEATURE_WRSR2 So if I understand it correctly, (1) we shouldn't add `FEATURE_WRSR2` here (2) But it is okay since when `FEATURE_WRSR_EXT2` is configured, the value of FEATURE_WRSR2 will be ignored. But please still remove this. (And try if it still works) Thanks! -- To view, visit https://review.coreboot.org/c/flashrom/+/79460?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I1425e931433c00caceaabc6037a79099d6d5eac5 Gerrit-Change-Number: 79460 Gerrit-PatchSet: 5 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 27 Dec 2023 07:58:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in flashrom[main]: flashchips: Add GD25LQ255E
by Hsuan-ting Chen (Code Review) 27 Dec '23

27 Dec '23

Attention is currently required from: Anastasia Klimchuk, David Wu, Kapil Porwal, Maximilian Brune, Nikolai Artemiev, Subrata Banik, Tyler Wang. Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/79088?usp=email ) Change subject: flashchips: Add GD25LQ255E ...................................................................... Patch Set 9: (1 comment) File flashchips.c: https://review.coreboot.org/c/flashrom/+/79088/comment/e3a58264_4b7d8e6a : PS9, Line 6559: FEATURE_WRSR_EXT2 > So the question is between `FEATURE_WRSR_EXT2` and `FEATURE_WRSR2`. […] I tried to learn from the current code and Nikolai's first commit: https://review.coreboot.org/c/flashrom/+/58570 Here's my understanding: There are two way of implemention write to status register 2: --- #### 1. FEATURE_WRSR2： See the code piece: ``` if (feature_bits & FEATURE_WRSR2) { write_cmd[0] = JEDEC_WRSR2; write_cmd[1] = value; write_cmd_len = JEDEC_WRSR2_OUTSIZE; break; } ``` This means that it has seperated instruction to write SR2, take AT25SL128A as an example, see datasheet: https://pdf1.alldatasheet.com/datasheet-pdf/download/1283751/DIALOG/AT25SL1… Page 21 (7.7 Write Status Register-2 (31h)) explicitly describe that they have 0x31 (JEDEC_WRSR2, see include/spi.h) to write SR2. --- #### 2. FEATURE_WRSR_EXT2 (was FEATURE_WRSR_EXT) See the code piece: ``` if (feature_bits & FEATURE_WRSR_EXT) { /* * Writing SR2 with an extended WRSR command requires * writing SR1 along with SR2, so just read SR1 and * write it back */ uint8_t sr1; if (spi_read_register(flash, STATUS1, &sr1)) { msg_cerr("Writing SR2 failed: failed to read SR1 for writeback.\n"); return 1; } write_cmd[0] = JEDEC_WRSR; write_cmd[1] = sr1; write_cmd[2] = value; write_cmd_len = JEDEC_WRSR_EXT_OUTSIZE; break; } ``` It means it concat the SR2 after SR1, and if we take a look at GD25LQ255E datasheet (https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20221129/DS-0…), page 18 table 10: Write Status Register 1&2: * Byte 1: 01H * Byte 2: S7-S0 (SR 1) * Byte 3: S15-S8 (SR 2) We can see that GD25LQ255E support that concat SR 2 value directly after SR 1 value, which aligns with our FEATURE_WRSR_EXT2. --- Similarly, we could see that W25Q512NW datasheet: https://www.mouser.com/datasheet/2/949/Winbond_07022021_W25Q512NW-2451091.p… is FEATURE_WRSR3 since 8.2.5 (page 33) shows that it has Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) and S25FL128L datasheet: https://www.infineon.com/dgdl/Infineon-S25FL256L_S25FL128L_256-MB_(32-MB)_1… is FEATURE_WRSR_EXT3 since 8.3.4 (page 81) shows that they just concat SR2, SR3 after SR1 while writing. -- To view, visit https://review.coreboot.org/c/flashrom/+/79088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0d780255ed6772f4aa406584acf071a7ddd6da47 Gerrit-Change-Number: 79088 Gerrit-PatchSet: 9 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 27 Dec 2023 06:21:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in flashrom[main]: Add Idaville platform into chipset enable list and add update IRC reg...
by Kevin Yu (Code Review) 25 Dec '23

25 Dec '23

Attention is currently required from: Anastasia Klimchuk, Angel Pons. Kevin Yu has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/79340?usp=email ) Change subject: Add Idaville platform into chipset enable list and add update IRC region support ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Hi Angle Pons Can you help reeview this code? Thanks Kevin Yu -- To view, visit https://review.coreboot.org/c/flashrom/+/79340?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Icc526b22a9efc8071e972bb1d8cfc51d6a83651b Gerrit-Change-Number: 79340 Gerrit-PatchSet: 6 Gerrit-Owner: Kevin Yu <ykevin(a)celestica.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 25 Dec 2023 01:41:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in flashrom[main]: flashchips: Add GD25LQ255E
by Anastasia Klimchuk (Code Review) 22 Dec '23

22 Dec '23

Attention is currently required from: David Wu, Kapil Porwal, Maximilian Brune, Nikolai Artemiev, Subrata Banik, Tyler Wang. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/79088?usp=email ) Change subject: flashchips: Add GD25LQ255E ...................................................................... Patch Set 9: (2 comments) File flashchips.c: https://review.coreboot.org/c/flashrom/+/79088/comment/54e1b41a_6d593b81 : PS9, Line 6559: FEATURE_WRSR_EXT2 > Umm.. I was refer to funciton spi_prepare_wrsr_ext(): […] So the question is between `FEATURE_WRSR_EXT2` and `FEATURE_WRSR2`. In reality your next patch CB:79460 needs this, when you get to testing. Nikolai maybe you can help us with this? Thank you! (I will get back to this after holidays) https://review.coreboot.org/c/flashrom/+/79088/comment/e40a7934_d83dbde8 : PS9, Line 6595: 1695, 1950 > I was reference GD25LQ128E settings. The datasheet says `Full voltage range: 1.65-2. […] Okay I see that the other chip has the same range too. Let's leave it for now, but maybe any of other reviewers knows why reducing the voltage range might be needed? -- To view, visit https://review.coreboot.org/c/flashrom/+/79088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0d780255ed6772f4aa406584acf071a7ddd6da47 Gerrit-Change-Number: 79088 Gerrit-PatchSet: 9 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 22 Dec 2023 09:12:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in flashrom[main]: flashrom_tester: Drop technical debt
by Edward O'Callaghan (Code Review) 21 Dec '23

21 Dec '23

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/79303?usp=email ) Change subject: flashrom_tester: Drop technical debt ...................................................................... flashrom_tester: Drop technical debt Drop `-p host` ChromeOS miss-feature and use `-p internal` instead. BUG=b:296978620 BRANCH=none TEST=run flashrom-tester with newer flashrom Change-Id: I1ea174c1760fee3e41a2ef0e9779badf0c51298d Signed-off-by: roccochen(a)chromium.com <roccochen(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/79303 Reviewed-by: Evan Benn <evanbenn(a)gmail.com> Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Bob Moragues <moragues(a)google.com> --- M util/flashrom_tester/flashrom/src/lib.rs M util/flashrom_tester/src/main.rs M util/flashrom_tester/src/tests.rs 3 files changed, 7 insertions(+), 7 deletions(-) Approvals: Evan Benn: Looks good to me, but someone else must approve Nick Vaccaro: Looks good to me, but someone else must approve David Wu: Looks good to me, but someone else must approve Edward O'Callaghan: Looks good to me, approved build bot (Jenkins): Verified Bob Moragues: Looks good to me, but someone else must approve diff --git a/util/flashrom_tester/flashrom/src/lib.rs b/util/flashrom_tester/flashrom/src/lib.rs index 41393e8..e2c9149 100644 --- a/util/flashrom_tester/flashrom/src/lib.rs +++ b/util/flashrom_tester/flashrom/src/lib.rs @@ -51,19 +51,19 @@ #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum FlashChip { - HOST, + INTERNAL, } impl FlashChip { pub fn from(s: &str) -> Result<FlashChip, &str> { match s { - "host" => Ok(FlashChip::HOST), + "internal" => Ok(FlashChip::INTERNAL), _ => Err("cannot convert str to enum"), } } pub fn to(fc: FlashChip) -> &'static str { match fc { - FlashChip::HOST => "host", + FlashChip::INTERNAL => "internal", } } @@ -80,7 +80,7 @@ /// disabled. pub fn can_control_hw_wp(&self) -> bool { match self { - FlashChip::HOST => true, + FlashChip::INTERNAL => true, } } } diff --git a/util/flashrom_tester/src/main.rs b/util/flashrom_tester/src/main.rs index b8a2581..3035ae5 100644 --- a/util/flashrom_tester/src/main.rs +++ b/util/flashrom_tester/src/main.rs @@ -82,7 +82,7 @@ .arg( Arg::with_name("ccd_target_type") .required(true) - .possible_values(&["host"]), + .possible_values(&["internal"]), ) .arg( Arg::with_name("print-layout") diff --git a/util/flashrom_tester/src/tests.rs b/util/flashrom_tester/src/tests.rs index 721a789..d1e9d61 100644 --- a/util/flashrom_tester/src/tests.rs +++ b/util/flashrom_tester/src/tests.rs @@ -219,8 +219,8 @@ /// is actually able to write to the Flash. This only makes sense for chips /// running Coreboot, which we assume is just host. fn elog_sanity_test(env: &mut TestEnv) -> TestResult { - if env.chip_type() != FlashChip::HOST { - info!("Skipping ELOG sanity check for non-host chip"); + if env.chip_type() != FlashChip::INTERNAL { + info!("Skipping ELOG sanity check for non-internal chip"); return Ok(()); } // flash should be back in the golden state -- To view, visit https://review.coreboot.org/c/flashrom/+/79303?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I1ea174c1760fee3e41a2ef0e9779badf0c51298d Gerrit-Change-Number: 79303 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Evan Benn <evanbenn(a)gmail.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in flashrom[main]: Add Idaville platform into chipset enable list and add update IRC reg...
by Kevin Yu (Code Review) 21 Dec '23

21 Dec '23

Attention is currently required from: Anastasia Klimchuk. Kevin Yu has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/79340?usp=email ) Change subject: Add Idaville platform into chipset enable list and add update IRC region support ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Hi Anastasia Klimchuk Any concern with you? Thanks -- To view, visit https://review.coreboot.org/c/flashrom/+/79340?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Icc526b22a9efc8071e972bb1d8cfc51d6a83651b Gerrit-Change-Number: 79340 Gerrit-PatchSet: 6 Gerrit-Owner: Kevin Yu <ykevin(a)celestica.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 21 Dec 2023 00:54:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in flashrom[main]: flashchips: Remove Macronix MX25U25635F from chip list
by DZ (Code Review) 21 Dec '23

21 Dec '23

DZ has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/79633?usp=email ) Change subject: flashchips: Remove Macronix MX25U25635F from chip list ...................................................................... flashchips: Remove Macronix MX25U25635F from chip list The MX25U25643G has same ID as MX25U25635F, and the former one is the next generation of the latter. Therefore, we replace it with MX25U25643G and backward compatible. We have tested read/write/erase and write protection function for MX25U25643G. MX25U25643G datasheet is available at the following URL: https://www.mxic.com.tw/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/spe… MX25U25635F datasheet is available at the following URL: https://www.macronix.com/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/sp… Change-Id: Ief3fd7641bed817066692c4abffff6d3b0df16b9 Signed-off-by: danielzhang <danielzhang(a)mxic.com.cn> --- M flashchips.c M include/flashchips.h 2 files changed, 2 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/33/79633/1 diff --git a/flashchips.c b/flashchips.c index a4605bd..8ae2680 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10257,59 +10257,10 @@ { .vendor = "Macronix", - .name = "MX25U25635F", - .bustype = BUS_SPI, - .manufacture_id = MACRONIX_ID, - .model_id = MACRONIX_MX25U25635F, - .total_size = 32768, - .page_size = 256, - /* OTP: 512B total; enter 0xB1, exit 0xC1 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_4BA, - .tested = TEST_OK_PREW, - .probe = PROBE_SPI_RDID, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {4 * 1024, 8192} }, - .block_erase = SPI_BLOCK_ERASE_21, - }, { - .eraseblocks = { {4 * 1024, 8192} }, - .block_erase = SPI_BLOCK_ERASE_20, - }, { - .eraseblocks = { {32 * 1024, 1024} }, - .block_erase = SPI_BLOCK_ERASE_5C, - }, { - .eraseblocks = { {32 * 1024, 1024} }, - .block_erase = SPI_BLOCK_ERASE_52, - }, { - .eraseblocks = { {64 * 1024, 512} }, - .block_erase = SPI_BLOCK_ERASE_DC, - }, { - .eraseblocks = { {64 * 1024, 512} }, - .block_erase = SPI_BLOCK_ERASE_D8, - }, { - .eraseblocks = { {32 * 1024 * 1024, 1} }, - .block_erase = SPI_BLOCK_ERASE_60, - }, { - .eraseblocks = { {32 * 1024 * 1024, 1} }, - .block_erase = SPI_BLOCK_ERASE_C7, - } - }, - /* TODO: security register */ - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */ - .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, - .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ - .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ - .voltage = {1650, 2000}, - }, - - { - .vendor = "Macronix", .name = "MX25U25643G", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, - .model_id = MACRONIX_MX25U25635F, + .model_id = MACRONIX_MX25U25643G, .total_size = 32768, .page_size = 256, /* OTP: 512B total; enter 0xB1, exit 0xC1 */ diff --git a/include/flashchips.h b/include/flashchips.h index 17a6fc4..654196f 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -529,7 +529,7 @@ #define MACRONIX_MX25U3235E 0x2536 /* Same as MX25U6435F */ #define MACRONIX_MX25U6435E 0x2537 /* Same as MX25U6435F */ #define MACRONIX_MX25U12835E 0x2538 /* Same as MX25U12835F */ -#define MACRONIX_MX25U25635F 0x2539 /* Same as MX25U25643G */ +#define MACRONIX_MX25U25643G 0x2539 #define MACRONIX_MX25U51245G 0x253a #define MACRONIX_MX25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */ #define MACRONIX_MX25L6495F 0x9517 -- To view, visit https://review.coreboot.org/c/flashrom/+/79633?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ief3fd7641bed817066692c4abffff6d3b0df16b9 Gerrit-Change-Number: 79633 Gerrit-PatchSet: 1 Gerrit-Owner: DZ Gerrit-MessageType: newchange

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[S] Change in flashrom[main]: flashchips: Add GD25LQ255E
by Tyler Wang (Code Review) 19 Dec '23

19 Dec '23

Attention is currently required from: Anastasia Klimchuk, David Wu, Kapil Porwal, Maximilian Brune, Nikolai Artemiev, Subrata Banik. Tyler Wang has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/79088?usp=email ) Change subject: flashchips: Add GD25LQ255E ...................................................................... Patch Set 9: (1 comment) File flashchips.c: https://review.coreboot.org/c/flashrom/+/79088/comment/b3fed484_bbc55af6 : PS9, Line 6559: FEATURE_WRSR_EXT2 > Also for my education: how do I find out from datasheet that FEATURE_WRSR_EXT2 is supported? Thank y […] Umm.. I was refer to funciton spi_prepare_wrsr_ext(): ``` /* * Writing SR2 or higher with an extended WRSR command requires * writing all lower SRx along with it, so just read the lower * SRx and write them back. */ ``` If it has SR2(or higher), FEATURE_WRSR_EXT2 is needed. But after check the code again, I think my opinion is incorrect. Do you know how to check FEATURE_WRSR_EXT2 is supported? -- To view, visit https://review.coreboot.org/c/flashrom/+/79088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0d780255ed6772f4aa406584acf071a7ddd6da47 Gerrit-Change-Number: 79088 Gerrit-PatchSet: 9 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Tue, 19 Dec 2023 05:14:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in flashrom[main]: flashchips: Add GD25LQ255E
by Tyler Wang (Code Review) 19 Dec '23

19 Dec '23

Attention is currently required from: Anastasia Klimchuk, David Wu, Kapil Porwal, Maximilian Brune, Nikolai Artemiev, Subrata Banik. Tyler Wang has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/79088?usp=email ) Change subject: flashchips: Add GD25LQ255E ...................................................................... Patch Set 9: (1 comment) File flashchips.c: https://review.coreboot.org/c/flashrom/+/79088/comment/0b1d2293_689b3985 : PS9, Line 6595: 1695, 1950 > Just for my education: the datasheet says `Full voltage range: 1.65-2. […] I was reference GD25LQ128E settings. The datasheet says `Full voltage range: 1.65-2.0V`, which is same as GD25LQ255E. So I use the same voltage settings. Shall we set the voltage setting to `{1650, 2000}`? GD25LQ128E datasheet: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230926/DS-0… -- To view, visit https://review.coreboot.org/c/flashrom/+/79088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0d780255ed6772f4aa406584acf071a7ddd6da47 Gerrit-Change-Number: 79088 Gerrit-PatchSet: 9 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Tue, 19 Dec 2023 02:54:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in flashrom[main]: Add Idaville platform into chipset enable list and add update IRC reg...
by Kevin Yu (Code Review) 19 Dec '23

19 Dec '23

Attention is currently required from: Anastasia Klimchuk. Kevin Yu has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/79340?usp=email ) Change subject: Add Idaville platform into chipset enable list and add update IRC region support ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Hi Anastasia Klimchuk Can you help review this ticket? Thanks -- To view, visit https://review.coreboot.org/c/flashrom/+/79340?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Icc526b22a9efc8071e972bb1d8cfc51d6a83651b Gerrit-Change-Number: 79340 Gerrit-PatchSet: 6 Gerrit-Owner: Kevin Yu <ykevin(a)celestica.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Tue, 19 Dec 2023 01:52:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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