Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/71621 )
Change subject: internal.c: Have preinit hook do cpu and bus init
......................................................................
internal.c: Have preinit hook do cpu and bus init
This is to work towards a internal programmers phased construction
and initalisation. Unlike other programmers the internal one is a
special case that needs to initalise other parts of the system to
make internal programming possible as well as detection of parts
and finally special case handling of failure modes.
Change-Id: Ia1cfd89a4fccfa07ba3c9ee1f6df1422ab95fc76
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M internal.c
1 file changed, 31 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/71621/1
diff --git a/internal.c b/internal.c
index 07b63b4..bf41508 100644
--- a/internal.c
+++ b/internal.c
@@ -174,6 +174,21 @@
*/
internal_buses_supported = BUS_NONSPI;
+ /* Initialize PCI access for flash enables */
+ if (pci_init_common()) {
+ return 1;
+ }
+
+ if (processor_flash_enable()) {
+ msg_perr("Processor detection/init failed.\nAborting.\n");
+ return 1;
+ }
+
+#if defined(__i386__) || defined(__x86_64__)
+ is_laptop = 2; /* Assume that we don't know by default. */
+ dmi_init();
+#endif
+
return 0;
}
@@ -232,19 +247,6 @@
goto internal_init_exit;
}
- /* Initialize PCI access for flash enables */
- if (pci_init_common() != 0) {
- ret = 1;
- goto internal_init_exit;
- }
-
- if (processor_flash_enable()) {
- msg_perr("Processor detection/init failed.\n"
- "Aborting.\n");
- ret = 1;
- goto internal_init_exit;
- }
-
#if defined(__i386__) || defined(__x86_64__)
if (rget_io_perms()) {
ret = 1;
@@ -264,10 +266,6 @@
}
}
- is_laptop = 2; /* Assume that we don't know by default. */
-
- dmi_init();
-
/* In case Super I/O probing would cause pretty explosions. */
board_handle_before_superio();
--
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: Ia1cfd89a4fccfa07ba3c9ee1f6df1422ab95fc76
Gerrit-Change-Number: 71621
Gerrit-PatchSet: 1
Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org>
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Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/71578 )
Change subject: internal.c: Factor out laptop alerts into helper func
......................................................................
internal.c: Factor out laptop alerts into helper func
Minor however a unfortant '_' suffix is temporarily needed
to skirt around global variable shadowing.
Change-Id: I8eea91012e6539b4fdf5d49a75a9cb48bb8a57ca
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M internal.c
1 file changed, 45 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/71578/1
diff --git a/internal.c b/internal.c
index 38a8405..cdc6f7b 100644
--- a/internal.c
+++ b/internal.c
@@ -164,6 +164,37 @@
return 0;
}
+// FIXME: remove '_' suffix once global shadowing is fixed.
+static void report_nonwl_laptop_detected(int is_laptop_, bool laptop_ok_)
+{
+ /* Report if a non-whitelisted laptop is detected that likely uses a legacy bus. */
+ if (is_laptop_ && !laptop_ok_) {
+ msg_pinfo("========================================================================\n");
+ if (is_laptop_ == 1) {
+ msg_pinfo("You seem to be running flashrom on an unknown laptop. Some\n"
+ "internal buses have been disabled for safety reasons.\n\n");
+ } else {
+ msg_pinfo("You may be running flashrom on an unknown laptop. We could not\n"
+ "detect this for sure because your vendor has not set up the SMBIOS\n"
+ "tables correctly. Some internal buses have been disabled for\n"
+ "safety reasons. You can enforce using all buses by adding\n"
+ " -p internal:laptop=this_is_not_a_laptop\n"
+ "to the command line, but please read the following warning if you\n"
+ "are not sure.\n\n");
+ }
+ msg_perr("Laptops, notebooks and netbooks are difficult to support and we\n"
+ "recommend to use the vendor flashing utility. The embedded controller\n"
+ "(EC) in these machines often interacts badly with flashing.\n"
+ "See the manpage and https://flashrom.org/Laptops for details.\n\n"
+ "If flash is shared with the EC, erase is guaranteed to brick your laptop\n"
+ "and write may brick your laptop.\n"
+ "Read and probe may irritate your EC and cause fan failure, backlight\n"
+ "failure and sudden poweroff.\n"
+ "You have been warned.\n"
+ "========================================================================\n");
+ }
+}
+
static int internal_init(const struct programmer_cfg *cfg)
{
int ret = 0;
@@ -283,32 +314,7 @@
if (internal_buses_supported & BUS_NONSPI)
register_par_master(&par_master_internal, internal_buses_supported, NULL);
- /* Report if a non-whitelisted laptop is detected that likely uses a legacy bus. */
- if (is_laptop && !laptop_ok) {
- msg_pinfo("========================================================================\n");
- if (is_laptop == 1) {
- msg_pinfo("You seem to be running flashrom on an unknown laptop. Some\n"
- "internal buses have been disabled for safety reasons.\n\n");
- } else {
- msg_pinfo("You may be running flashrom on an unknown laptop. We could not\n"
- "detect this for sure because your vendor has not set up the SMBIOS\n"
- "tables correctly. Some internal buses have been disabled for\n"
- "safety reasons. You can enforce using all buses by adding\n"
- " -p internal:laptop=this_is_not_a_laptop\n"
- "to the command line, but please read the following warning if you\n"
- "are not sure.\n\n");
- }
- msg_perr("Laptops, notebooks and netbooks are difficult to support and we\n"
- "recommend to use the vendor flashing utility. The embedded controller\n"
- "(EC) in these machines often interacts badly with flashing.\n"
- "See the manpage and https://flashrom.org/Laptops for details.\n\n"
- "If flash is shared with the EC, erase is guaranteed to brick your laptop\n"
- "and write may brick your laptop.\n"
- "Read and probe may irritate your EC and cause fan failure, backlight\n"
- "failure and sudden poweroff.\n"
- "You have been warned.\n"
- "========================================================================\n");
- }
+ report_nonwl_laptop_detected(is_laptop, laptop_ok);
ret = 0;
--
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Gerrit-Project: flashrom
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Gerrit-Change-Id: I8eea91012e6539b4fdf5d49a75a9cb48bb8a57ca
Gerrit-Change-Number: 71578
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Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/71577 )
Change subject: internal.c: Move sio register to own object
......................................................................
internal.c: Move sio register to own object
While super i/o is related to the internal programmer it
isn't actually _the_ internal programmer. Move register
logic to its own object consistent with other programmer
types.
Change-Id: I9a4c3e12bce5d22492c8d1b8f4a3f49d736dcf31
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M Makefile
M internal.c
M meson.build
A superio.c
4 files changed, 59 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/71577/1
diff --git a/Makefile b/Makefile
index 425b58c..cf3150b 100644
--- a/Makefile
+++ b/Makefile
@@ -583,7 +583,7 @@
ifeq ($(CONFIG_INTERNAL) $(CONFIG_INTERNAL_X86), yes yes)
FEATURE_FLAGS += -D'CONFIG_INTERNAL=1'
PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o \
- internal.o it87spi.o sb600spi.o amd_imc.o wbsio_spi.o mcp6x_spi.o \
+ internal.o it87spi.o sb600spi.o superio.o amd_imc.o wbsio_spi.o mcp6x_spi.o \
ichspi.o dmi.o known_boards.o
endif
else
diff --git a/internal.c b/internal.c
index 9b80f37..38a8405 100644
--- a/internal.c
+++ b/internal.c
@@ -35,34 +35,6 @@
enum chipbustype internal_buses_supported = BUS_NONE;
-#if defined(__i386__) || defined(__x86_64__)
-void probe_superio(void)
-{
- probe_superio_winbond();
- /* ITE probe causes SMSC LPC47N217 to power off the serial UART.
- * Always probe for SMSC first, and if a SMSC Super I/O is detected
- * at a given I/O port, do _not_ probe that port with the ITE probe.
- * This means SMSC probing must be done before ITE probing.
- */
- //probe_superio_smsc();
- probe_superio_ite();
-}
-
-int superio_count = 0;
-#define SUPERIO_MAX_COUNT 3
-
-struct superio superios[SUPERIO_MAX_COUNT];
-
-int register_superio(struct superio s)
-{
- if (superio_count == SUPERIO_MAX_COUNT)
- return 1;
- superios[superio_count++] = s;
- return 0;
-}
-
-#endif
-
static void internal_chip_writeb(const struct flashctx *flash, uint8_t val,
chipaddr addr)
{
diff --git a/meson.build b/meson.build
index 27a284e..1cafdcb 100644
--- a/meson.build
+++ b/meson.build
@@ -247,6 +247,7 @@
'internal.c',
'it87spi.c',
'sb600spi.c',
+ 'superio.c',
'amd_imc.c',
'wbsio_spi.c',
'mcp6x_spi.c',
diff --git a/superio.c b/superio.c
new file mode 100644
index 0000000..3121578
--- /dev/null
+++ b/superio.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the flashrom project.
+ *
+ * Copyright (C) 2009 Carl-Daniel Hailfinger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "programmer.h"
+
+int superio_count = 0;
+#define SUPERIO_MAX_COUNT 3
+
+struct superio superios[SUPERIO_MAX_COUNT];
+
+int register_superio(struct superio s)
+{
+ if (superio_count == SUPERIO_MAX_COUNT)
+ return 1;
+ superios[superio_count++] = s;
+ return 0;
+}
+
+void probe_superio(void)
+{
+ probe_superio_winbond();
+ /* ITE probe causes SMSC LPC47N217 to power off the serial UART.
+ * Always probe for SMSC first, and if a SMSC Super I/O is detected
+ * at a given I/O port, do _not_ probe that port with the ITE probe.
+ * This means SMSC probing must be done before ITE probing.
+ */
+ //probe_superio_smsc();
+ probe_superio_ite();
+}
--
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/71206 )
Change subject: flashchips: Remove FEATURE_4BA_WREN for MT25QL128 and mark as tested
......................................................................
Patch Set 3: Code-Review+2
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Change subject: flashrom.c: Guard against sending spi commands on non-spi mst
......................................................................
Patch Set 1:
(1 comment)
File flashrom.c:
https://review.coreboot.org/c/flashrom/+/71269/comment/000f2c2a_7211e799
PS1, Line 1937: spi_master_no_4ba_modes
Wouldn't it make more sense to add the bustype check inside this function?
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Change subject: sb600spi.c: Move promontory code into a mmap_read=yes mode
......................................................................
Patch Set 2: Code-Review+1
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