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Change subject: rust: Add license and other metadata to Cargo.toml
......................................................................
Patch Set 1: Code-Review+1
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Change subject: programmer.h: Guard against sending spi commands on non-spi mst
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
I also ran into this issue and can confirm that this fixes it, W25Q256FV on Coffee Lake. Thanks Edward!
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Change subject: programmer.h: Guard against sending spi commands on non-spi mst
......................................................................
Patch Set 2:
(1 comment)
File flashrom.c:
https://review.coreboot.org/c/flashrom/+/71269/comment/79edb5d5_14e8c830
PS1, Line 1937: spi_master_no_4ba_modes
> Wouldn't it make more sense to add the bustype check inside this function?
sort of but not really. This is a chip bustype check not a master bustype check.
Adding a predicate to `spi_master_no_4ba_modes()` is not related to preventing the subsequent calls to `spi_{enter,exit}_4ba()`.
I think what you are asking for is a `spi_chip_4ba()` func which I have now done?
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Hello Felix Singer, build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/71269
to look at the new patch set (#2).
Change subject: programmer.h: Guard against sending spi commands on non-spi mst
......................................................................
programmer.h: Guard against sending spi commands on non-spi mst
Validate (flash->chip->bustype == BUS_SPI) as ich copies the
chip flags in the opaque master and tries incorrectly
to issue 4BA commands which results in failure.
The issue was detected only in the case of chips >16MB, in
this case 'W25Q256FV' that has the feature bits:
```
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN |
FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ |
FEATURE_WRSR2,
```
The regression was noticed from,
commit 0741727925b841c2479b993204ce58c5eb75185a ichspi.c: Read chip ID and use it to populate `flash->chip`
TEST=In the case of 'W25Q256FV' on TigerLake.
Change-Id: I7cce4f9c032d33c01bf616e27a50b9727a40fe1b
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M flashrom.c
M include/programmer.h
2 files changed, 33 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/69/71269/2
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Change subject: sb600spi.c: Move promontory code into a mmap_read=yes mode
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/71565/comment/70f0f78d_8675d2de
PS2, Line 10: This is not
: hardware specific
I believe it is hardware specific to controllers after a certain generation. i.e., supported on SPI100 controllers (Zen etc) however not supported on pre-SPI100 controllers was my understanding.
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Change subject: chipset_enable.c: Add TL UP3 and UP4/Y id's
......................................................................
Patch Set 1:
(1 comment)
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/71576/comment/acd6174a_b5a5ac11
PS1, Line 2083: {0x8086, 0xa083, B_S, DEP, "Intel", "Tiger Lake U Premium 3", enable_flash_pch500},
> As far as I can tell, 0xa083 isn't used after all, so we don't need to add this.
Let's keep it, but mark it as untested (change `DEP` to `NT`).
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Change subject: chipset_enable.c: Add TL UP3 and UP4/Y id's
......................................................................
Patch Set 1:
(2 comments)
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/71576/comment/339e3db0_c567540c
PS1, Line 2083: {0x8086, 0xa083, B_S, DEP, "Intel", "Tiger Lake U Premium 3", enable_flash_pch500},
As far as I can tell, 0xa083 isn't used after all, so we don't need to add this.
https://review.coreboot.org/c/flashrom/+/71576/comment/d1f3ec48_db6bf680
PS1, Line 2084: U Premium 4/Y
If we follow the final naming scheme this should be "Tiger Lake Premium UP4". If we follow earlier platforms, and the coreboot scheme, then "Tiger Lake Y Premium".
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Change subject: internal.c: Do cb_parse_table() in preinit
......................................................................
Patch Set 1:
(1 comment)
File include/programmer.h:
https://review.coreboot.org/c/flashrom/+/71624/comment/2a1d035a_2b63228f
PS1, Line 35: struct {
: const char *cb_vendor;
: const char *cb_model;
: } internal;
This should be a programmer-defined opaque struct, pointed to by `struct programmer_cfg`.
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Change subject: board_enables: Couple prog cfg with board cfg
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
It's hard to say if all the plumbing is needed, but no idea how to make it better.
File internal.c:
https://review.coreboot.org/c/flashrom/+/71623/comment/e1b8040f_e61d8481
PS1, Line 270: board_handle_before_superio((struct programmer_cfg *)cfg);
Ugh, it'd be better to avoid casting away const... Quick solution would be to make a mutable local copy:
struct programmer_cfg mut_cfg = *cfg;
Then use `&mut_cfg` as argument instead of `(struct programmer_cfg *)cfg`.
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