[S] Change in flashrom[master]: chipset_enable.c: Add TL UP3 and UP4/Y id's
Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/71576 ) Change subject: chipset_enable.c: Add TL UP3 and UP4/Y id's ...................................................................... chipset_enable.c: Add TL UP3 and UP4/Y id's As listed in coreboot source under src/include/device/pci_ids.h BUG=b:227393555 BRANCH=none TEST=ran --flash-name on TLK machine. Change-Id: I77120612f7a770ae1319f4cd82913fa465f355f5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> --- M chipset_enable.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/76/71576/1 diff --git a/chipset_enable.c b/chipset_enable.c index b9144d1..5cf9256 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2080,6 +2080,8 @@ {0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400}, {0x8086, 0x0285, B_S, DEP, "Intel", "Comet Lake U Base", enable_flash_pch400}, {0x8086, 0xa082, B_S, DEP, "Intel", "Tiger Lake U Premium", enable_flash_pch500}, + {0x8086, 0xa083, B_S, DEP, "Intel", "Tiger Lake U Premium 3", enable_flash_pch500}, + {0x8086, 0xa087, B_S, DEP, "Intel", "Tiger Lake U Premium 4/Y", enable_flash_pch500}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, {0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100}, -- To view, visit https://review.coreboot.org/c/flashrom/+/71576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I77120612f7a770ae1319f4cd82913fa465f355f5 Gerrit-Change-Number: 71576 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec@chromium.org> Gerrit-MessageType: newchange
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Edward O'Callaghan (Code Review)