Attention is currently required from: Daniel Verkamp, Edward O'Callaghan, Angel Pons.
Hello build bot (Jenkins), Daniel Verkamp, Edward O'Callaghan, Angel Pons,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/flashrom/+/67844
to review the following change.
Change subject: pcidev.c: populate IDs with pci_fill_info()
......................................................................
pcidev.c: populate IDs with pci_fill_info()
With pciutils 3.7.0, flashrom is unable to match any PCI devices by
vendor/device ID because the vendor_id and device_id fields of struct
pci_dev are not filled in.
Call pci_fill_info() to request these identifiers before trying to match
them against the supported device list.
The pciutils ChangeLog for 3.7.0 mentions that the documentation and
back-end behavior for pci_fill_info() was updated; it seems that a call
to pci_fill_info() was always intended to be required, but some backends
(such as the sysfs one used on Linux) would fill the identifier fields
even when not requested by the user. The pci_fill_info() function and
the PCI_FILL_IDENT flag have been available for all versions of pciutils
since at least 2.0 from 1999, so it should be safe to add without any
version checks.
With this change, reading/writing a nicintel_spi boot ROM is successful.
Signed-off-by: Daniel Verkamp <dverkamp(a)chromium.org>
Change-Id: Ia011d4d801f8a54160e45a70b14b740e6dcc00ef
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46310
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M pcidev.c
1 file changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/44/67844/1
diff --git a/pcidev.c b/pcidev.c
index f4e5542..4bc32c1 100644
--- a/pcidev.c
+++ b/pcidev.c
@@ -211,6 +211,7 @@
for (dev = pacc->devices; dev; dev = dev->next) {
if (pci_filter_match(&filter, dev)) {
+ pci_fill_info(dev, PCI_FILL_IDENT);
/* Check against list of supported devices. */
for (i = 0; devs[i].device_name != NULL; i++)
if ((dev->vendor_id == devs[i].vendor_id) &&
--
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Gerrit-Change-Id: Ia011d4d801f8a54160e45a70b14b740e6dcc00ef
Gerrit-Change-Number: 67844
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Attention is currently required from: Sam McNally, Edward O'Callaghan, Angel Pons.
Hello Sam McNally, build bot (Jenkins), Edward O'Callaghan, Angel Pons,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/flashrom/+/67842
to review the following change.
Change subject: chipset_enable.c: check return value from rphysmap() call
......................................................................
chipset_enable.c: check return value from rphysmap() call
Port from the ChromiumOS fork of flashrom.
Change-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46444
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Sam McNally <sammc(a)google.com>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M chipset_enable.c
1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/42/67842/1
diff --git a/chipset_enable.c b/chipset_enable.c
index 3437792..67ce761 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -934,6 +934,8 @@
uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00;
msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase);
void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */
+ if (spibar == ERROR_PTR)
+ return ERROR_FATAL;
/* Enable Flash Writes.
* Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C).
--
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Attention is currently required from: Stefan Reinauer, Edward O'Callaghan, SANTHOSH JANARDHANA HASSAN.
Hello build bot (Jenkins), Stefan Reinauer, Edward O'Callaghan, SANTHOSH JANARDHANA HASSAN,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/flashrom/+/67840
to review the following change.
Change subject: spi25: Debug flashrom crash when Write Protect is ON
......................................................................
spi25: Debug flashrom crash when Write Protect is ON
When hardware write protect is applied, flashrom crashed and
generate coredump. spi_disable_blockprotect_generic() calls
flash->chip->printlock() method when disable was failed,
but this method is optional, can be NULL depends on type of
flashrom chip. NULL pointer check before call is added to
avoid crash.
BRANCH=none
BUG=b:129083894
TEST=Run on Mistral P2
(On CR50 console, run "wp disable")
flashrom --wp-range 0 0x400000
flashrom --wp-enable
(On CR50 console, run "wp enable")
flashrom -r /tmp/test.bin
Verify "Block protection could not be disabled!" is shown,
but flash read completes.
Signed-off-by: Yuji Sasaki <sasakiy(a)chromium.org>
Change-Id: I81094ab5f16a85871fc9869a2e285eddbbbdec4e
Reviewed-on: https://chromium-review.googlesource.com/1535140
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator(a)appspot.gserviceaccount.com>
Tested-by: Edward O'Callaghan <quasisec(a)chromium.org>
Reviewed-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-by: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40468
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M spi25_statusreg.c
1 file changed, 38 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/67840/1
diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index 05c7acf..de629a9 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -186,7 +186,8 @@
status = spi_read_status_register(flash);
if ((status & bp_mask) != 0) {
msg_cerr("Block protection could not be disabled!\n");
- flash->chip->printlock(flash);
+ if (flash->chip->printlock)
+ flash->chip->printlock(flash);
return 1;
}
msg_cdbg("disabled.\n");
--
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Attention is currently required from: Angel Pons, Name of user not set #1004601.
Peter Stuge has removed a vote from this change. ( https://review.coreboot.org/c/flashrom/+/67822 )
Change subject: serial.c: support BAUD rates > 230400 on macOS
......................................................................
Removed Code-Review+2 by Peter Stuge <peter(a)stuge.se>
--
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