Sean Anderson has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43608 )
Change subject: buspirate: Add option for setting the aux pin
......................................................................
buspirate: Add option for setting the aux pin
This adds a parameter to drive the aux pin low (or high if you
explicitly want the previous behavior). Some boards need to have a reset
pin driven low before the firmware can be safely flashed. With the Bus
Pirate, this is most easily done with the auxiliary pin.
Change-Id: Ieeecfdf1afc06dadda9b8f99547cd74854ca6775
Signed-off-by: Sean Anderson <seanga2(a)gmail.com>
---
M buspirate_spi.c
M flashrom.8.tmpl
2 files changed, 33 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/43608/1
diff --git a/buspirate_spi.c b/buspirate_spi.c
index fdfc0e4..1ccb107 100644
--- a/buspirate_spi.c
+++ b/buspirate_spi.c
@@ -228,6 +228,7 @@
int serialspeed_index = -1;
int ret = 0;
int pullup = 0;
+ int aux = 1;
dev = extract_programmer_param("dev");
if (dev && !strlen(dev)) {
@@ -277,6 +278,17 @@
}
free(tmp);
+ tmp = extract_programmer_param("aux");
+ if (tmp) {
+ if (strcasecmp("high", tmp) == 0)
+ ; /* Default */
+ else if (strcasecmp("low", tmp) == 0)
+ aux = 0;
+ else
+ msg_perr("Invalid AUX state, driving high by default.\n");
+ }
+ free(tmp);
+
/* Default buffer size is 19: 16 bytes data, 3 bytes control. */
#define DEFAULT_BUFSIZE (16 + 3)
bp_commbuf = malloc(DEFAULT_BUFSIZE);
@@ -520,11 +532,18 @@
}
/* Initial setup (SPI peripherals config): Enable power, CS high, AUX */
- bp_commbuf[0] = 0x40 | 0x0b;
+ bp_commbuf[0] = 0x40 | 0x09;
if (pullup == 1) {
bp_commbuf[0] |= (1 << 2);
msg_pdbg("Enabling pull-up resistors.\n");
}
+ if (aux) {
+ bp_commbuf[0] |= (1 << 1);
+ msg_pdbg("Driving AUX high.\n");
+ } else {
+ msg_pdbg("Driving AUX low.\n");
+ }
+
ret = buspirate_sendrecv(bp_commbuf, 1, 1);
if (ret)
return 1;
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index db50d59..caf860c 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -902,6 +902,19 @@
.URLB "http://dangerousprototypes.com/docs/Practical_guide_to_Bus_Pirate_pull-up_r…" \
"in a guide by dangerousprototypes" .
Only the external supply voltage (Vpu) is supported as of this writing.
+.sp
+An optional aux parameter specifies the state of the Bus Pirate auxiliary pin.
+This may be used to drive the auxiliary pin high or low before a transfer.
+Syntax is
+.sp
+.B " flashrom -p buspirate_spi:aux=state"
+.sp
+where
+.B state
+can be
+.BR high " or " low .
+The default
+.BR state " is " high .
.SS
.BR "pickit2_spi " programmer
.IP
--
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: Ieeecfdf1afc06dadda9b8f99547cd74854ca6775
Gerrit-Change-Number: 43608
Gerrit-PatchSet: 1
Gerrit-Owner: Sean Anderson <seanga2(a)gmail.com>
Gerrit-MessageType: newchange
Attention is currently required from: Felix Singer, Nico Huber, Thomas Heijligen, Alexander Goncharov.
Hello Felix Singer, build bot (Jenkins), Nico Huber, Thomas Heijligen, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/67878
to look at the new patch set (#9).
Change subject: dirtyjtag: Add DirtyJTAG programmer
......................................................................
dirtyjtag: Add DirtyJTAG programmer
Add a new programmer driver for the DirtyJTAG project (a USB-JTAG
firmware for STM32 MCUs).
Successfully tested with DirtyJTAG 1.4 running on an Olimex STM32-H103
development board and a SST25VF020B SPI flash chip.
Change-Id: Ic43e9a014ed7d04e429e73b30c9dcfdde1a78913
Signed-off-by: Jean THOMAS <virgule(a)jeanthomas.me>
---
M Makefile
A dirtyjtag_spi.c
M flashrom.8.tmpl
M include/programmer.h
M meson.build
M meson_options.txt
M programmer_table.c
M test_build.sh
8 files changed, 381 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/67878/9
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Jean THOMAS has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67878 )
Change subject: dirtyjtag: Add DirtyJTAG programmer
......................................................................
Patch Set 7:
(5 comments)
Patchset:
PS7:
> Thanks for your update. Alas, I missed to check the resource usage/cleanup in […]
Done
PS7:
Hi Nico, don't worry and thanks again for your careful review. I tried addressing the cleanup issues and did a little bit of code styling to better match the requirements of the linux kernel coding style.
We're close to the end! ;-)
File dirtyjtag_spi.c:
https://review.coreboot.org/c/flashrom/+/67878/comment/cb86c88a_3f69e8d5
PS7, Line 154: 32
> Just curious, is there anything in the last two bytes?
Nope! But the xfer reply is fixed 32 bytes, no matter how much data is written.
https://github.com/jeanthom/DirtyJTAG/blob/master/src/cmd.c#L179https://review.coreboot.org/c/flashrom/+/67878/comment/cafac22d_a05dd3cd
PS7, Line 212: NULL
> Should use the `djtag_data->libusb_ctx`. Many more below, too.
Done
https://review.coreboot.org/c/flashrom/+/67878/comment/b1eafeb2_9ffcea8e
PS7, Line 297: return -1;
> Sorry, I always forget to check such cleanup paths ._. […]
Don't worry, I should've been more careful on this one. I've created 2 additionals labels for the cleanup path:
* cleanup_djtag_struct: Freeing the djtag_data structure
* cleanup_libusb_ctx: Cleaning the libusb context
* cleanup_libusb_handle: Cleaning the libusb handle/attaching back the kernel driver
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Attention is currently required from: Felix Singer, Thomas Heijligen, Jean THOMAS, Alexander Goncharov.
Hello Felix Singer, build bot (Jenkins), Nico Huber, Thomas Heijligen, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/67878
to look at the new patch set (#8).
Change subject: dirtyjtag: Add DirtyJTAG programmer
......................................................................
dirtyjtag: Add DirtyJTAG programmer
Add a new programmer driver for the DirtyJTAG project (a USB-JTAG
firmware for STM32 MCUs).
Successfully tested with DirtyJTAG 1.4 running on an Olimex STM32-H103
development board and a SST25VF020B SPI flash chip.
Change-Id: Ic43e9a014ed7d04e429e73b30c9dcfdde1a78913
Signed-off-by: Jean THOMAS <virgule(a)jeanthomas.me>
---
M Makefile
A dirtyjtag_spi.c
M flashrom.8.tmpl
M include/programmer.h
M meson.build
M meson_options.txt
M programmer_table.c
M test_build.sh
8 files changed, 372 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/67878/8
--
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Change subject: test_build.sh: Use multiple cores if Make is used
......................................................................
Abandoned
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Change subject: test_build.sh: Improve robustness when dealing with empty $CC
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Change subject: test_build.sh: Identify runs for Coverity Scan
......................................................................
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Change subject: test_build.sh: Build all programmers individually using Make
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Change subject: Makefile: Fix dependencies for developerbox_spi
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