May 2022 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: meson: relocate config_print_wiki & config_default_programmer_*
by Thomas Heijligen (Code Review) 12 May '22

12 May '22

Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64029 ) Change subject: meson: relocate config_print_wiki & config_default_programmer_* ...................................................................... Patch Set 3: (1 comment) File meson.build: https://review.coreboot.org/c/flashrom/+/64029/comment/8a44d6c1_414dc600 PS2, Line 417: cargs += '-DCONFIG_DEFAULT_PROGRAMMER_ARGS="' + config_default_programmer_args + '"' > Anastasia is correct, we do have the use-case of the default programmer and this is typically "inter […] Funfact, I've added this only 11 month ago to meson. CB:55123 Maybe we can improve this option e.g. -Dclassic_cli_default_programmer=internal:boardenable=force and clean up the code for it in cli_classic. In the long run this may become problematic when cli_classic doesn't depend anymore on internal symbols and we can't check if the programmer exists in the C code. Then we have to fallback checking for the programmer availability in meson and passing the programmer name as string. This works until we change the shared library against one without the default programmer in it. In this case we can only throw an error for it. Maybe we should start a discussion how to deal with it? -- To view, visit https://review.coreboot.org/c/flashrom/+/64029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9538b0aee31b294844d4f4ca0396334a81dfb498 Gerrit-Change-Number: 64029 Gerrit-PatchSet: 3 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 May 2022 06:37:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Thomas Heijligen <src(a)posteo.de> Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: meson: relocate source file list
by Anastasia Klimchuk (Code Review) 12 May '22

12 May '22

Attention is currently required from: Thomas Heijligen. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64026 ) Change subject: meson: relocate source file list ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: I think you can start merging the first part of the chain ;) seems like a big chunk is ready already. It will be easier for you to manage the remaining patches. -- To view, visit https://review.coreboot.org/c/flashrom/+/64026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I921be8a8a99b93d23c1dbd4ea54672ba9998558d Gerrit-Change-Number: 64026 Gerrit-PatchSet: 3 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Thu, 12 May 2022 05:02:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: meson: link flashrom binary against static libflashrom
by Anastasia Klimchuk (Code Review) 12 May '22

12 May '22

Attention is currently required from: Thomas Heijligen. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64030 ) Change subject: meson: link flashrom binary against static libflashrom ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/64030/comment/c9b05909_88fbdc99 PS2, Line 8: > Is this enough? Done -- To view, visit https://review.coreboot.org/c/flashrom/+/64030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic522610f59e00299ebfa1bd29482ff92120ec52b Gerrit-Change-Number: 64030 Gerrit-PatchSet: 4 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Thu, 12 May 2022 05:00:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Thomas Heijligen <src(a)posteo.de> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: flashrom: Drop read_flash_to_file() usage
by Anastasia Klimchuk (Code Review) 12 May '22

12 May '22

Attention is currently required from: Nico Huber, Thomas Heijligen, Paul Menzel, Edward O'Callaghan. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59291 ) Change subject: flashrom: Drop read_flash_to_file() usage ...................................................................... Patch Set 17: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/59291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4b690b688acf9d5deb46e8642a252a2132ea8c73 Gerrit-Change-Number: 59291 Gerrit-PatchSet: 17 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Daniel Campello <campello(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Thu, 12 May 2022 03:34:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: tests: test write protection
by Anastasia Klimchuk (Code Review) 12 May '22

12 May '22

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/59075 ) Change subject: tests: test write protection ...................................................................... tests: test write protection Tests both WP implementation and its emulation in dummy programmer. Change-Id: I49af7f6d173eb4c56c22d80b01a473b8c499c0f8 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59075 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Thomas Heijligen <src(a)posteo.de> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> --- A tests/chip_wp.c M tests/meson.build M tests/tests.c M tests/tests.h 4 files changed, 344 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Thomas Heijligen: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved diff --git a/tests/chip_wp.c b/tests/chip_wp.c new file mode 100644 index 0000000..8b209bd --- /dev/null +++ b/tests/chip_wp.c @@ -0,0 +1,325 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2021 3mdeb Embedded Systems Consulting + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <include/test.h> +#include <stdio.h> +#include <string.h> + +#include "chipdrivers.h" +#include "flash.h" +#include "libflashrom.h" +#include "programmer.h" +#include "tests.h" + +/* + * Tests in this file do not use any mocking, because using write-protect + * emulation in dummyflasher programmer is sufficient + */ + +#define LAYOUT_TAIL_REGION_START 0x1000 + +static void setup_chip(struct flashrom_flashctx *flash, struct flashrom_layout **layout, + struct flashchip *chip, const char *programmer_param) +{ + flash->chip = chip; + + if (layout) { + const size_t tail_start = LAYOUT_TAIL_REGION_START; + const size_t tail_len = chip->total_size * KiB - 1; + + assert_int_equal(0, flashrom_layout_new(layout)); + assert_int_equal(0, flashrom_layout_add_region(*layout, 0, tail_start - 1, "head")); + assert_int_equal(0, flashrom_layout_add_region(*layout, tail_start, tail_len, "tail")); + + flashrom_layout_set(flash, *layout); + } + + assert_int_equal(0, programmer_init(&programmer_dummy, programmer_param)); + /* Assignment below normally happens while probing, but this test is not probing. */ + flash->mst = &registered_masters[0]; +} + +static void teardown(struct flashrom_layout **layout) +{ + assert_int_equal(0, programmer_shutdown()); + if (layout) + flashrom_layout_release(*layout); +} + +/* Setup the struct for W25Q128.V, all values come from flashchips.c */ +static const struct flashchip chip_W25Q128_V = { + .vendor = "aklm&dummyflasher", + .total_size = 16 * 1024, + .tested = TEST_OK_PREW, + .read = spi_chip_read, + .write = spi_chip_write_256, + .unlock = spi_disable_blockprotect, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR2, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + .wps = {STATUS3, 2, RW}, + }, + .decode_range = decode_range_spi25, +}; + +/* Trying to set an unsupported WP range fails */ +void invalid_wp_range_dummyflasher_test_success(void **state) +{ + (void) state; /* unused */ + + char *param_dup = strdup("bus=spi,emulate=W25Q128FV,hwwp=no"); + + struct flashrom_flashctx flash = { 0 }; + struct flashchip mock_chip = chip_W25Q128_V; + struct flashrom_wp_cfg *wp_cfg; + + setup_chip(&flash, NULL, &mock_chip, param_dup); + + assert_int_equal(0, flashrom_wp_cfg_new(&wp_cfg)); + flashrom_wp_set_mode(wp_cfg, FLASHROM_WP_MODE_HARDWARE); + flashrom_wp_set_range(wp_cfg, 0x1000, 0x1000); + + assert_int_equal(FLASHROM_WP_ERR_RANGE_UNSUPPORTED, flashrom_wp_write_cfg(&flash, wp_cfg)); + + teardown(NULL); + + flashrom_wp_cfg_release(wp_cfg); + free(param_dup); +} + +/* Enabling hardware WP with a valid range succeeds */ +void set_wp_range_dummyflasher_test_success(void **state) +{ + (void) state; /* unused */ + + char *param_dup = strdup("bus=spi,emulate=W25Q128FV,hwwp=no"); + + struct flashrom_flashctx flash = { 0 }; + struct flashchip mock_chip = chip_W25Q128_V; + struct flashrom_wp_cfg *wp_cfg; + + size_t start; + size_t len; + + setup_chip(&flash, NULL, &mock_chip, param_dup); + + /* Use last 4 KiB for a range. */ + assert_int_equal(0, flashrom_wp_cfg_new(&wp_cfg)); + flashrom_wp_set_mode(wp_cfg, FLASHROM_WP_MODE_HARDWARE); + flashrom_wp_set_range(wp_cfg, mock_chip.total_size * KiB - 4 * KiB, 4 * KiB); + + assert_int_equal(0, flashrom_wp_write_cfg(&flash, wp_cfg)); + + /* Check that range was set correctly. */ + assert_int_equal(0, flashrom_wp_read_cfg(wp_cfg, &flash)); + flashrom_wp_get_range(&start, &len, wp_cfg); + assert_int_equal(16 * MiB - 4 * KiB, start); + assert_int_equal(4 * KiB, len); + + teardown(NULL); + + flashrom_wp_cfg_release(wp_cfg); + free(param_dup); +} + +/* Enable hardware WP and verify that it can not be unset */ +void switch_wp_mode_dummyflasher_test_success(void **state) +{ + (void) state; /* unused */ + + char *param_dup = strdup("bus=spi,emulate=W25Q128FV,hwwp=yes"); + + struct flashrom_flashctx flash = { 0 }; + struct flashchip mock_chip = chip_W25Q128_V; + struct flashrom_wp_cfg *wp_cfg; + + setup_chip(&flash, NULL, &mock_chip, param_dup); + + assert_int_equal(0, flashrom_wp_cfg_new(&wp_cfg)); + + /* Check initial mode. */ + assert_int_equal(0, flashrom_wp_read_cfg(wp_cfg, &flash)); + assert_int_equal(FLASHROM_WP_MODE_DISABLED, flashrom_wp_get_mode(wp_cfg)); + + /* Enable hardware protection, which can't be unset because simulated + HW WP pin is in active state. */ + flashrom_wp_set_mode(wp_cfg, FLASHROM_WP_MODE_HARDWARE); + assert_int_equal(0, flashrom_wp_write_cfg(&flash, wp_cfg)); + assert_int_equal(0, flashrom_wp_read_cfg(wp_cfg, &flash)); + assert_int_equal(FLASHROM_WP_MODE_HARDWARE, flashrom_wp_get_mode(wp_cfg)); + + /* Check that write-protection mode can't be unset. */ + flashrom_wp_set_mode(wp_cfg, FLASHROM_WP_MODE_DISABLED); + assert_int_equal(FLASHROM_WP_ERR_VERIFY_FAILED, flashrom_wp_write_cfg(&flash, wp_cfg)); + + /* Final mode should be "hardware". */ + assert_int_equal(0, flashrom_wp_read_cfg(wp_cfg, &flash)); + assert_int_equal(FLASHROM_WP_MODE_HARDWARE, flashrom_wp_get_mode(wp_cfg)); + + teardown(NULL); + + flashrom_wp_cfg_release(wp_cfg); + free(param_dup); +} + +/* WP state is decoded correctly from status registers */ +void wp_init_from_status_dummyflasher_test_success(void **state) +{ + (void) state; /* unused */ + + /* + * CMP (S14) = 1 (range complement) + * SRP1 (S8) = 1 + * SRP0 (S7) = 1 (`SRP1 == 1 && SRP0 == 1` is permanent mode) + * SEC (S6) = 1 (base unit is a 4 KiB sector) + * TB (S5) = 1 (bottom up range) + * BP2 (S4) = 0 + * BP1 (S3) = 1 + * BP0 (S2) = 1 (bp: BP2-0 == 0b011 == 3) + * + * Range coefficient is `2 ** (bp - 1)`, which is 4 in this case. + * Multiplaying that by base unit gives 16 KiB protected region at the + * bottom (start of the chip), which is then complemented. + */ + char *param_dup = strdup("bus=spi,emulate=W25Q128FV,spi_status=0x41ec"); + + struct flashrom_flashctx flash = { 0 }; + struct flashchip mock_chip = chip_W25Q128_V; + struct flashrom_wp_cfg *wp_cfg; + + size_t start; + size_t len; + + setup_chip(&flash, NULL, &mock_chip, param_dup); + + assert_int_equal(0, flashrom_wp_cfg_new(&wp_cfg)); + + /* Verify that WP mode reflects SPI status */ + assert_int_equal(0, flashrom_wp_read_cfg(wp_cfg, &flash)); + assert_int_equal(FLASHROM_WP_MODE_PERMANENT, flashrom_wp_get_mode(wp_cfg)); + flashrom_wp_get_range(&start, &len, wp_cfg); + assert_int_equal(0x004000, start); + assert_int_equal(0xffc000, len); + + teardown(NULL); + + flashrom_wp_cfg_release(wp_cfg); + free(param_dup); +} + +/* Enabled WP makes full chip erasure fail */ +void full_chip_erase_with_wp_dummyflasher_test_success(void **state) +{ + (void) state; /* unused */ + + struct flashrom_flashctx flash = { 0 }; + struct flashrom_layout *layout; + struct flashchip mock_chip = chip_W25Q128_V; + struct flashrom_wp_cfg *wp_cfg; + + char *param_dup = strdup("bus=spi,emulate=W25Q128FV,hwwp=yes"); + + setup_chip(&flash, &layout, &mock_chip, param_dup); + /* Layout regions are created by setup_chip(). */ + assert_int_equal(0, flashrom_layout_include_region(layout, "head")); + assert_int_equal(0, flashrom_layout_include_region(layout, "tail")); + + assert_int_equal(0, flashrom_wp_cfg_new(&wp_cfg)); + + /* Write protection takes effect only after changing SRP values, so at + this stage WP is not enabled and erase completes successfully. */ + assert_int_equal(0, flashrom_flash_erase(&flash)); + + assert_int_equal(0, flashrom_wp_read_cfg(wp_cfg, &flash)); + + /* Hardware-protect first 4 KiB. */ + flashrom_wp_set_range(wp_cfg, 0, 4 * KiB); + flashrom_wp_set_mode(wp_cfg, FLASHROM_WP_MODE_HARDWARE); + + assert_int_equal(0, flashrom_wp_write_cfg(&flash, wp_cfg)); + + /* Try erasing the chip again. Now that WP is active, the first 4 KiB is + protected and we're trying to erase the whole chip, erase should + fail. */ + assert_int_equal(1, flashrom_flash_erase(&flash)); + + teardown(&layout); + + flashrom_wp_cfg_release(wp_cfg); + free(param_dup); +} + +/* Enabled WP does not block erasing unprotected parts of the chip */ +void partial_chip_erase_with_wp_dummyflasher_test_success(void **state) +{ + (void) state; /* unused */ + + struct flashrom_flashctx flash = { 0 }; + struct flashrom_layout *layout; + struct flashchip mock_chip = chip_W25Q128_V; + struct flashrom_wp_cfg *wp_cfg; + + char *param_dup = strdup("bus=spi,emulate=W25Q128FV,hwwp=yes"); + + setup_chip(&flash, &layout, &mock_chip, param_dup); + /* Layout region is created by setup_chip(). */ + assert_int_equal(0, flashrom_layout_include_region(layout, "tail")); + + assert_int_equal(0, flashrom_wp_cfg_new(&wp_cfg)); + + assert_int_equal(0, flashrom_wp_read_cfg(wp_cfg, &flash)); + + /* Hardware-protect head region. */ + flashrom_wp_set_mode(wp_cfg, FLASHROM_WP_MODE_HARDWARE); + flashrom_wp_set_range(wp_cfg, 0, LAYOUT_TAIL_REGION_START); + + assert_int_equal(0, flashrom_wp_write_cfg(&flash, wp_cfg)); + + /* First 4 KiB is the only protected part of the chip and the region + we included covers only unprotected part, so erase operation should + succeed. */ + assert_int_equal(0, flashrom_flash_erase(&flash)); + + teardown(&layout); + + flashrom_wp_cfg_release(wp_cfg); + free(param_dup); +} diff --git a/tests/meson.build b/tests/meson.build index d3b46b1..588ac17 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -23,6 +23,7 @@ 'lifecycle.c', 'layout.c', 'chip.c', + 'chip_wp.c', ] mocks = [ diff --git a/tests/tests.c b/tests/tests.c index 6aabd90..2f955ff 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -436,5 +436,15 @@ }; ret |= cmocka_run_group_tests_name("chip.c tests", chip_tests, NULL, NULL); + const struct CMUnitTest chip_wp_tests[] = { + cmocka_unit_test(invalid_wp_range_dummyflasher_test_success), + cmocka_unit_test(set_wp_range_dummyflasher_test_success), + cmocka_unit_test(switch_wp_mode_dummyflasher_test_success), + cmocka_unit_test(wp_init_from_status_dummyflasher_test_success), + cmocka_unit_test(full_chip_erase_with_wp_dummyflasher_test_success), + cmocka_unit_test(partial_chip_erase_with_wp_dummyflasher_test_success), + }; + ret |= cmocka_run_group_tests_name("chip_wp.c tests", chip_wp_tests, NULL, NULL); + return ret; } diff --git a/tests/tests.h b/tests/tests.h index 68f7781..89e4095 100644 --- a/tests/tests.h +++ b/tests/tests.h @@ -68,4 +68,12 @@ void verify_chip_test_success(void **state); void verify_chip_with_dummyflasher_test_success(void **state); +/* chip_wp.c */ +void invalid_wp_range_dummyflasher_test_success(void **state); +void set_wp_range_dummyflasher_test_success(void **state); +void switch_wp_mode_dummyflasher_test_success(void **state); +void wp_init_from_status_dummyflasher_test_success(void **state); +void full_chip_erase_with_wp_dummyflasher_test_success(void **state); +void partial_chip_erase_with_wp_dummyflasher_test_success(void **state); + #endif /* TESTS_H */ -- To view, visit https://review.coreboot.org/c/flashrom/+/59075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I49af7f6d173eb4c56c22d80b01a473b8c499c0f8 Gerrit-Change-Number: 59075 Gerrit-PatchSet: 41 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: dummyflasher: enforce write protection for W25Q128FV
by Anastasia Klimchuk (Code Review) 12 May '22

12 May '22

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/59074 ) Change subject: dummyflasher: enforce write protection for W25Q128FV ...................................................................... dummyflasher: enforce write protection for W25Q128FV Start taking bits related to write protection into account. Also add "hwwp" parameter for dummy programmer that sets state of WP pin (not inverted value). TEST=use command-line interface to run WP-related commands dummyflasher doesn't store state of the chip between runs and flashrom allows running only one command, so testing WP in this way is limited. However, WP options can be combined with other operations and are executed prior to them, so certain scenarios can be checked. List possible ranges: flashrom -p dummy:emulate=W25Q128FV,hwwp=yes --wp-list Set a particular range and check status is correct: flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \ --wp-enable \ --wp-range=0x00100000,0x00f00000 \ --wp-status Enable write protection and try erasing/writing (erasing here): # this fails flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \ --wp-range=0,0x00c00000 \ --wp-enable \ --erase Write protecting empty range has no effect: # this succeeds flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \ --wp-range=0,0 \ --wp-enable \ --erase Disabling WP is possible if hwwp is off: # this fails flashrom -p dummy:emulate=W25Q128FV,spi_status=0x80,hwwp=yes \ --wp-disable # this succeeds flashrom -p dummy:emulate=W25Q128FV,spi_status=0x80,hwwp=no \ --wp-disable Change-Id: I9fd1417f941186391bd213bd355530143c8f04a0 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59074 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Thomas Heijligen <src(a)posteo.de> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M dummyflasher.c M flashrom.8.tmpl 2 files changed, 157 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Thomas Heijligen: Looks good to me, but someone else must approve Edward O'Callaghan: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved diff --git a/dummyflasher.c b/dummyflasher.c index 6323139..1ee9d3e 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -26,6 +26,7 @@ #include "programmer.h" #include "flashchips.h" #include "spi.h" +#include "writeprotect.h" enum emu_chip { EMULATE_NONE, @@ -64,6 +65,11 @@ unsigned int spi_blacklist_size; unsigned int spi_ignorelist_size; + bool hwwp; /* state of hardware write protection */ + /* wp_start == wp_end when write-protection is disabled */ + uint32_t wp_start; + uint32_t wp_end; + unsigned int spi_write_256_chunksize; uint8_t *flashchip_contents; }; @@ -173,7 +179,14 @@ uint8_t ro_bits = reg == STATUS1 ? SPI_SR_WIP : 0; if (data->emu_chip == EMULATE_WINBOND_W25Q128FV) { - if (reg == STATUS2) { + const bool srp0 = (data->emu_status[0] >> 7); + const bool srp1 = (data->emu_status[1] & 1); + + const bool wp_active = (srp1 || (srp0 && data->hwwp)); + + if (wp_active) { + ro_bits = 0xff; + } else if (reg == STATUS2) { /* SUS (bit_7) and (R) (bit_2). */ ro_bits = 0x84; /* Once any of the lock bits (LB[1..3]) are set, they @@ -190,6 +203,79 @@ return ro_bits; } +static void update_write_protection(struct emu_data *data) +{ + if (data->emu_chip != EMULATE_WINBOND_W25Q128FV) + return; + + const struct wp_bits bits = { + .srp = data->emu_status[0] >> 7, + .srl = data->emu_status[1] & 1, + + .bp_bit_count = 3, + .bp = + { + (data->emu_status[0] >> 2) & 1, + (data->emu_status[0] >> 3) & 1, + (data->emu_status[0] >> 4) & 1 + }, + + .tb_bit_present = true, + .tb = (data->emu_status[0] >> 5) & 1, + + .sec_bit_present = true, + .sec = (data->emu_status[0] >> 6) & 1, + + .cmp_bit_present = true, + .cmp = (data->emu_status[1] >> 6) & 1, + }; + + size_t start; + size_t len; + decode_range_spi25(&start, &len, &bits, data->emu_chip_size); + + data->wp_start = start; + data->wp_end = start + len; +} + +/* Checks whether range intersects a write-protected area of the flash if one is + * defined. */ +static bool is_write_protected(const struct emu_data *data, uint32_t start, uint32_t len) +{ + if (len == 0) + return false; + + const uint32_t last = start + len - 1; + return (start < data->wp_end && last >= data->wp_start); +} + +/* Returns non-zero on error. */ +static int write_flash_data(struct emu_data *data, uint32_t start, uint32_t len, const uint8_t *buf) +{ + if (is_write_protected(data, start, len)) { + msg_perr("At least part of the write range is write protected!\n"); + return 1; + } + + memcpy(data->flashchip_contents + start, buf, len); + data->emu_modified = 1; + return 0; +} + +/* Returns non-zero on error. */ +static int erase_flash_data(struct emu_data *data, uint32_t start, uint32_t len) +{ + if (is_write_protected(data, start, len)) { + msg_perr("At least part of the erase range is write protected!\n"); + return 1; + } + + /* FIXME: take data->erase_to_zero into account. */ + memset(data->flashchip_contents + start, 0xff, len); + data->emu_modified = 1; + return 0; +} + static int emulate_spi_chip_response(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, @@ -376,6 +462,8 @@ msg_pdbg2("WRSR wrote 0x%02x%02x.\n", data->emu_status[1], data->emu_status[0]); else msg_pdbg2("WRSR wrote 0x%02x.\n", data->emu_status[0]); + + update_write_protection(data); break; case JEDEC_WRSR2: if (data->emu_status_len < 2) @@ -390,6 +478,8 @@ data->emu_status[1] |= (writearr[1] & ~ro_bits); msg_pdbg2("WRSR2 wrote 0x%02x.\n", data->emu_status[1]); + + update_write_protection(data); break; case JEDEC_WRSR3: if (data->emu_status_len < 3) @@ -431,8 +521,10 @@ msg_perr("Max BYTE PROGRAM size exceeded!\n"); return 1; } - memcpy(data->flashchip_contents + offs, writearr + 4, writecnt - 4); - data->emu_modified = 1; + if (write_flash_data(data, offs, writecnt - 4, writearr + 4)) { + msg_perr("Failed to program flash!\n"); + return 1; + } break; case JEDEC_BYTE_PROGRAM_4BA: offs = writearr[1] << 24 | writearr[2] << 16 | writearr[3] << 8 | writearr[4]; @@ -446,8 +538,10 @@ msg_perr("Max BYTE PROGRAM size exceeded!\n"); return 1; } - memcpy(data->flashchip_contents + offs, writearr + 5, writecnt - 5); - data->emu_modified = 1; + if (write_flash_data(data, offs, writecnt - 5, writearr + 5)) { + msg_perr("Failed to program flash!\n"); + return 1; + } break; case JEDEC_AAI_WORD_PROGRAM: if (!data->emu_max_aai_size) @@ -468,7 +562,10 @@ writearr[3]; /* Truncate to emu_chip_size. */ aai_offs %= data->emu_chip_size; - memcpy(data->flashchip_contents + aai_offs, writearr + 4, 2); + if (write_flash_data(data, aai_offs, 2, writearr + 4)) { + msg_perr("Failed to program flash!\n"); + return 1; + } aai_offs += 2; } else { if (writecnt < JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE) { @@ -481,10 +578,12 @@ "too long!\n"); return 1; } - memcpy(data->flashchip_contents + aai_offs, writearr + 1, 2); + if (write_flash_data(data, aai_offs, 2, writearr + 1)) { + msg_perr("Failed to program flash!\n"); + return 1; + } aai_offs += 2; } - data->emu_modified = 1; break; case JEDEC_WRDI: if (data->emu_max_aai_size) @@ -505,8 +604,10 @@ if (offs & (data->emu_jedec_se_size - 1)) msg_pdbg("Unaligned SECTOR ERASE 0x20: 0x%x\n", offs); offs &= ~(data->emu_jedec_se_size - 1); - memset(data->flashchip_contents + offs, 0xff, data->emu_jedec_se_size); - data->emu_modified = 1; + if (erase_flash_data(data, offs, data->emu_jedec_se_size)) { + msg_perr("Failed to erase flash!\n"); + return 1; + } break; case JEDEC_BE_52: if (!data->emu_jedec_be_52_size) @@ -523,8 +624,10 @@ if (offs & (data->emu_jedec_be_52_size - 1)) msg_pdbg("Unaligned BLOCK ERASE 0x52: 0x%x\n", offs); offs &= ~(data->emu_jedec_be_52_size - 1); - memset(data->flashchip_contents + offs, 0xff, data->emu_jedec_be_52_size); - data->emu_modified = 1; + if (erase_flash_data(data, offs, data->emu_jedec_be_52_size)) { + msg_perr("Failed to erase flash!\n"); + return 1; + } break; case JEDEC_BE_D8: if (!data->emu_jedec_be_d8_size) @@ -541,8 +644,10 @@ if (offs & (data->emu_jedec_be_d8_size - 1)) msg_pdbg("Unaligned BLOCK ERASE 0xd8: 0x%x\n", offs); offs &= ~(data->emu_jedec_be_d8_size - 1); - memset(data->flashchip_contents + offs, 0xff, data->emu_jedec_be_d8_size); - data->emu_modified = 1; + if (erase_flash_data(data, offs, data->emu_jedec_be_d8_size)) { + msg_perr("Failed to erase flash!\n"); + return 1; + } break; case JEDEC_CE_60: if (!data->emu_jedec_ce_60_size) @@ -557,8 +662,10 @@ } /* JEDEC_CE_60_OUTSIZE is 1 (no address) -> no offset. */ /* emu_jedec_ce_60_size is emu_chip_size. */ - memset(data->flashchip_contents, 0xff, data->emu_jedec_ce_60_size); - data->emu_modified = 1; + if (erase_flash_data(data, 0, data->emu_jedec_ce_60_size)) { + msg_perr("Failed to erase flash!\n"); + return 1; + } break; case JEDEC_CE_C7: if (!data->emu_jedec_ce_c7_size) @@ -573,8 +680,10 @@ } /* JEDEC_CE_C7_OUTSIZE is 1 (no address) -> no offset. */ /* emu_jedec_ce_c7_size is emu_chip_size. */ - memset(data->flashchip_contents, 0xff, data->emu_jedec_ce_c7_size); - data->emu_modified = 1; + if (erase_flash_data(data, 0, data->emu_jedec_ce_c7_size)) { + msg_perr("Failed to erase flash!\n"); + return 1; + } break; case JEDEC_SFDP: if (data->emu_chip != EMULATE_MACRONIX_MX25L6436) @@ -884,6 +993,21 @@ free(tmp); } + tmp = extract_programmer_param("hwwp"); + if (tmp) { + if (!strcmp(tmp, "yes")) { + msg_pdbg("Emulated chip will have hardware WP enabled\n"); + data->hwwp = true; + } else if (!strcmp(tmp, "no")) { + msg_pdbg("Emulated chip will have hardware WP disabled\n"); + } else { + msg_perr("hwwp can be \"yes\" or \"no\"\n"); + free(tmp); + return 1; + } + free(tmp); + } + tmp = extract_programmer_param("emulate"); if (!tmp) { msg_pdbg("Not emulating any flash chip.\n"); diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 0f7bc97..58f5ec0 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -820,6 +820,21 @@ SR1, 0x22 to SR2 and 0x33 to SR3. Shorter value is padded to 24 bits with zeroes on the left. See datasheet for chosen chip for details about the registers content. +.sp +.TP +.B Write protection +.sp +Chips with emulated WP: W25Q128FV. +.sp +You can simulate state of hardware protection pin (WP) with the +.sp +.B " flashrom -p dummy:hwwp=state" +.sp +syntax where +.B state +is "yes" or "no" (default value). "yes" means active state of the pin implies +that chip is write-protected (on real hardware the pin is usually negated, but +not here). .SS .BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ -- To view, visit https://review.coreboot.org/c/flashrom/+/59074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9fd1417f941186391bd213bd355530143c8f04a0 Gerrit-Change-Number: 59074 Gerrit-PatchSet: 38 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: dummyflasher: emulate SR2 and SR3 for W25Q128FV
by Anastasia Klimchuk (Code Review) 12 May '22

12 May '22

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/59073 ) Change subject: dummyflasher: emulate SR2 and SR3 for W25Q128FV ...................................................................... dummyflasher: emulate SR2 and SR3 for W25Q128FV Enable emulation of SR2 and SR3 for W25Q128FV and provide logic for updating them (masks of read-only bits that can't be set from outside). TEST=check how input value affects status registers of emulated chip flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x12 | grep -A3 'Initial status registers' flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x1234 | grep -A3 'Initial status registers' flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x123456 | grep -A3 'Initial status registers' Change-Id: I79f9b4a0b604663d3288ad70dcbe3ea4075dede5 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59073 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Thomas Heijligen <src(a)posteo.de> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M dummyflasher.c 1 file changed, 25 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Thomas Heijligen: Looks good to me, but someone else must approve Edward O'Callaghan: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved diff --git a/dummyflasher.c b/dummyflasher.c index fe2375f..6323139 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -164,13 +164,30 @@ return; } -static uint8_t get_reg_ro_bit_mask(enum flash_reg reg) +static uint8_t get_reg_ro_bit_mask(const struct emu_data *data, enum flash_reg reg) { /* Whoever adds a new register must not forget to update this function or at least shouldn't use it incorrectly. */ assert(reg == STATUS1 || reg == STATUS2 || reg == STATUS3); - return reg == STATUS1 ? SPI_SR_WIP : 0; + uint8_t ro_bits = reg == STATUS1 ? SPI_SR_WIP : 0; + + if (data->emu_chip == EMULATE_WINBOND_W25Q128FV) { + if (reg == STATUS2) { + /* SUS (bit_7) and (R) (bit_2). */ + ro_bits = 0x84; + /* Once any of the lock bits (LB[1..3]) are set, they + can't be unset. */ + ro_bits |= data->emu_status[1] & (1 << 3); + ro_bits |= data->emu_status[1] & (1 << 4); + ro_bits |= data->emu_status[1] & (1 << 5); + } else if (reg == STATUS3) { + /* Four reserved bits. */ + ro_bits = 0x1b; + } + } + + return ro_bits; } static int emulate_spi_chip_response(unsigned int writecnt, @@ -346,11 +363,11 @@ /* FIXME: add some reasonable simulation of the busy flag */ - ro_bits = get_reg_ro_bit_mask(STATUS1); + ro_bits = get_reg_ro_bit_mask(data, STATUS1); data->emu_status[0] &= ro_bits; data->emu_status[0] |= writearr[1] & ~ro_bits; if (wrsr_ext) { - ro_bits = get_reg_ro_bit_mask(STATUS2); + ro_bits = get_reg_ro_bit_mask(data, STATUS2); data->emu_status[1] &= ro_bits; data->emu_status[1] |= writearr[2] & ~ro_bits; } @@ -368,7 +385,7 @@ break; } - ro_bits = get_reg_ro_bit_mask(STATUS2); + ro_bits = get_reg_ro_bit_mask(data, STATUS2); data->emu_status[1] &= ro_bits; data->emu_status[1] |= (writearr[1] & ~ro_bits); @@ -382,7 +399,7 @@ break; } - ro_bits = get_reg_ro_bit_mask(STATUS3); + ro_bits = get_reg_ro_bit_mask(data, STATUS3); data->emu_status[2] &= ro_bits; data->emu_status[2] |= (writearr[1] & ~ro_bits); @@ -932,10 +949,11 @@ } if (!strcmp(tmp, "W25Q128FV")) { data->emu_chip = EMULATE_WINBOND_W25Q128FV; + data->emu_wrsr_ext = true; data->emu_chip_size = 16 * 1024 * 1024; data->emu_max_byteprogram_size = 256; data->emu_max_aai_size = 0; - data->emu_status_len = 1; + data->emu_status_len = 3; data->emu_jedec_se_size = 4 * 1024; data->emu_jedec_be_52_size = 32 * 1024; data->emu_jedec_be_d8_size = 64 * 1024; -- To view, visit https://review.coreboot.org/c/flashrom/+/59073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I79f9b4a0b604663d3288ad70dcbe3ea4075dede5 Gerrit-Change-Number: 59073 Gerrit-PatchSet: 38 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: tests: test write protection
by Edward O'Callaghan (Code Review) 12 May '22

12 May '22

Attention is currently required from: Nico Huber, Sergii Dmytruk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59075 ) Change subject: tests: test write protection ...................................................................... Patch Set 40: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/59075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I49af7f6d173eb4c56c22d80b01a473b8c499c0f8 Gerrit-Change-Number: 59075 Gerrit-PatchSet: 40 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Thu, 12 May 2022 03:00:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: dummyflasher: enforce write protection for W25Q128FV
by Edward O'Callaghan (Code Review) 12 May '22

12 May '22

Attention is currently required from: Nico Huber, Angel Pons, Sergii Dmytruk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59074 ) Change subject: dummyflasher: enforce write protection for W25Q128FV ...................................................................... Patch Set 37: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/59074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9fd1417f941186391bd213bd355530143c8f04a0 Gerrit-Change-Number: 59074 Gerrit-PatchSet: 37 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Thu, 12 May 2022 03:00:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: dummyflasher: emulate SR2 and SR3 for W25Q128FV
by Edward O'Callaghan (Code Review) 12 May '22

12 May '22

Attention is currently required from: Angel Pons, Sergii Dmytruk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59073 ) Change subject: dummyflasher: emulate SR2 and SR3 for W25Q128FV ...................................................................... Patch Set 37: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/59073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I79f9b4a0b604663d3288ad70dcbe3ea4075dede5 Gerrit-Change-Number: 59073 Gerrit-PatchSet: 37 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Thu, 12 May 2022 03:00:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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