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Change subject: ichspi.c: Implement read_write_status for wp
......................................................................
Patch Set 4: Code-Review+2
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64540 )
Change subject: ichspi.c: Implement read_write_status for wp
......................................................................
Patch Set 3:
(2 comments)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/64540/comment/6d73b75d_b460fe51
PS2, Line 1349: static int ich_hwseq_read_status(const struct flashctx *flash, enum flash_reg reg_, uint8_t *value)
> I think both functions should fail if reg_ is not SR1.
Done
https://review.coreboot.org/c/flashrom/+/64540/comment/5d99b916_e7b1bcf5
PS2, Line 1352: int len = 1;
> I'd make len a constant in both functions. […]
Done
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Hello build bot (Jenkins), Subrata Banik, Nikolai Artemiev, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/64540
to look at the new patch set (#4).
Change subject: ichspi.c: Implement read_write_status for wp
......................................................................
ichspi.c: Implement read_write_status for wp
The ichspi hwseq path has a opaque master specialisation that
allows for reading and writing STATUS1 registers. Hook the callbacks
with a implementation to allow for this so that writeprotect maybe
supported though this path.
Change-Id: I7ecbe8491ecea3697922c91af26ca62276e86317
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M ichspi.c
1 file changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/64540/4
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64375 )
Change subject: spi25_statusreg.c: Allow opaque masters to hook spi_{rw}_register()
......................................................................
Patch Set 4:
(1 comment)
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/64375/comment/7d79312b_17e4c9fc
PS3, Line 35: }
> nit: no need for curly braces here and below
If I recall the correct way around, Angel Pons suggests to always use braces in flashrom style?
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Change subject: ichspi.c: Implement read_write_status for wp
......................................................................
Patch Set 3:
(2 comments)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/64540/comment/36789db4_05e0f16c
PS2, Line 1349: static int ich_hwseq_read_status(const struct flashctx *flash, enum flash_reg reg_, uint8_t *value)
I think both functions should fail if reg_ is not SR1.
https://review.coreboot.org/c/flashrom/+/64540/comment/b1d90ebf_a7d242f8
PS2, Line 1352: int len = 1;
I'd make len a constant in both functions. It's used 15 lines below and one has to trace the code to understand that it's never updated.
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64375 )
Change subject: spi25_statusreg.c: Allow opaque masters to hook spi_{rw}_register()
......................................................................
Patch Set 4:
(1 comment)
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/64375/comment/ba5e6e08_469938b1
PS3, Line 35: }
nit: no need for curly braces here and below
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Change subject: ichspi.c: Implement read_write_status for wp
......................................................................
Patch Set 3:
(1 comment)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/64540/comment/c772e5df_bf03d8e8
PS1, Line 122: FIXME(quasisec): Port to new macros? - Control bits
> Thanks Subrata, hopefully the updated patch addresses the issue?
Ack
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Change subject: ichspi.c: Implement read_write_status for wp
......................................................................
Patch Set 3: Code-Review+2
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Change subject: ichspi.c: Implement read_write_status for wp
......................................................................
Patch Set 2:
(1 comment)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/64540/comment/28e8c344_29c2ae91
PS1, Line 122: FIXME(quasisec): Port to new macros? - Control bits
> > @Subrata, what did you suggest downstream to clean this up here? […]
Thanks Subrata, hopefully the updated patch addresses the issue?
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Hello build bot (Jenkins), Subrata Banik, Nikolai Artemiev, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/64540
to look at the new patch set (#3).
Change subject: ichspi.c: Implement read_write_status for wp
......................................................................
ichspi.c: Implement read_write_status for wp
The ichspi hwseq path has a opaque master specialisation that
allows for reading and writing STATUS1 registers. Hook the callbacks
with a implementation to allow for this so that writeprotect maybe
supported though this path.
Change-Id: I7ecbe8491ecea3697922c91af26ca62276e86317
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M ichspi.c
1 file changed, 65 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/64540/3
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