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Change subject: ch341a_spi.c: Reset device before use
......................................................................
Patch Set 1: Code-Review+1
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Change subject: tests/: wrap flock() and ftruncate()
......................................................................
Patch Set 11:
(1 comment)
File tests/tests.c:
https://review.coreboot.org/c/flashrom/+/62312/comment/12329192_bdb5e71f
PS11, Line 285: int __wrap_flock(int fd, int operation)
These should go after __wrap_ferror().
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Change subject: tests/: wrap flock() and ftruncate()
......................................................................
Patch Set 10:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62312/comment/1ee368bb_a3d687e9
PS6, Line 7: wrap flock() and ftruncate()
> Done
I think this should be its own commit and merged regardless. All the I/O ops should be stubbed out so real variants are not accidentally called with fake fd values. If that is how the test harness works then it shouldn't have singularities that make your leg explode while writing a unit-test, sounds like a lot of foot-gun if doing on ad hoc.
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Hello build bot (Jenkins), Daniel Campello, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62312
to look at the new patch set (#10).
Change subject: tests/: wrap flock() and ftruncate()
......................................................................
tests/: wrap flock() and ftruncate()
Avoid calling real I/O functions accidentally with fake fd values.
BUG=b:217629892,b:215255210
TEST=`ninja test`.
Change-Id: I57e7843a4d94c0a7200690d4c1d9e4194b9f83c5
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M tests/meson.build
M tests/tests.c
2 files changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/12/62312/10
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63227 )
Change subject: tests: assert pathname and flags when calling open()
......................................................................
Patch Set 6:
(2 comments)
File tests/tests.c:
https://review.coreboot.org/c/flashrom/+/63227/comment/dbcb4444_8e94b126
PS6, Line 77: wrap_open_and_friends
this may have unexpected behavior when `(get_io()->open != NULL)&&(get_io()->open_state != NULL)`.
https://review.coreboot.org/c/flashrom/+/63227/comment/f279dd8e_dd00ff2f
PS6, Line 81: )
`&& !get_io()->open)`
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Change subject: tests: use MOCK_FD instead of NON_ZERO
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/63193/comment/74679319_de3fd274
PS3, Line 9: return a non-negative value for
: the file descriptor expected from open operations.
Actually, was this intentional?
```
RETURN VALUE
On success, open(), openat(), and creat() return the new file descriptor (a nonnegative integer). On error, -1 is returned and errno is set to indicate the error.
```
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62282 )
Change subject: ichspi: Add Jasper Lake support
......................................................................
Patch Set 8:
(2 comments)
Patchset:
PS4:
> Well it's different from EHL, but is it really new? It looks closer to the […]
Unresolving then because it does look like a pch300 although I am not 100% on every tiny idiosyncrasy.
If `ich_number_of_masters()` needs adjusting then so does the switch in `prettyprint_ich_descriptor_master()` too.
Thing is, that has:
```
const char *const master_names[] = {
"BIOS", "ME", "GbE", "unknown", "EC",
};
```
but the datasheet says on page 42 - [BIOS, ME, GbE, EC] and states there are 4 masters. Nothing indicates if to interpret "number of masters" from the flash descriptor as so called- 0-based or 1-based. Therefore I just assumed `cont->NM`.
Open to some guidance here? My concern is that I got those two functions wrong.
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/62282/comment/2df4901f_35436b88
PS8, Line 1061: CHIPSET_ELKHART_LAKE
> EHL has CSSO 0x58. It's in the updated SPI Guide and was confirmed with […]
Thanks Nico that is super useful ! I didn't have access to EHL I was asking if Subrata could ask a contact to get that value out of band. I fixed the patch now to be explicit, I think that is a good strategy for the function to be total.
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Hello Sam McNally, build bot (Jenkins), Subrata Banik, Angel Pons,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#9).
Change subject: ichspi: Add Jasper Lake support
......................................................................
ichspi: Add Jasper Lake support
Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect
the chipset when the CSSL (CPU Soft Strap Length) field default value
(0x03) on Jasper Lake is the same as Elkhart Lake.
BUG=b:221175960
TEST=dedede with `flashrom -p internal --flash-size`.
```
$ flashrom -VVV -p internal --ifd -i fd -i bios -r /tmp/filename.rom
<snip>
Enabling hardware sequencing by default for 100+ series PCH.
OK.
No board enable found matching coreboot IDs vendor="Google", model="Magolor".
The following protocols are supported: Programmer-specific.
Probing for Programmer Opaque flash chip, 0 kB: Chip identified: GD25Q127C/GD25Q128C
Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB.
There is only one partition containing the whole address space (0x000000 - 0xffffff).
There are 4096 erase blocks with 4096 B each.
Added layout entry 00000000 - 00ffffff named complete flash
Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific).
This chip may contain one-time programmable memory. flashrom cannot read
and may never be able to write it, hence it may not be able to completely
clone the contents of this chip (see man page for details).
Reading Status register
Block protection is disabled.
Reading ich descriptor... Reading 4096 bytes starting at 0x000000.
done.
Assuming chipset 'Jasper Lake'.
Added layout entry 00000000 - 00000fff named fd
Added layout entry 00381000 - 00ffffff named bios
Added layout entry 00001000 - 00380fff named me
restore_power_management: Re-enabling power management.
Using regions: "bios", "fd".
Reading Status register
Block protection is disabled.
Reading flash... 0x381000-0xffffff:R Reading 13103104 bytes starting at 0x381000.
000000-0x0fff:R Reading 4096 bytes starting at 0x000000.
done.
restore_power_management: Re-enabling power management.
SUCCESS
Restoring PCI config space for 00:1f:5 reg 0xdc
restore_power_management: Re-enabling power management.
```
Change-Id: Ib942d0b8942fe0a991b2af0b187414818485153d
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M chipset_enable.c
M ich_descriptors.c
M ichspi.c
M programmer.h
M util/ich_descriptors_tool/ich_descriptors_tool.c
5 files changed, 37 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/82/62282/9
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62282 )
Change subject: ichspi: Add Jasper Lake support
......................................................................
Patch Set 8:
(2 comments)
Patchset:
PS4:
> Given the subtle differences such as `freq_str` it looks like keeping them separate was the right id […]
Well it's different from EHL, but is it really new? It looks closer to the
big core PCHs, looking at Figure 1 of the datasheet. The masters and regions
in the SPI guide also don't look like what we print for APL/GLK. And from the
CSE version it should be somewhere between Ice Point and Comet Point. I haven't
looked at every single bit, but it seems 300-series compatible (renaming the
enum entry is also an option, if the code matches).
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/62282/comment/c55662d0_05398e49
PS8, Line 1061: CHIPSET_ELKHART_LAKE
> I do not but this preserves the current behavior and that sounds like a another patch. […]
EHL has CSSO 0x58. It's in the updated SPI Guide and was confirmed with
a real-world descriptor. IIRC, David wants us to have all paths with
explicit checks plus a fallback default that repeats the most recent
known chipset. That would be a fixup for the ADL/MTL patches, though.
Have a look how things were before your patches and you can get the
idea.
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Change subject: ichspi: Add Jasper Lake support
......................................................................
Patch Set 8:
(1 comment)
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/62282/comment/a720aef7_ce52143b
PS8, Line 1061: CHIPSET_ELKHART_LAKE
> Do you know what is the CSSO value for EHL by any chance ? […]
I do not but this preserves the current behavior and that sounds like a another patch. Keeping the `else` or not feels stylistically subjective? Let me know if you feel strongly?
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