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Change subject: flashchips.c: add writeprotect support for more chips
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Patch Set 26:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62214/comment/9ba5ca29_af337d1e
PS26, Line 17: GD25LQ128C/GD25LQ128D/GD25LQ128E
This ones seem to be added earlier, not in this patch but before.
The table is a good idea, did you mean it to cover everything added in this patch, or everything that supported up to this patch?
It is at the moment the latter (unless I am missing something). Which is also fine, just maybe add the title of the table "Summary: everything that supported up to this patch" or something like that.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62894 )
Change subject: ichspi: Rename HSFC_FDBC -> HSFC_FDBC_MASK
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Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62894/comment/11965152_783e220e
PS6, Line 10: during the data portion of the SPI cycle.
What's the reasoning for this change? The commit message doesn't explain *why* this change would be desired.
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/62894/comment/5f18dd70_e8035cf0
PS4, Line 508: FDBC
> > I have one more question :) […]
Hmmm, if the new macro name doesn't work nicely with the existing code, maybe it wasn't meant to be changed?
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Change subject: ichspi: Define `Write Enable Type (WET)` register under HSFC
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Patch Set 6:
(1 comment)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/62888/comment/6423acef_a3f881ff
PS6, Line 91: /* New HSFC Control bit */
I think this was defined here because it's new with PCH100. Older platforms don't seem to have this bit.
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