April 2022 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: ichspi: Introduce FCYCLE_MASK(n) macro
by Nico Huber (Code Review) 04 Apr '22

04 Apr '22

Attention is currently required from: Subrata Banik, Angel Pons, Anastasia Klimchuk. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62891 ) Change subject: ichspi: Introduce FCYCLE_MASK(n) macro ...................................................................... Patch Set 7: (3 comments) File ichspi.c: https://review.coreboot.org/c/flashrom/+/62891/comment/3998961f_9b166be6 PS6, Line 88: Changed HSFC Control bits These are register fields that changed with Sunrise Point, please keep things grouped by the comments. https://review.coreboot.org/c/flashrom/+/62891/comment/99104afd_66b8ff43 PS6, Line 147: 4K Not always 4K. https://review.coreboot.org/c/flashrom/+/62891/comment/8d884e60_181b1c40 PS6, Line 150: /* : * 4 bits to represents the FCYCLE operation for PCH as: : * 0: SPI Read : * 2: SPI Write : * 3: SPI Erase 4K : * 4: SPI Erase 64K : * 6: SPI RDID : * 7: SPI Write Status : * 8: SPI Read Status : */ : #define HSFC_FCYCLE_BIT_WIDTH_PCH 0xf Please don't mix ICH9 with PCH100 definitions. -- To view, visit https://review.coreboot.org/c/flashrom/+/62891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id222304165610c7ae48e365d72ec8fdeea51c51d Gerrit-Change-Number: 62891 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 04 Apr 2022 10:49:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: ichspi: Define `Write Enable Type (WET)` register under HSFC
by Nico Huber (Code Review) 04 Apr '22

04 Apr '22

Attention is currently required from: Subrata Banik, Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62888 ) Change subject: ichspi: Define `Write Enable Type (WET)` register under HSFC ...................................................................... Patch Set 6: (1 comment) File ichspi.c: https://review.coreboot.org/c/flashrom/+/62888/comment/a5f43823_8cc3b94d PS6, Line 91: /* New HSFC Control bit */ > > I think this was defined here because it's new with PCH100. […] If you have doubts that the bit was introduced with PCH100, you can always test the hardware. -- To view, visit https://review.coreboot.org/c/flashrom/+/62888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f Gerrit-Change-Number: 62888 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Apr 2022 10:49:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in flashrom[master]: ichspi: Unify timeouts across all SPI operations to 30s
by Subrata Banik (Code Review) 04 Apr '22

04 Apr '22

Attention is currently required from: Subrata Banik, Nico Huber, Paul Menzel, Angel Pons, Anastasia Klimchuk. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62867 ) Change subject: ichspi: Unify timeouts across all SPI operations to 30s ...................................................................... Patch Set 8: (1 comment) File ichspi.c: https://review.coreboot.org/c/flashrom/+/62867/comment/0c2222e6_96ca7802 PS8, Line 68: */ > This comment is much too long, starts by describing the past state of the > code and references a specific flash chip which it shouldn't. Also, first > calculating 2.065s and then concluding 30s probably raises more questions > than are answered. > > It should be possible to boil it down to 2 or 3 sentences, preferably in > the commit message and not as a code comment. If Intel would update the > public datasheets, we could also reference those. If not, we could also > add it to Documentation/. Intel has updated the ADL SPI programming guide which I believe is not in public domain, so we need to have the explanation behind the increased timeout logic. I agreed with you that, this is too verbose and can be optimised. Are you recommending to remove the comments from code block and only keep in the commit section alone ? -- To view, visit https://review.coreboot.org/c/flashrom/+/62867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b Gerrit-Change-Number: 62867 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 04 Apr 2022 10:34:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in flashrom[master]: ichspi: Unify timeouts across all SPI operations to 30s
by Nico Huber (Code Review) 04 Apr '22

04 Apr '22

Attention is currently required from: Subrata Banik, Paul Menzel, Angel Pons, Anastasia Klimchuk. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62867 ) Change subject: ichspi: Unify timeouts across all SPI operations to 30s ...................................................................... Patch Set 8: (2 comments) Patchset: PS5: > > I think the reason to use smaller timeout values in some cases is to avoid unnecessary delays. […] Angel, the background is that there is a hardware component that arbitrates between the multiple integrated masters (host, me, gbe, ec, ...). When the bus is kept busy by one master, execution of a transaction of another master, e.g. ours, will be delayed. There is no way for us to know for how long so we need to wait for the worst case (every master happens to erase a block at the same time). This arbitration was never documented AFAIK but if one thinks about it, it's the only reasonable way to explain how it works with the given register interfaces. We could still have distinct timeouts, but the difference would seem marginal because it would be something like <worst-case-other-masters> + 100ms vs. <worst-case-other-masters> + 5s If that worst case time is high, it makes no difference. (the above information is roughly what I would expect in the commit message) File ichspi.c: https://review.coreboot.org/c/flashrom/+/62867/comment/27513014_0473af01 PS8, Line 68: */ This comment is much too long, starts by describing the past state of the code and references a specific flash chip which it shouldn't. Also, first calculating 2.065s and then concluding 30s probably raises more questions than are answered. It should be possible to boil it down to 2 or 3 sentences, preferably in the commit message and not as a code comment. If Intel would update the public datasheets, we could also reference those. If not, we could also add it to Documentation/. -- To view, visit https://review.coreboot.org/c/flashrom/+/62867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b Gerrit-Change-Number: 62867 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 04 Apr 2022 10:25:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: flashchips: enable write-protection for W25Q{64,128}.V
by Edward O'Callaghan (Code Review) 04 Apr '22

04 Apr '22

Attention is currently required from: Nico Huber, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59071 ) Change subject: flashchips: enable write-protection for W25Q{64,128}.V ...................................................................... Patch Set 24: Code-Review+1 -- To view, visit https://review.coreboot.org/c/flashrom/+/59071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iccb69a8d3a0dd2192e2c938caddaf07b1889ed35 Gerrit-Change-Number: 59071 Gerrit-PatchSet: 24 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Mon, 04 Apr 2022 05:58:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: writeprotect: add WPS bit and set it to zero
by Edward O'Callaghan (Code Review) 04 Apr '22

04 Apr '22

Attention is currently required from: Nico Huber, Nikolai Artemiev, Anastasia Klimchuk, Sergii Dmytruk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/60231 ) Change subject: writeprotect: add WPS bit and set it to zero ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/60231/comment/71b4cf1c_df82fd08 PS8, Line 9: proper support Can you elaborate about this and why it perhaps cannot just be done in the immediate sense here in this patch? -- To view, visit https://review.coreboot.org/c/flashrom/+/60231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2c26ec65d64a3b6fb1f1a73690bc771415db2744 Gerrit-Change-Number: 60231 Gerrit-PatchSet: 8 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Mon, 04 Apr 2022 05:57:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: tests: assert pathname and flags when calling open()
by Daniel Campello (Code Review) 04 Apr '22

04 Apr '22

Attention is currently required from: Sam McNally, Edward O'Callaghan. Daniel Campello has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63227 ) Change subject: tests: assert pathname and flags when calling open() ...................................................................... Patch Set 7: (1 comment) File tests/tests.c: https://review.coreboot.org/c/flashrom/+/63227/comment/08938044_939b1e82 PS6, Line 77: wrap_open_and_friends > That is what I mean by "unexpected behavior" as `open_state` being non-NULL implies a builtin versio […] Added assertion for that case on io_mock_register() -- To view, visit https://review.coreboot.org/c/flashrom/+/63227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib46ca5b854c8453ec02ae09f3151cd4d25f988eb Gerrit-Change-Number: 63227 Gerrit-PatchSet: 7 Gerrit-Owner: Daniel Campello <campello(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Mon, 04 Apr 2022 05:36:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Comment-In-Reply-To: Daniel Campello <campello(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: tests: assert pathname and flags when calling open()
by Daniel Campello (Code Review) 04 Apr '22

04 Apr '22

Attention is currently required from: Sam McNally, Daniel Campello. Hello Sam McNally, build bot (Jenkins), Edward O'Callaghan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/63227 to look at the new patch set (#7). Change subject: tests: assert pathname and flags when calling open() ...................................................................... tests: assert pathname and flags when calling open() With this change the wrappers for mock and friends are able to take an optional io_mock_open_state struct to assert expected pathnames and flags whenever an open operation is called. Based partially on https://review.coreboot.org/c/flashrom/+/62319/5 BUG=b:227404721,b:217629892,b:215255210 TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom BRANCH=none Signed-off-by: Daniel Campello <campello(a)chromium.org> Co-Author: Edward O'Callaghan <quasisec(a)google.com> Change-Id: Ib46ca5b854c8453ec02ae09f3151cd4d25f988eb --- M tests/io_mock.c M tests/io_mock.h M tests/lifecycle.c M tests/tests.c 4 files changed, 39 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/27/63227/7 -- To view, visit https://review.coreboot.org/c/flashrom/+/63227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib46ca5b854c8453ec02ae09f3151cd4d25f988eb Gerrit-Change-Number: 63227 Gerrit-PatchSet: 7 Gerrit-Owner: Daniel Campello <campello(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Daniel Campello <campello(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: ichspi: Introduce HSFC CYCLE READ/WRITE/ERASE macros
by Subrata Banik (Code Review) 04 Apr '22

04 Apr '22

Attention is currently required from: Subrata Banik, Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62868 ) Change subject: ichspi: Introduce HSFC CYCLE READ/WRITE/ERASE macros ...................................................................... Patch Set 12: (2 comments) File ichspi.c: https://review.coreboot.org/c/flashrom/+/62868/comment/6447fb57_2f4aa9cf PS12, Line 163: #define HSFC_FCYCLE(cyc) ((cyc) << HSFC_FCYCLE_OFF) > Isn't this equivalent to `HSFC_FCYCLE_MASK`? Apparently it look same as its used for bit shift HSFC_FCYCLE_MASK: to represent the FCYCLE bit shift between ICH and PCH. HSFC_FCYCLE: takes SPI operation as argument and generate the the FCYCLE value for the same. Do you have suggestion to unifies both in meaningful way ? https://review.coreboot.org/c/flashrom/+/62868/comment/92ef7b7d_8ad08b43 PS12, Line 166: 4K > Is it always 4K? atleast on PCH chipsets I could see it's since SPT PCH and Nico has mentioned some history here https://review.coreboot.org/c/flashrom/+/62870/6..8//COMMIT_MSG#b10 -- To view, visit https://review.coreboot.org/c/flashrom/+/62868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3ea74b668e5f8d8e4b3da2a8ad8b81f1813e1e80 Gerrit-Change-Number: 62868 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 04 Apr 2022 04:49:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in flashrom[master]: flashchips: Add AT45DB641E
by Savva Mitrofanov (Code Review) 04 Apr '22

04 Apr '22

Savva Mitrofanov has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/63345 ) Change subject: flashchips: Add AT45DB641E ...................................................................... flashchips: Add AT45DB641E Also use EDI(Extended Device Information) to differentiate AT45DB641E and AT45DB642D. I have successfully tested it with CH341A-programmer. Signed-off-by: Savva Mitrofanov <sk.mitrofanov(a)ispras.ru> Change-Id: I56843b02bee74918a5131326627941ea82003f1f --- M flashchips.c M flashchips.h 2 files changed, 44 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/45/63345/1 diff --git a/flashchips.c b/flashchips.c index acb7718..4626f5c 100644 --- a/flashchips.c +++ b/flashchips.c @@ -3136,6 +3136,48 @@ { .vendor = "Atmel", + .name = "AT45DB641E", + .bustype = BUS_SPI, + .manufacture_id = ATMEL_ID, + .model_id = ATMEL_AT45DB641E, + .total_size = 8192, /* or 8448, determined from status register */ + .page_size = 256, /* or 264, determined from status register */ + /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ + /* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */ + .feature_bits = FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_at45db, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {256, 32768} }, + .block_erase = spi_erase_at45db_page, + }, { + .eraseblocks = { {8 * 256, 32768/8} }, + .block_erase = spi_erase_at45db_block, + }, { + .eraseblocks = { + {8 * 256, 1}, + {1016 * 256, 1}, + {1024 * 256, 31}, + }, + .block_erase = spi_erase_at45db_sector + }, { + .eraseblocks = { {8192 * 1024, 1} }, + .block_erase = spi_erase_at45db_chip, + } + }, + .printlock = spi_prettyprint_status_register_at45db, + .unlock = spi_disable_blockprotect_at45db, /* Impossible if locked down or #WP is low */ + /* granularity will be set by the probing function. */ + .write = spi_write_at45db, + .read = spi_read_at45db, /* Fast read (0x0B) supported */ + .voltage = {1700, 3600}, + }, + + { + .vendor = "Atmel", .name = "AT49(H)F010", .bustype = BUS_PARALLEL, .manufacture_id = ATMEL_ID, diff --git a/flashchips.h b/flashchips.h index ba97719..654b973 100644 --- a/flashchips.h +++ b/flashchips.h @@ -193,7 +193,8 @@ #define ATMEL_AT45DB321E /* same as above but with EDI 0x0100 */ #define ATMEL_AT45DB321D 0x2701 /* Buggy data sheet */ #define ATMEL_AT45DB642 /* No ID (opcode) available for AT45DB642 */ -#define ATMEL_AT45DB642D 0x2800 +#define ATMEL_AT45DB642D 0x280000 +#define ATMEL_AT45DB641E 0x280001 #define ATMEL_AT49BV512 0x03 /* Same as AT49F512 */ #define ATMEL_AT49F001N 0x05 /* Same as AT49F001 */ #define ATMEL_AT49F001NT 0x04 /* Same as AT49F001T */ -- To view, visit https://review.coreboot.org/c/flashrom/+/63345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I56843b02bee74918a5131326627941ea82003f1f Gerrit-Change-Number: 63345 Gerrit-PatchSet: 1 Gerrit-Owner: Savva Mitrofanov <savvamtr(a)gmail.com> Gerrit-MessageType: newchange

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