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Change subject: ch341a_spi.c: Reset device before use
......................................................................
Patch Set 1:
(1 comment)
File ch341a_spi.c:
https://review.coreboot.org/c/flashrom/+/63258/comment/c85474e4_e6a02306
PS1, Line 452: if (ret != 0) {
From the libusb API doc:
"If the reset fails, [...]. This means that the device handle is no longer valid [...]."
A no longer valid libusb handle is not caught.
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Change subject: programmer: Use C linkage when compiling with C++
......................................................................
Patch Set 1: Code-Review-1
(1 comment)
Patchset:
PS1:
flashrom is entirely written in C and should only be compiled with a proper C compiler. Since programmer.h is a internal header of flashrom I see no need to guard id for C++ usage.
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Change subject: dmi.c: Hide has_dmi_support global behind method
......................................................................
Patch Set 4: Code-Review+2
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Change subject: flashchips: enable write-protection for W25Q{64,128}.V
......................................................................
Patch Set 25:
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/59071/comment/ce844fbb_27a4c755
PS25, Line 18017: W25Q64JV
> We already have the same name in the entry below (with a different […]
Thanks, I didn't notice that this entry was added. I think proposed names are correct.
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Change subject: spi25_statusreg.c: add SR3 read/write support
......................................................................
Patch Set 9:
(1 comment)
File flash.h:
https://review.coreboot.org/c/flashrom/+/60230/comment/407f5415_fe88f429
PS2, Line 148: FEATURE_SR3
> As mentioned above SR2 is a different case no matter what we do, as […]
I think Nico is right and this flag is not actually useful, because it never on its own controls whether SR3 access will occur. Removed it.
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Hello build bot (Jenkins), Nico Huber, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59709
to look at the new patch set (#23).
Change subject: [RFC][OTP] spi25_statusreg: support reading/writing security register
......................................................................
[RFC][OTP] spi25_statusreg: support reading/writing security register
Not to be confused with "secure registers" of OTP.
Security register is a dedicated status register for security-related
bits. You don't write its value directly, issuing corresponding write
command with no data just sets OTP bit to 1 automatically.
No WREN is necessary, but at least some datasheets indicate BUSY state
after write command.
Unlike cases where OTP bit is part of SR and can only be written while
in OTP mode, security register can only be written outside of the mode.
Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M flash.h
M spi.h
M spi25_statusreg.c
3 files changed, 75 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/59709/23
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