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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62867
to look at the new patch set (#9).
Change subject: ichspi: Unify timeouts across all SPI operations to 30s
......................................................................
ichspi: Unify timeouts across all SPI operations to 30s
`ich_hwseq_wait_for_cycle_complete()` drops taking `timeout` as argument
in favor of a fixed timeout of `30 seconds` for any given SPI operation
as recommended by the SPI programming guide.
Document: Alder Lake-P Client Platform SPI Programming Guide
Rev 1.30 (supporting document for multi-master accessing the
SPI Flash device.)
Refer to below section to understand the problem in more detail and SPI
operation timeout recommendation from Intel in multi-master
scenarios.
On Intel Chipsets that support multi-mastering access of the SPI flash
may run into a timeout failure when the operation initiated from a
single master just follows the SPI operational timeout recommendation
as per the vendor datasheet (example: winbond spiflash W25Q256JV-DTR
specification, table 9.7).
In the multi-master SPI accessing scenario using hardware sequencing
operation, it's impossible to know the actual status of the SPI bus
prior to individual master starting the operation (SPI Cycle In Progress
a.k.a SCIP bit represents the status of SPI operation on individual
master).
Thus, any SPI operation triggered in multi-master environment might need
to account a worst case scenario where the most time consuming operation
might have occupied the SPI bus from a master and an operation initiated
by another master just timed out.
Here is the timeout calculation for any hardware sequencing operation:
Worst Case Operational Delay =
(Maximum Time consumed by a SPI operation + Any marginal
adjustment)
Timeout Recommendation for Hardware Sequencing Operation =
((Worst Case Operational Delay) * (#No. Of SPI Master - 1) +
Current Operational latency)
Assume, on Intel platform with 2 SPI master like, Host CPU and CSE, the
Timeout Calculation for SPI Write Operation would look like as below:
Maximum Time consumed by a SPI Operation = 2 seconds
(for SPI Erase Operation as per Winbond Data Sheet)
Worst Case Operational Delay = (2 seconds + 50 milliseconds) =
2 seconds 50 milliseconds
Timeout Recommendation for Hardware Seq Operation =
(2 seconds 50 milliseconds) * (2 - 1) + 15 milliseconds
(for SPI Write Operation as per Winbond Data Sheet)
= 2 seconds 65 milliseconds
The timeout value for SPI Hardware Sequencing is defined here based on
the maximum number of master with SPI flash access and worst case SPI
operation time. For example: SPI programming guide on PCH 600 series
defines 5 master sections as HOST CPU/BIOS, CSE, GBE, EC and one reserved.
A rough calculation for the worst case operation a.k.a SPI erase might
take ~5 seconds, hence, the safest timeout value might be
(5 * ~5sec) + 5sec (keeping some buffer) = 30 seconds.
BUG=b:223630977
TEST=Able to perform read/write/erase operation on PCH 600 series
chipset (board name: Brya).
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b
---
M ichspi.c
1 file changed, 9 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/67/62867/9
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/56023 )
Change subject: board_enable.c: Add ME unlock function for Clevo laptops
......................................................................
Patch Set 15:
(1 comment)
File board_enable.c:
https://review.coreboot.org/c/flashrom/+/56023/comment/0455bd99_c1dfb970
PS2, Line 2339: return 0;
I gave it a try and extracted a separate tool in CB:63416, the question is whether it's OK for it to link to 48 source files of flashrom... All of them are needed for successful linking, I've added an SVG depicting module dependencies to show how interdependent everything is.
> It should be possible to use the board_status infrastructure without going through the programmer/flash API.
Even pcidev.c depends on programmer, because it uses register_shutdown() and thus brings in half of flashrom.
Please take a look and say what you think about a tool like that.
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Hello build bot (Jenkins), Nico Huber, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62899
to look at the new patch set (#7).
Change subject: Endian conversion: move to platform.h and platform/endian*.c
......................................................................
Endian conversion: move to platform.h and platform/endian*.c
Starting to move the platform dependent code to platform/ and provide
the abstraction through the platform.h header.
Change-Id: I35640282d451960f2a329ae24339ec05dbae6d30
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
---
M Makefile
M hwaccess_physmap.c
M meson.build
R platform.h
R platform/endian_big.c
R platform/endian_little.c
6 files changed, 12 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/99/62899/7
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Hello Felix Singer, build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Nikolai Artemiev, Peter Marheine,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62898
to look at the new patch set (#7).
Change subject: hwaccess: replace macros by C code
......................................................................
hwaccess: replace macros by C code
Split the code for endian conversion into separate files for big and
little endian. The buildsystem selects the correct file for the used
endianness. Replace the swab macros with `static inline` c functions.
Define macros for returning the same or swapped value. Call those macros
in the endian specific files.
Change-Id: I86d38d816b37c283279c485fac8027f8fb94364a
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
---
M Makefile
M hwaccess.h
A hwaccess_endian_big.c
A hwaccess_endian_little.c
M meson.build
5 files changed, 167 insertions(+), 67 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/98/62898/7
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