April 2022 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: tests: assert pathname and flags when calling open()
by Anastasia Klimchuk (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Sam McNally, Daniel Campello. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63227 ) Change subject: tests: assert pathname and flags when calling open() ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/63227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib46ca5b854c8453ec02ae09f3151cd4d25f988eb Gerrit-Change-Number: 63227 Gerrit-PatchSet: 10 Gerrit-Owner: Daniel Campello <campello(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Daniel Campello <campello(a)chromium.org> Gerrit-Comment-Date: Wed, 06 Apr 2022 00:51:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: dummyflasher: add SR2 and SR3 emulation harness
by Edward O'Callaghan (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Nico Huber, Angel Pons, Nikolai Artemiev, Sergii Dmytruk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59072 ) Change subject: dummyflasher: add SR2 and SR3 emulation harness ...................................................................... Patch Set 30: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/59072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59 Gerrit-Change-Number: 59072 Gerrit-PatchSet: 30 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 00:48:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: flashchips: enable write-protection for W25Q{64,128}.V
by Edward O'Callaghan (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Nico Huber, Angel Pons, Sergii Dmytruk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59071 ) Change subject: flashchips: enable write-protection for W25Q{64,128}.V ...................................................................... Patch Set 26: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/59071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iccb69a8d3a0dd2192e2c938caddaf07b1889ed35 Gerrit-Change-Number: 59071 Gerrit-PatchSet: 26 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 00:46:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: writeprotect.c: refactor and fix wp_mode functions
by Edward O'Callaghan (Code Review) 06 Apr '22

06 Apr '22

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62643 ) Change subject: writeprotect.c: refactor and fix wp_mode functions ...................................................................... writeprotect.c: refactor and fix wp_mode functions This is a follow up on commit 12dbc4e04508aecfff53ad95b6f68865da1b4f07. Use a lookup table in get_wp_mode() and drop the srp_bit_present check, since a chip without SRP is just FLASHROM_WP_MODE_DISABLED. Add a srp_bit_present check to set_wp_mode() if the mode requires it. BUG=b:182223106 BRANCH=none TEST=flashrom --wp-{enable,disable,status} on AMD dut Change-Id: Ib6c347453f9216e5816e4ed35bf9783fd3c720e0 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62643 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M writeprotect.c 1 file changed, 13 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved diff --git a/writeprotect.c b/writeprotect.c index 6b3bbcf..5893593 100644 --- a/writeprotect.c +++ b/writeprotect.c @@ -351,16 +351,17 @@ /** Get the mode selected by a WP configuration. */ static int get_wp_mode(enum flashrom_wp_mode *mode, const struct wp_bits *bits) { - if (!bits->srp_bit_present) - return FLASHROM_WP_ERR_CHIP_UNSUPPORTED; + const enum flashrom_wp_mode wp_modes[2][2] = { + { + FLASHROM_WP_MODE_DISABLED, /* srl=0, srp=0 */ + FLASHROM_WP_MODE_HARDWARE, /* srl=0, srp=1 */ + }, { + FLASHROM_WP_MODE_POWER_CYCLE, /* srl=1, srp=0 */ + FLASHROM_WP_MODE_PERMANENT, /* srl=1, srp=1 */ + }, + }; - if (bits->srl_bit_present && bits->srl == 1) { - *mode = bits->srp ? FLASHROM_WP_MODE_PERMANENT : - FLASHROM_WP_MODE_POWER_CYCLE; - } else { - *mode = bits->srp ? FLASHROM_WP_MODE_HARDWARE : - FLASHROM_WP_MODE_DISABLED; - } + *mode = wp_modes[bits->srl][bits->srp]; return FLASHROM_WP_OK; } @@ -375,6 +376,9 @@ return FLASHROM_WP_OK; case FLASHROM_WP_MODE_HARDWARE: + if (!bits->srp_bit_present) + return FLASHROM_WP_ERR_CHIP_UNSUPPORTED; + bits->srl = 0; bits->srp = 1; return FLASHROM_WP_OK; -- To view, visit https://review.coreboot.org/c/flashrom/+/62643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib6c347453f9216e5816e4ed35bf9783fd3c720e0 Gerrit-Change-Number: 62643 Gerrit-PatchSet: 13 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: libflashrom,linux_mtd: add linux_mtd writeprotect support
by Edward O'Callaghan (Code Review) 06 Apr '22

06 Apr '22

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/61897 ) Change subject: libflashrom,linux_mtd: add linux_mtd writeprotect support ...................................................................... libflashrom,linux_mtd: add linux_mtd writeprotect support This commit adds a generic framework to allow opaque programmers to implement writeprotect operations and uses the framework to support writeprotect operations on linux MTD device files. The generic framework comprises three new functions in `struct opaque_master` that are called from libflashrom: - wp_write_cfg() - wp_read_cfg() - wp_get_ranges() For linux_mtd, only the read/write functions are implemented. Linux's MTD interface doesn't provide a way to get available ranges, so calling get_wp_ranges() on the linux_mtd master will return FLASHROM_WP_ERR_RANGE_LIST_UNAVAILABLE. BUG=b:182223106 BRANCH=none TEST=WP ops on hana DUT (MT8173) with W25Q32DW flash TEST=flashrom --wp-enable --wp-range <non-empty> succeeds TEST=flashrom --wp-enable --wp-range <empty> fails as expected TEST=flashrom --wp-disable --wp-range <empty> succeeds TEST=flashrom --wp-disable --wp-range <non-empty> fails as expected TEST=flashrom --wp-status succeeds Change-Id: I5c86e28cdec44bec49ba1d36f8ab62241b9b01da Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/61897 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M libflashrom.c M linux_mtd.c M programmer.h 3 files changed, 132 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved diff --git a/libflashrom.c b/libflashrom.c index 39b0c67..658d812 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -714,14 +714,12 @@ */ enum flashrom_wp_result flashrom_wp_write_cfg(struct flashctx *flash, const struct flashrom_wp_cfg *cfg) { - /* - * TODO: Call custom implementation if the programmer is opaque, as - * direct WP operations require SPI access. In particular, linux_mtd - * has its own WP operations we should use instead. - */ if (flash->mst->buses_supported & BUS_SPI) return wp_write_cfg(flash, cfg); + if (flash->mst->buses_supported & BUS_PROG && flash->mst->opaque.wp_write_cfg) + return flash->mst->opaque.wp_write_cfg(flash, cfg); + return FLASHROM_WP_ERR_OTHER; } @@ -736,14 +734,12 @@ */ enum flashrom_wp_result flashrom_wp_read_cfg(struct flashrom_wp_cfg *cfg, struct flashctx *flash) { - /* - * TODO: Call custom implementation if the programmer is opaque, as - * direct WP operations require SPI access. In particular, linux_mtd - * has its own WP operations we should use instead. - */ if (flash->mst->buses_supported & BUS_SPI) return wp_read_cfg(cfg, flash); + if (flash->mst->buses_supported & BUS_PROG && flash->mst->opaque.wp_read_cfg) + return flash->mst->opaque.wp_read_cfg(cfg, flash); + return FLASHROM_WP_ERR_OTHER; } @@ -761,15 +757,12 @@ */ enum flashrom_wp_result flashrom_wp_get_available_ranges(struct flashrom_wp_ranges **list, struct flashrom_flashctx *flash) { - /* - * TODO: Call custom implementation if the programmer is opaque, as - * direct WP operations require SPI access. We actually can't implement - * this in linux_mtd right now, but we should adopt a proper generic - * architechure to match the read and write functions anyway. - */ if (flash->mst->buses_supported & BUS_SPI) return wp_get_available_ranges(list, flash); + if (flash->mst->buses_supported & BUS_PROG && flash->mst->opaque.wp_get_ranges) + return flash->mst->opaque.wp_get_ranges(list, flash); + return FLASHROM_WP_ERR_OTHER; } diff --git a/linux_mtd.c b/linux_mtd.c index 9d80a51..445a903 100644 --- a/linux_mtd.c +++ b/linux_mtd.c @@ -308,6 +308,123 @@ return 0; } +static enum flashrom_wp_result linux_mtd_wp_read_cfg(struct flashrom_wp_cfg *cfg, struct flashctx *flash) +{ + struct linux_mtd_data *data = flash->mst->opaque.data; + bool start_found = false; + bool end_found = false; + + cfg->mode = FLASHROM_WP_MODE_DISABLED; + cfg->range.start = 0; + cfg->range.len = 0; + + /* Check protection status of each block */ + for (size_t u = 0; u < data->total_size; u += data->erasesize) { + struct erase_info_user erase_info = { + .start = u, + .length = data->erasesize, + }; + + int ret = ioctl(fileno(data->dev_fp), MEMISLOCKED, &erase_info); + if (ret == 0) { + /* Block is unprotected. */ + + if (start_found) { + end_found = true; + } + } else if (ret == 1) { + /* Block is protected. */ + + if (end_found) { + /* + * We already found the end of another + * protection range, so this is the start of a + * new one. + */ + return FLASHROM_WP_ERR_OTHER; + } + if (!start_found) { + cfg->range.start = erase_info.start; + cfg->mode = FLASHROM_WP_MODE_HARDWARE; + start_found = true; + } + cfg->range.len += data->erasesize; + } else { + msg_perr("%s: ioctl: %s\n", __func__, strerror(errno)); + return FLASHROM_WP_ERR_READ_FAILED; + } + + } + + return FLASHROM_WP_OK; +} + +static enum flashrom_wp_result linux_mtd_wp_write_cfg(struct flashctx *flash, const struct flashrom_wp_cfg *cfg) +{ + const struct linux_mtd_data *data = flash->mst->opaque.data; + + const struct erase_info_user entire_chip = { + .start = 0, + .length = data->total_size, + }; + const struct erase_info_user desired_range = { + .start = cfg->range.start, + .length = cfg->range.len, + }; + + /* + * MTD ioctls will enable hardware status register protection if and + * only if the protected region is non-empty. Return an error if the + * cfg cannot be activated using the MTD interface. + */ + if ((cfg->range.len == 0) != (cfg->mode == FLASHROM_WP_MODE_DISABLED)) { + return FLASHROM_WP_ERR_OTHER; + } + + /* + * MTD handles write-protection additively, so whatever new range is + * specified is added to the range which is currently protected. To + * just protect the requsted range, we need to disable the current + * write protection and then enable it for the desired range. + */ + int ret = ioctl(fileno(data->dev_fp), MEMUNLOCK, &entire_chip); + if (ret < 0) { + msg_perr("%s: Failed to disable write-protection, MEMUNLOCK ioctl " + "retuned %d, error: %s\n", __func__, ret, strerror(errno)); + return FLASHROM_WP_ERR_WRITE_FAILED; + } + + if (cfg->range.len > 0) { + ret = ioctl(fileno(data->dev_fp), MEMLOCK, &desired_range); + if (ret < 0) { + msg_perr("%s: Failed to enable write-protection, " + "MEMLOCK ioctl retuned %d, error: %s\n", + __func__, ret, strerror(errno)); + return FLASHROM_WP_ERR_WRITE_FAILED; + } + } + + /* Verify */ + struct flashrom_wp_cfg readback_cfg; + enum flashrom_wp_result read_ret = linux_mtd_wp_read_cfg(&readback_cfg, flash); + if (read_ret != FLASHROM_WP_OK) + return read_ret; + + if (readback_cfg.mode != cfg->mode || + readback_cfg.range.start != cfg->range.start || + readback_cfg.range.len != cfg->range.len) { + return FLASHROM_WP_ERR_VERIFY_FAILED; + } + + return FLASHROM_WP_OK; +} + +static enum flashrom_wp_result linux_mtd_wp_get_available_ranges(struct flashrom_wp_ranges **list, struct flashctx *flash) +{ + /* Not supported by MTD interface. */ + return FLASHROM_WP_ERR_RANGE_LIST_UNAVAILABLE; +} + static const struct opaque_master linux_mtd_opaque_master = { /* max_data_{read,write} don't have any effect for this programmer */ .max_data_read = MAX_DATA_UNSPECIFIED, @@ -317,6 +434,9 @@ .write = linux_mtd_write, .erase = linux_mtd_erase, .shutdown = linux_mtd_shutdown, + .wp_read_cfg = linux_mtd_wp_read_cfg, + .wp_write_cfg = linux_mtd_wp_write_cfg, + .wp_get_ranges = linux_mtd_wp_get_available_ranges, }; /* Returns 0 if setup is successful, non-zero to indicate error */ diff --git a/programmer.h b/programmer.h index 0657bb1..47d2dc3 100644 --- a/programmer.h +++ b/programmer.h @@ -403,6 +403,9 @@ int (*read) (struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int (*write) (struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int (*erase) (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen); + enum flashrom_wp_result (*wp_write_cfg)(struct flashctx *, const struct flashrom_wp_cfg *); + enum flashrom_wp_result (*wp_read_cfg)(struct flashrom_wp_cfg *, struct flashctx *); + enum flashrom_wp_result (*wp_get_ranges)(struct flashrom_wp_ranges **, struct flashctx *); int (*shutdown)(void *data); void *data; }; 38 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/flashrom/+/61897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5c86e28cdec44bec49ba1d36f8ab62241b9b01da Gerrit-Change-Number: 61897 Gerrit-PatchSet: 40 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: flashchips.c: add writeprotect support for more chips
by Edward O'Callaghan (Code Review) 06 Apr '22

06 Apr '22

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62214 ) Change subject: flashchips.c: add writeprotect support for more chips ...................................................................... flashchips.c: add writeprotect support for more chips Chips I had available for testing were tested with all writeprotect commands and an FT232H adapter. Chips I wasn't able to test were just checked against the datasheets. Chips used for testing (including chips added in previous patches) are listed in the table below: Flashrom Chip name | Chip(s) tested ---------------------------------+---------------------------- AT25SL128A | EN25QH128 | GD25LQ128C/GD25LQ128D/GD25LQ128E | GD25LQ128DSIG GD25LQ64(B) | GD25LQ64CWIG GD25Q127C/GD25Q128C | GD25Q127CSIG, GD25Q128ESIG GD25Q256D | GD25Q256DYIG GD25Q64(B) | GD25Q64CSIG W25Q128.JW.DTR | W25Q128.V..M | W25Q128.W | W25Q256JV_M | W25Q256.V | W25Q64.W | XM25QH128C | XM25QH256C | BUG=b:182223106 BRANCH=none TEST=flashrom --wp-{enable,disable,range,list,status} Change-Id: I7f3d4c4148056098a845b5c64308b0333ebda395 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62214 Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M flashchips.c 1 file changed, 138 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index acb7718..3224142 100644 --- a/flashchips.c +++ b/flashchips.c @@ -2414,7 +2414,7 @@ .total_size = 16384, .page_size = 256, /* supports SFDP */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -2442,6 +2442,16 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {1700, 2000}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = decode_range_spi25, }, { @@ -5167,6 +5177,13 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */ + }, + .decode_range = decode_range_spi25, }, { @@ -6483,7 +6500,7 @@ .total_size = 8192, .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -6511,6 +6528,16 @@ .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1695, 1950}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */ + .sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */ + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = decode_range_spi25, }, { @@ -6600,7 +6627,7 @@ .page_size = 256, /* OTP: 1536B total; read 0x48; write 0x42, erase 0x44 */ /* QPI: enable 0x38, disable 0xFF */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -6629,6 +6656,16 @@ .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */ + .sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */ + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = decode_range_spi25, }, { @@ -6895,7 +6932,7 @@ .total_size = 8192, .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR2, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -6923,6 +6960,16 @@ .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */ + .sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */ + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = decode_range_spi25, }, { @@ -17172,7 +17219,7 @@ .model_id = WINBOND_NEX_W25Q128_V_M, .total_size = 16384, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -17200,6 +17247,16 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = decode_range_spi25, }, { @@ -17212,7 +17269,7 @@ .page_size = 256, /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -17240,6 +17297,16 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {1650, 1950}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = decode_range_spi25, }, { @@ -17250,7 +17317,7 @@ .model_id = WINBOND_NEX_W25Q128_DTR, .total_size = 16384, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -17278,6 +17345,16 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {1650, 1950}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = decode_range_spi25, }, { @@ -17410,8 +17487,9 @@ /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN - | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN | + FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | + FEATURE_WRSR2, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -17439,6 +17517,14 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {STATUS1, 6, RW}, + }, + .decode_range = decode_range_spi25, }, { @@ -17452,7 +17538,7 @@ /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_WRSR2, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -17486,6 +17572,15 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = decode_range_spi25, }, { @@ -17946,7 +18041,7 @@ .page_size = 256, /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ /* QPI enable 0x38, disable 0xFF */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -17974,6 +18069,16 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = decode_range_spi25, }, { @@ -19308,7 +19413,7 @@ .model_id = XMC_XM25QH128C, .total_size = 16384, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -19336,6 +19441,16 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = decode_range_spi25, }, { @@ -19389,8 +19504,9 @@ /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN - | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN | + FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | + FEATURE_WRSR2, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -19418,6 +19534,14 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {STATUS1, 6, RW}, + }, + .decode_range = decode_range_spi25, }, { -- To view, visit https://review.coreboot.org/c/flashrom/+/62214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7f3d4c4148056098a845b5c64308b0333ebda395 Gerrit-Change-Number: 62214 Gerrit-PatchSet: 28 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: cli_classic: add writeprotect CLI
by Edward O'Callaghan (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Nico Huber, Paul Menzel, Angel Pons, Nikolai Artemiev, Sergii Dmytruk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58738 ) Change subject: cli_classic: add writeprotect CLI ...................................................................... Patch Set 76: Code-Review+2 (1 comment) File cli_classic.c: https://review.coreboot.org/c/flashrom/+/58738/comment/bd8e4d88_65a6edeb PS76, Line 62: " --wp-disable disable write protection\n" : " --wp-enable enable write protection\n" : " --wp-list list supported write protection ranges\n" : " --wp-status show write protection status\n" : " --wp-range=<start>,<len> set write protection range (use --wp-range=0,0\n" : " to unprotect the entire flash)\n" : " --wp-region <region> set write protection region\n" This commit should include the relevant man page updates. -- To view, visit https://review.coreboot.org/c/flashrom/+/58738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I499f521781ee8999921996517802c0c0c641d869 Gerrit-Change-Number: 58738 Gerrit-PatchSet: 76 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Tue, 05 Apr 2022 22:44:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: dmi.c: Ensure g_has_dmi_support is default on shutdown
by Edward O'Callaghan (Code Review) 06 Apr '22

06 Apr '22

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62996 ) Change subject: dmi.c: Ensure g_has_dmi_support is default on shutdown ...................................................................... dmi.c: Ensure g_has_dmi_support is default on shutdown Ensure the g_has_dmi_support variable has the default state of false after the life-time has expired. BUG=none TEST=builds Change-Id: I0674950304736e53d014117d287682a4f6349879 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62996 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Thomas Heijligen <src(a)posteo.de> Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M dmi.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Thomas Heijligen: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Nikolai Artemiev: Looks good to me, but someone else must approve diff --git a/dmi.c b/dmi.c index a82b494..7c0fc4c 100644 --- a/dmi.c +++ b/dmi.c @@ -386,6 +386,7 @@ free(dmi_strings[i].value); dmi_strings[i].value = NULL; } + g_has_dmi_support = false; return 0; } 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/flashrom/+/62996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0674950304736e53d014117d287682a4f6349879 Gerrit-Change-Number: 62996 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: dmi.c: Ensure g_has_dmi_support is default on shutdown
by Edward O'Callaghan (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Angel Pons. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62996 ) Change subject: dmi.c: Ensure g_has_dmi_support is default on shutdown ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/62996/comment/20d05524_d210557a PS1, Line 9: the g_has_dmi_support > nit: the g_has_dmi_support *variable* Done -- To view, visit https://review.coreboot.org/c/flashrom/+/62996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0674950304736e53d014117d287682a4f6349879 Gerrit-Change-Number: 62996 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 05 Apr 2022 22:41:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in flashrom[master]: dmi.c: Ensure g_has_dmi_support is default on shutdown
by Edward O'Callaghan (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Edward O'Callaghan. Hello build bot (Jenkins), Thomas Heijligen, Angel Pons, Nikolai Artemiev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/62996 to look at the new patch set (#2). Change subject: dmi.c: Ensure g_has_dmi_support is default on shutdown ...................................................................... dmi.c: Ensure g_has_dmi_support is default on shutdown Ensure the g_has_dmi_support variable has the default state of false after the life-time has expired. BUG=none TEST=builds Change-Id: I0674950304736e53d014117d287682a4f6349879 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M dmi.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/62996/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/62996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0674950304736e53d014117d287682a4f6349879 Gerrit-Change-Number: 62996 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newpatchset

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