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Change subject: ichspi: Define `Write Enable Type (WET)` register under HSFC
......................................................................
ichspi: Define `Write Enable Type (WET)` register under HSFC
This patch moves the `WET` macro definition under HSFC offset to make
it more readable.
BUG=b:223630977
TEST=Able to perform read/write/erase operation on brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f
---
M ichspi.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/62888/2
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I'd like you to reexamine a change. Please visit
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Change subject: ichspi: Unify timeout (5sec) across all SPI operations
......................................................................
ichspi: Unify timeout (5sec) across all SPI operations
This patch removes taking `timeout` argument for different operations
using `ich_hwseq_wait_for_cycle_complete()`. Make use of 5sec unified
timeout for all SPI operations.
Document Number: TBD (supporting document for multi-master accessing
the SPI Flash device is awaited from Intel.)
BUG=b:223630977
TEST=Able to perform read/write/erase/status operation on brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b
---
M ichspi.c
1 file changed, 37 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/67/62867/4
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I'd like you to reexamine a change. Please visit
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Change subject: ichspi: Add support for 64KB SPI erase operation
......................................................................
ichspi: Add support for 64KB SPI erase operation
This patch add support for SPI HW sequencing 64KB erase operation based
on erase_block size and `only_4k` flag is not set.
BUG=b:223630977
TEST=Able to perform SPI erase operation on brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I534471dc8eeeed66e5cbc44baadcd2448d21d34d
---
M ichspi.c
1 file changed, 7 insertions(+), 2 deletions(-)
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62870
to look at the new patch set (#3).
Change subject: ichspi: Add support for 64KB SPI erase operation
......................................................................
ichspi: Add support for 64KB SPI erase operation
This patch add support for SPI HW sequencing 64KB erase operation based
on erase_block size and `only_4k` flag is not set.
BUG=b:223630977
TEST=Able to perform SPI erase operation on brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I534471dc8eeeed66e5cbc44baadcd2448d21d34d
---
M ichspi.c
1 file changed, 7 insertions(+), 2 deletions(-)
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: ichspi: Refactor Flashrom HW Sequencing Operation
......................................................................
ichspi: Refactor Flashrom HW Sequencing Operation
List of changes:
1. Add a unified `execute SPI flash transfer` function that does:
- Check the SCIP bit prior initiate new operation.
- Start the transfer by setting address and length for transfer,
finally set FGO bit.
- Wait for the transaction to get completed/failed/timed out.
2. All HW Sequencing SPI operation uses `execute SPI flash transfer`
function
BUG=b:223630977
TEST=Able to perform flash read/write/erase operation on brya
without any failure.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ic9fd50841449e02f476a8834f4642d6ecad36dc3
---
M ichspi.c
1 file changed, 42 insertions(+), 52 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/69/62869/3
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62868 )
Change subject: ichspi: Introduce HSFC CYCLE READ/WRITE/ERASE macros
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62868/comment/f4f91b0f_088dad88
PS1, Line 9: List of changes:
: 1. Introduced useful macros (read/write/erase/status etc.) and used
: throughout the SPI operations.
: 2. Drop unused macros.
: 3. SPI operations are using `control register (offset 0x6)` hence
: converted 32-bit reads into 16-bit read to cover the only hardware
: sequencing control register alone.
> commit message is also misaligned with the patch content. For example (3) doesn't apply here?
rebased this CL after addressing this review comment.
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