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Change subject: pcidev: Move pci_card_find() from internal to canonical place
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
Patchset:
PS5:
This patch also renames the function. This is not mentioned anywhere. The move if also a duplicate of CB:55848. IMO separate patches would be nicer.
+1 for the content, I'm fine with it. Please have a look at other patches touching the same code.
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Change subject: print_buildinfo: remove unreachable print of libpci version
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS1:
> How about we define something in the Makefile that can be used literally? roughly: […]
Can we keep this in mind for later and an other patch?
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Change subject: hwaccess: replace macros by C code
......................................................................
Patch Set 6:
(5 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62898/comment/48cfa498_d73abedf
PS5, Line 9: seperate
> sep*a*rate
Done
https://review.coreboot.org/c/flashrom/+/62898/comment/f8770b71_d8756fcc
PS5, Line 11: endiannes
> one more `s`
Done
https://review.coreboot.org/c/flashrom/+/62898/comment/1cc594c3_455d5d9f
PS5, Line 12: swaped
> another `p`, i.e. `swapped` also a lot in the code.
Done
Patchset:
PS6:
Patch set 6: mostly cosmetic fixes.
File hwaccess.h:
https://review.coreboot.org/c/flashrom/+/62898/comment/f602b9ed_d4215d17
PS5, Line 30: return ((value & (uint16_t)0x00ffU) << 8) |
> Maybe add another space after `return` for alignment?
Done, corrected also the code of the function. This was the code from swap16, not swap8
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Hello build bot (Jenkins), Nico Huber, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
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Change subject: Endian conversion: move to platform.h and platform/endian*.c
......................................................................
Endian conversion: move to platform.h and platform/endian*.c
Starting to move the platform dependent code to platform/ and provide
the abstraction through the platform.h header.
Change-Id: I35640282d451960f2a329ae24339ec05dbae6d30
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
---
M Makefile
M hwaccess_physmap.c
M meson.build
R platform.h
R platform/endian_big.c
R platform/endian_little.c
6 files changed, 12 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/99/62899/6
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I'd like you to reexamine a change. Please visit
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Change subject: hwaccess: replace macros by C code
......................................................................
hwaccess: replace macros by C code
Split the code for endian conversion into separate files for big and
little endian. The buildsystem selects the correct file for the used
endianness. Replace the swab macros with `static inline` c functions.
Define macros for returning the same or swapped value. Call those macros
in the endian specific files.
Change-Id: I86d38d816b37c283279c485fac8027f8fb94364a
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---
M Makefile
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A hwaccess_endian_big.c
A hwaccess_endian_little.c
M meson.build
5 files changed, 167 insertions(+), 67 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/98/62898/6
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62870 )
Change subject: ichspi: Add support for 64KB SPI erase operation
......................................................................
Patch Set 6:
(4 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62870/comment/2b713e80_696c358a
PS6, Line 9: This patch add support for SPI HW sequencing 64KB erase operation based
Excuse my ignorance, but could you start with an introduction of the functionality. Is that a feature of new devices?
https://review.coreboot.org/c/flashrom/+/62870/comment/3e5353eb_b0be52ce
PS6, Line 9: based
: on erase_block size and `only_4k` flag is not set
I do not know the whole code, but where is the `only_4k` done in the diff?
https://review.coreboot.org/c/flashrom/+/62870/comment/2662cb13_f6cec9f2
PS6, Line 13: TEST=Able to perform SPI erase operation on brya.
Are they faster now?
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/62870/comment/1c03bff0_32c144f6
PS6, Line 1476: if (erase_block == 64 * KiB)
: erase_cycle = HSFC_CYCLE_64K_ERASE;
: else
: erase_cycle = HSFC_CYCLE_4K_ERASE;
Use ternary operator?
erase_cycle = (erase_block == 64 * KiB) ? HSFC_CYCLE_64K_ERASE : HSFC_CYCLE_4K_ERASE;
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Change subject: ichspi: Add support for 64KB SPI erase operation
......................................................................
ichspi: Add support for 64KB SPI erase operation
This patch adds support for SPI HW sequencing 64KB erase operation based
on erase_block size and `only_4k` flag is not set.
BUG=b:223630977
TEST=Able to perform SPI erase operation on brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I534471dc8eeeed66e5cbc44baadcd2448d21d34d
---
M ichspi.c
1 file changed, 7 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/70/62870/7
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