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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62888
to look at the new patch set (#5).
Change subject: ichspi: Define `Write Enable Type (WET)` register under HSFC
......................................................................
ichspi: Define `Write Enable Type (WET)` register under HSFC
This patch moves the `WET` macro definition under HSFC offset to make
it more readable.
BUG=b:223630977
TEST=Observe no difference (with below operation) in final binary with
and without this CL.
> make clean && make CONFIG_EVERYTHING=yes VERSION=none
> diff binary_before binary_after
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f
---
M ichspi.c
1 file changed, 2 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/62888/5
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62867
to look at the new patch set (#7).
Change subject: ichspi: Unify timeout (30sec) across all SPI operations
......................................................................
ichspi: Unify timeout (30sec) across all SPI operations
This patch removes taking `timeout` argument for different operations
using `ich_hwseq_wait_for_cycle_complete()`. Make use of 30sec unified
timeout for all SPI operations.
Document Number: Alder Lake-P Client Platform SPI Programming Guide
Rev 1.30 (supporting document for multi-master
accessing the SPI Flash device.)
BUG=b:223630977
TEST=Able to perform read/write/erase operation on PCH 600 series
chipset (board name: Brya).
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b
---
M ichspi.c
1 file changed, 44 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/67/62867/7
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62888 )
Change subject: ichspi: Define `Write Enable Type (WET)` register under HSFC
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62888/comment/9d782ef7_4bbdcb85
PS3, Line 13: brya
> What chipset brya has? It would be useful to have this info in commit message.
Ack
Patchset:
PS3:
> This change should not change the binary, is it right? (please tell me if I am wrong) […]
Ack
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/62888/comment/fef299e7_14e80329
PS3, Line 83: /* New HSFC Control bit */
> This comment should be moved too?
I think we can remove this comment as well.
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62888
to look at the new patch set (#4).
Change subject: ichspi: Define `Write Enable Type (WET)` register under HSFC
......................................................................
ichspi: Define `Write Enable Type (WET)` register under HSFC
This patch moves the `WET` macro definition under HSFC offset to make
it more readable.
BUG=b:223630977
TEST=Observe no change in final binary with and without this CL.
> make clean && make CONFIG_EVERYTHING=yes VERSION=none`
> diff binary_before binary_after
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f
---
M ichspi.c
1 file changed, 2 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/62888/4
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62867 )
Change subject: ichspi: Unify timeout (30sec) across all SPI operations
......................................................................
Patch Set 6:
(2 comments)
Patchset:
PS5:
> Just curious, what was the reason for using two different timeouts?
didn't get you, can you please point me about 2 different timeout ?
Typically timeout values are derived from SPI flash vendor spec https://www.winbond.com/resource-files/w25q256jv%20dtr%20revc%2010252016.pdf
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/62867/comment/877d5b2f_fd2a0771
PS5, Line 33: /* Sunrise Point */
> This "Sunrise Point" comment used to be above HSFS status bits macros, maybe it should be moved back […]
Ack
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62867
to look at the new patch set (#6).
Change subject: ichspi: Unify timeout (30sec) across all SPI operations
......................................................................
ichspi: Unify timeout (30sec) across all SPI operations
This patch removes taking `timeout` argument for different operations
using `ich_hwseq_wait_for_cycle_complete()`. Make use of 30sec unified
timeout for all SPI operations.
Document Number: Alder Lake-P Client Platform SPI Programming Guide
Rev 1.30 (supporting document for multi-master
accessing the SPI Flash device.)
BUG=b:223630977
TEST=Able to perform read/write/erase/status operation on PCH 600
series chipset (board name: Brya).
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b
---
M ichspi.c
1 file changed, 44 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/67/62867/6
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Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59280 )
Change subject: pcidev: Move pci_dev_find() from internal to canonical place
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
Patchset:
PS5:
Same as previous patch, this is also done by CB:55848. Reorder the prototypes in programmer.h could be an own patch. Maybe relocating all relevant prototypes at once.
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