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Change subject: libflashrom,writeprotect: add functions for reading/writing WP configs
......................................................................
Patch Set 29:
(5 comments)
Patchset:
PS22:
> That sounds good. I'm working on implementing it now.
Done.
I've also moved all libflashrom functions to libflashrom.c to make way for linux_mtd support.
File libflashrom.h:
https://review.coreboot.org/c/flashrom/+/58479/comment/3e0bb11b_3647a7f6
PS27, Line 133: };
> That sounds good to me, it's good to address ABI stability problems early on. […]
I went with the second option for the range list. Resolving as the original comment is done and CB:58481 is a better place to discuss the range list functions.
File libflashrom.h:
https://review.coreboot.org/c/flashrom/+/58479/comment/1f1abd47_8c6370b8
PS22, Line 125: software
> I've removed the comment now, mentioning software protection is confusing/inaccurate since software […]
Resolving.
File writeprotect.c:
https://review.coreboot.org/c/flashrom/+/58479/comment/a0df967a_3f696fbe
PS22, Line 56: struct wp_chip_config *cfg
> Undoing done
Done
https://review.coreboot.org/c/flashrom/+/58479/comment/e34d3c83_ffcfb806
PS22, Line 145: which of two configurations should be used if they both select the same
: * protection range
> This was kind of an adaptation of an earlier function that just compared ranges so they could be sor […]
Done
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Change subject: flashchips: add writeprotect bit layout map to chips
......................................................................
Patch Set 27:
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/58477/comment/e2ec5feb_a94dda0f
PS20, Line 6353: .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */
: .sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */
> IMO we should definitely use the naming by the bit's function, like you did. […]
Done in the code, though I'm not sure how I should create an account to edit the wiki.
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Change subject: spi25_statusreg,flashchips: add SR2 read/write support
......................................................................
Patch Set 24:
(3 comments)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/58570/comment/f0312092_2cdbb77a
PS18, Line 6711: FEATURE_WRSR_EXT
> > And a comment about the datasheet oddity would be nice. […]
I just added it as a comment at the end of the line, that seems to be fairly standard for flashchips.c.
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/58570/comment/b2e85df1_4d1f47f0
PS23, Line 94:
> A bright pink space :)
Done
https://review.coreboot.org/c/flashrom/+/58570/comment/9b22900c_7c880664
PS23, Line 116: *
> This can be removed (you have two asterisks).
Done
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Change subject: spi25_statusreg: make register read/write functions generic
......................................................................
Patch Set 21:
(2 comments)
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/58475/comment/55d80574_821a45d0
PS20, Line 67: unlikley
> unlikely (typo)
Done
https://review.coreboot.org/c/flashrom/+/58475/comment/a2d76588_764175f1
PS20, Line 74: i -= 10;
> I can't understand this after reading the comment. […]
Oops, the delay should be 100*1000 not 10*1000.
It would probably fine without modifying `i`, it's just so that the total time is always 5 seconds.
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#15).
Change subject: writeprotect, cli_classic: delete old writeprotect code
......................................................................
writeprotect, cli_classic: delete old writeprotect code
Delete writeprotect code that was previously extracted from the cros tree.
This is the first of a series of commits adding writeprotect support.
Following commits incrementally implement writeprotect operations,
culminating in writeprotect support for three example chips: GD25LQ128,
GD25Q32, and GD25Q256.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
BRANCH=none
Change-Id: I67e9b31f86465e5a8f7d3def637198671ee818a8
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M cli_classic.c
M flash.h
M s25f.c
M writeprotect.c
M writeprotect.h
5 files changed, 7 insertions(+), 570 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/74/58474/15
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#21).
Change subject: spi25_statusreg: make register read/write functions generic
......................................................................
spi25_statusreg: make register read/write functions generic
This patch adds new spi_{read,write}_register() functions that take the
source/destination register as an argument. Currently they can only
access SR1, support for other registers will be added in another patch.
Since we're refactoring things, this commit also makes
spi_read_register() return an error code, making it possible to identify
error conditions that spi_read_status_register() concealed.
This also removes the initial 100ms delay between writing a register and
the first attempt to check the chip's status. An initial delay was added
to avoid needing to read the status register multiple times, but that is
unlikely to cause problems on modern flash chips.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
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Change-Id: I0a3951bbf993f2d8d830143b29d3ce16cc6901d7
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M chipdrivers.h
M flash.h
M spi25_statusreg.c
3 files changed, 99 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/75/58475/21
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I'd like you to reexamine a change. Please visit
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Change subject: spi25_statusreg,flashchips: add SR2 read/write support
......................................................................
spi25_statusreg,flashchips: add SR2 read/write support
This patch adds support for reading and writing the second status
register and enables it on a limited set of flash chips.
Chip support for RDSR2/WRSR2/extended WRSR is represented using feature
flags to be consistent with how other SPI capabilities are represented.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
TEST=logged SR2 read/write values during wp commands
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---
M flash.h
M flashchips.c
M spi.h
M spi25_statusreg.c
4 files changed, 53 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/70/58570/24
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I'd like you to reexamine a change. Please visit
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Change subject: flashchips: add writeprotect bit layout map to chips
......................................................................
flashchips: add writeprotect bit layout map to chips
This patch adds a register bit map `struct reg_bit_info`, with fields
for storing the register, bit index, and writability of each bit that
affects the chip's write protection. This allows writeprotect code to be
independent of the register layout of any specific chip. The new fields
have been filled out for example chips.
The representation is centered around describing how bits can be
accessed and modified, rather than the layout of registers. This is
generally easier to work with in code that needs to access specific bits
and typically requires specifying the locations of fewer bits overall.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
BRANCH=none
Change-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flash.h
M flashchips.c
M writeprotect.h
3 files changed, 74 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/58477/27
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#28).
Change subject: writeprotect.h: add structure to represent chip wp configuration bits
......................................................................
writeprotect.h: add structure to represent chip wp configuration bits
Add `struct wp_bits` for representing values of all WP bits in a chip's
status/config register(s).
It allows most WP code to store and manipulate a chip's configuration
without knowing the exact layout of bits in the chip's status registers.
Supporting other chips may require additional fields to be added to the
structure.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
BRANCH=none
Change-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flash.h
M writeprotect.h
2 files changed, 32 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/58478/28
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