November 2022 - flashrom-gerrit

[S] Change in flashrom[master]: flashchips: Add write protect bits to W25Q64JW...M
by Evan Benn (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Edward O'Callaghan. Evan Benn has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67719 ) Change subject: flashchips: Add write protect bits to W25Q64JW...M ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > please submit oh it failed -- To view, visit https://review.coreboot.org/c/flashrom/+/67719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idf2289b7c90724ececc122d2a05c7cae3af2cf62 Gerrit-Change-Number: 67719 Gerrit-PatchSet: 3 Gerrit-Owner: Evan Benn <evanbenn(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Tue, 08 Nov 2022 23:35:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Evan Benn <evanbenn(a)google.com> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashchips: Add write protect bits to W25Q64JW...M
by Evan Benn (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Edward O'Callaghan, Evan Benn. Evan Benn has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67719 ) Change subject: flashchips: Add write protect bits to W25Q64JW...M ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: please submit -- To view, visit https://review.coreboot.org/c/flashrom/+/67719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idf2289b7c90724ececc122d2a05c7cae3af2cf62 Gerrit-Change-Number: 67719 Gerrit-PatchSet: 3 Gerrit-Owner: Evan Benn <evanbenn(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Evan Benn <evanbenn(a)google.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 23:35:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in flashrom[master]: tests: Add prefix to io_mock functions not to clash with macros
by Anastasia Klimchuk (Code Review) 08 Nov '22

08 Nov '22

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/68433 ) Change subject: tests: Add prefix to io_mock functions not to clash with macros ...................................................................... tests: Add prefix to io_mock functions not to clash with macros Flashrom I/O mock functions need to be renamed so that they do not have name clash with standard I/O, because the latter are allowed to be macros. Adding a prefix to flashrom mock functions avoids them being accidentally expanded. Standard I/O functions are expanded and flashrom mocks stay as they are. BUG=b:237606255 TEST=ninja test 1) gcc 12.2.0 on Debian 2) clang 15.0 on Chromium OS Ticket: https://ticket.coreboot.org/issues/411 Change-Id: I7998a8fb1b9e65621e12adbfab5460a245d5606b Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68433 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M tests/chip.c M tests/io_mock.c M tests/io_mock.h M tests/linux_mtd.c M tests/linux_spi.c M tests/parade_lspcon.c M tests/realtek_mst_i2c_spi.c M tests/tests.c 8 files changed, 68 insertions(+), 43 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/tests/chip.c b/tests/chip.c index 79d0c87..8f4771a 100644 --- a/tests/chip.c +++ b/tests/chip.c @@ -434,7 +434,7 @@ .paths = { NULL }, }; const struct io_mock verify_chip_io = { - .fread = verify_chip_fread, + .iom_fread = verify_chip_fread, .fallback_open_state = &data, }; @@ -471,7 +471,7 @@ .paths = { NULL }, }; const struct io_mock verify_chip_io = { - .fread = verify_chip_fread, + .iom_fread = verify_chip_fread, .fallback_open_state = &data, }; diff --git a/tests/io_mock.c b/tests/io_mock.c index 9f86fcd..c04e9c5 100644 --- a/tests/io_mock.c +++ b/tests/io_mock.c @@ -22,7 +22,7 @@ void io_mock_register(const struct io_mock *io) { /* A test can either register its own mock open function or fallback_open_state. */ - assert_true(io == NULL || io->open == NULL || io->fallback_open_state == NULL); + assert_true(io == NULL || io->iom_open == NULL || io->fallback_open_state == NULL); current_io = io; } diff --git a/tests/io_mock.h b/tests/io_mock.h index 9e92a9d..644da74 100644 --- a/tests/io_mock.h +++ b/tests/io_mock.h @@ -101,17 +101,17 @@ void (*libusb_free_config_descriptor)(void *state, struct libusb_config_descriptor *); /* POSIX File I/O */ - int (*open)(void *state, const char *pathname, int flags); - int (*ioctl)(void *state, int fd, unsigned long request, va_list args); - int (*read)(void *state, int fd, void *buf, size_t sz); - int (*write)(void *state, int fd, const void *buf, size_t sz); + int (*iom_open)(void *state, const char *pathname, int flags); + int (*iom_ioctl)(void *state, int fd, unsigned long request, va_list args); + int (*iom_read)(void *state, int fd, void *buf, size_t sz); + int (*iom_write)(void *state, int fd, const void *buf, size_t sz); /* Standard I/O */ - FILE* (*fopen)(void *state, const char *pathname, const char *mode); - char* (*fgets)(void *state, char *buf, int len, FILE *fp); - size_t (*fread)(void *state, void *buf, size_t size, size_t len, FILE *fp); - int (*fprintf)(void *state, FILE *fp, const char *fmt, va_list args); - int (*fclose)(void *state, FILE *fp); + FILE* (*iom_fopen)(void *state, const char *pathname, const char *mode); + char* (*iom_fgets)(void *state, char *buf, int len, FILE *fp); + size_t (*iom_fread)(void *state, void *buf, size_t size, size_t len, FILE *fp); + int (*iom_fprintf)(void *state, FILE *fp, const char *fmt, va_list args); + int (*iom_fclose)(void *state, FILE *fp); /* * An alternative to custom open mock. A test can either register its diff --git a/tests/linux_mtd.c b/tests/linux_mtd.c index 10ccb5e..3aaa5ab 100644 --- a/tests/linux_mtd.c +++ b/tests/linux_mtd.c @@ -81,9 +81,9 @@ }; const struct io_mock linux_mtd_io = { .state = &linux_mtd_io_state, - .fopen = linux_mtd_fopen, - .fread = linux_mtd_fread, - .fclose = linux_mtd_fclose, + .iom_fopen = linux_mtd_fopen, + .iom_fread = linux_mtd_fread, + .iom_fclose = linux_mtd_fclose, .fallback_open_state = &linux_mtd_fallback_open_state, }; diff --git a/tests/linux_spi.c b/tests/linux_spi.c index 2e3dc95..1009634 100644 --- a/tests/linux_spi.c +++ b/tests/linux_spi.c @@ -60,8 +60,8 @@ .flags = { O_RDWR }, }; const struct io_mock linux_spi_io = { - .fgets = linux_spi_fgets, - .ioctl = linux_spi_ioctl, + .iom_fgets = linux_spi_fgets, + .iom_ioctl = linux_spi_ioctl, .fallback_open_state = &linux_spi_fallback_open_state, }; diff --git a/tests/parade_lspcon.c b/tests/parade_lspcon.c index 9d7bd23..980e128 100644 --- a/tests/parade_lspcon.c +++ b/tests/parade_lspcon.c @@ -108,9 +108,9 @@ }; const struct io_mock parade_lspcon_io = { .state = &parade_lspcon_io_state, - .ioctl = parade_lspcon_ioctl, - .read = parade_lspcon_read, - .write = parade_lspcon_write, + .iom_ioctl = parade_lspcon_ioctl, + .iom_read = parade_lspcon_read, + .iom_write = parade_lspcon_write, .fallback_open_state = &parade_lspcon_fallback_open_state, }; diff --git a/tests/realtek_mst_i2c_spi.c b/tests/realtek_mst_i2c_spi.c index 0526124..753f06b 100644 --- a/tests/realtek_mst_i2c_spi.c +++ b/tests/realtek_mst_i2c_spi.c @@ -50,9 +50,9 @@ .flags = { O_RDWR }, }; const struct io_mock realtek_mst_io = { - .ioctl = realtek_mst_ioctl, - .read = realtek_mst_read, - .write = realtek_mst_write, + .iom_ioctl = realtek_mst_ioctl, + .iom_read = realtek_mst_read, + .iom_write = realtek_mst_write, .fallback_open_state = &realtek_mst_fallback_open_state, }; diff --git a/tests/tests.c b/tests/tests.c index 77cb1ef..ea416b8 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -77,8 +77,8 @@ static int mock_open(const char *pathname, int flags) { - if (get_io() && get_io()->open) - return get_io()->open(get_io()->state, pathname, flags); + if (get_io() && get_io()->iom_open) + return get_io()->iom_open(get_io()->state, pathname, flags); if (get_io() && get_io()->fallback_open_state) { struct io_mock_fallback_open_state *io_state; @@ -117,11 +117,11 @@ int __wrap_ioctl(int fd, unsigned long int request, ...) { LOG_ME; - if (get_io() && get_io()->ioctl) { + if (get_io() && get_io()->iom_ioctl) { va_list args; int out; va_start(args, request); - out = get_io()->ioctl(get_io()->state, fd, request, args); + out = get_io()->iom_ioctl(get_io()->state, fd, request, args); va_end(args); return out; } @@ -131,32 +131,32 @@ int __wrap_write(int fd, const void *buf, size_t sz) { LOG_ME; - if (get_io() && get_io()->write) - return get_io()->write(get_io()->state, fd, buf, sz); + if (get_io() && get_io()->iom_write) + return get_io()->iom_write(get_io()->state, fd, buf, sz); return sz; } int __wrap_read(int fd, void *buf, size_t sz) { LOG_ME; - if (get_io() && get_io()->read) - return get_io()->read(get_io()->state, fd, buf, sz); + if (get_io() && get_io()->iom_read) + return get_io()->iom_read(get_io()->state, fd, buf, sz); return sz; } FILE *__wrap_fopen(const char *pathname, const char *mode) { LOG_ME; - if (get_io() && get_io()->fopen) - return get_io()->fopen(get_io()->state, pathname, mode); + if (get_io() && get_io()->iom_fopen) + return get_io()->iom_fopen(get_io()->state, pathname, mode); return not_null(); } FILE *__wrap_fopen64(const char *pathname, const char *mode) { LOG_ME; - if (get_io() && get_io()->fopen) - return get_io()->fopen(get_io()->state, pathname, mode); + if (get_io() && get_io()->iom_fopen) + return get_io()->iom_fopen(get_io()->state, pathname, mode); return not_null(); } @@ -217,16 +217,16 @@ char *__wrap_fgets(char *buf, int len, FILE *fp) { LOG_ME; - if (get_io() && get_io()->fgets) - return get_io()->fgets(get_io()->state, buf, len, fp); + if (get_io() && get_io()->iom_fgets) + return get_io()->iom_fgets(get_io()->state, buf, len, fp); return NULL; } size_t __wrap_fread(void *ptr, size_t size, size_t nmemb, FILE *fp) { LOG_ME; - if (get_io() && get_io()->fread) - return get_io()->fread(get_io()->state, ptr, size, nmemb, fp); + if (get_io() && get_io()->iom_fread) + return get_io()->iom_fread(get_io()->state, ptr, size, nmemb, fp); return nmemb; } @@ -263,11 +263,11 @@ int __wrap_fprintf(FILE *fp, const char *fmt, ...) { LOG_ME; - if (get_io() && get_io()->fprintf) { + if (get_io() && get_io()->iom_fprintf) { va_list args; int out; va_start(args, fmt); - out = get_io()->fprintf(get_io()->state, fp, fmt, args); + out = get_io()->iom_fprintf(get_io()->state, fp, fmt, args); va_end(args); return out; } @@ -277,8 +277,8 @@ int __wrap_fclose(FILE *fp) { LOG_ME; - if (get_io() && get_io()->fclose) - return get_io()->fclose(get_io()->state, fp); + if (get_io() && get_io()->iom_fclose) + return get_io()->iom_fclose(get_io()->state, fp); return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/68433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7998a8fb1b9e65621e12adbfab5460a245d5606b Gerrit-Change-Number: 68433 Gerrit-PatchSet: 8 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in flashrom[master]: spi25_statusreg: support reading/writing configuration register
by Sergii Dmytruk (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/66211 ) Change subject: spi25_statusreg: support reading/writing configuration register ...................................................................... Patch Set 8: (1 comment) Patchset: PS2: Rebased everything due to `flashchips.c` changes and moved aliasing to CB:69399 restoring an older patchset here. > it seemed to make the code simpler I guess it depends on how you look at it. Aliasing does make SPI code changes smaller and keeps fewer entities to know about, but I think Edward's argument is that not using aliasing makes understanding and modifying code easier, because it has more obvious structure. -- To view, visit https://review.coreboot.org/c/flashrom/+/66211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I45f9afcc31f1928ef6263a749596380082963de4 Gerrit-Change-Number: 66211 Gerrit-PatchSet: 8 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Tue, 08 Nov 2022 17:46:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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[M] Change in flashrom[master]: spi25_statusreg: make "configuration registers" an alias to SRs
by Sergii Dmytruk (Code Review) 08 Nov '22

08 Nov '22

Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69399 ) Change subject: spi25_statusreg: make "configuration registers" an alias to SRs ...................................................................... spi25_statusreg: make "configuration registers" an alias to SRs Sometimes it's only a matter of naming and these behave exactly like SR2/SR3 (Spansion S25FL256L and S25FL128L), so they can be treated as a variation on status registers. Change-Id: I27e89626037dcb0ed078029efe1e919b1f3e88fe Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M flashchips.c M include/flash.h M spi25_statusreg.c 3 files changed, 51 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/99/69399/1 diff --git a/flashchips.c b/flashchips.c index 69e524f..3ba07a3 100644 --- a/flashchips.c +++ b/flashchips.c @@ -9365,7 +9365,7 @@ { .srp = {STATUS1, 7, RW}, .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, - .tb = {CONFIG, 3, OTP}, + .tb = {CONFIG1, 3, OTP}, .wps = {SECURITY, 7, OTP}, /* This bit is set by WPSEL command */ }, .decode_range = DECODE_RANGE_SPI25, @@ -9413,7 +9413,7 @@ { .srp = {STATUS1, 7, RW}, .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, - .tb = {CONFIG, 3, OTP}, + .tb = {CONFIG1, 3, OTP}, }, .decode_range = DECODE_RANGE_SPI25, }, @@ -16467,6 +16467,13 @@ .total_size = 16384, .page_size = 256, /* 4 x 256B Security Region (OTP) */ + /* + * Note: Map of registers names: + * STATUS1 ... Status Register 1 + * ... Status Register 2 (read-only) + * STATUS2/CONFIG1 ... Configuration Register 1 + * STATUS3/CONFIG2 ... Configuration Register 2 + */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_WRSR_EXT3 | FEATURE_OTP, .tested = TEST_UNTESTED, .probe = PROBE_SPI_RDID, @@ -16497,20 +16504,13 @@ .voltage = {2700, 3600}, .reg_bits = { - /* - * Note: This chip has a read-only Status Register 2 that is not - * counted here. Registers are mapped as follows: - * STATUS1 ... Status Register 1 - * STATUS2 ... Configuration Register 1 - * STATUS3 ... Configuration Register 2 - */ .srp = {STATUS1, 7, RW}, - .srl = {STATUS2, 0, RW}, + .srl = {CONFIG1, 0, RW}, .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, .tb = {STATUS1, 5, RW}, .sec = {STATUS1, 6, RW}, - .cmp = {STATUS2, 6, RW}, - .wps = {STATUS3, 2, RW}, + .cmp = {CONFIG1, 6, RW}, + .wps = {CONFIG2, 2, RW}, }, .decode_range = DECODE_RANGE_SPI25, }, @@ -16951,6 +16951,13 @@ .total_size = 32768, .page_size = 256, /* 4 x 256B Security Region (OTP) */ + /* + * Note: Map of registers names: + * STATUS1 ... Status Register 1 + * ... Status Register 2 (read-only) + * STATUS2/CONFIG1 ... Configuration Register 1 + * STATUS3/CONFIG2 ... Configuration Register 2 + */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_WRSR_EXT3 | FEATURE_OTP | FEATURE_4BA_ENTER | FEATURE_4BA_NATIVE, .tested = TEST_UNTESTED, @@ -16991,19 +16998,12 @@ .voltage = {2700, 3600}, .reg_bits = { - /* - * Note: This chip has a read-only Status Register 2 that is not - * counted here. Registers are mapped as follows: - * STATUS1 ... Status Register 1 - * STATUS2 ... Configuration Register 1 - * STATUS3 ... Configuration Register 2 - */ .srp = {STATUS1, 7, RW}, - .srl = {STATUS2, 0, RW}, + .srl = {CONFIG1, 0, RW}, .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, .tb = {STATUS1, 6, RW}, - .cmp = {STATUS2, 6, RW}, - .wps = {STATUS3, 2, RW}, + .cmp = {CONFIG1, 6, RW}, + .wps = {CONFIG2, 2, RW}, }, .decode_range = DECODE_RANGE_SPI25, }, diff --git a/include/flash.h b/include/flash.h index d18e25e..0a1fe02 100644 --- a/include/flash.h +++ b/include/flash.h @@ -161,8 +161,11 @@ */ #define FEATURE_SCUR (1 << 24) -/* Whether chip has configuration register (RDCR/WRSR_EXT2 commands) */ -#define FEATURE_CFGR (1 << 25) +/* + * Some chips read SR2 with 0x15 opcode and call it "configuration register". + * Writes are done as for FEATURE_WRSR_EXT2. + */ +#define FEATURE_RDSR2_0x15 ((1 << 25) | FEATURE_WRSR_EXT2) #define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff) @@ -192,13 +195,17 @@ #define flashctx flashrom_flashctx /* TODO: Agree on a name and convert all occurrences. */ typedef int (erasefunc_t)(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +/* For chips that call SR2 "Configuration Register 1" */ +#define CONFIG1 STATUS2 +/* For chips that call SR3 "Configuration Register 2" */ +#define CONFIG2 STATUS3 + enum flash_reg { INVALID_REG = 0, STATUS1, STATUS2, STATUS3, SECURITY, - CONFIG, MAX_REGISTERS }; diff --git a/spi25_statusreg.c b/spi25_statusreg.c index b178b2e..d90ff26 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -107,23 +107,6 @@ */ msg_cerr("Cannot write SECURITY: unsupported by design\n"); return 1; - case CONFIG: - /* - * This one is read via a separate command, but written as if it's SR2 - * in FEATURE_WRSR_EXT2 case of WRSR command. - */ - if (feature_bits & FEATURE_CFGR) { - write_cmd[0] = JEDEC_WRSR; - if (spi_read_register(flash, STATUS1, &write_cmd[1])) { - msg_cerr("Writing CONFIG failed: failed to read SR1 for writeback.\n"); - return 1; - } - write_cmd[2] = value; - write_cmd_len = 3; - break; - } - msg_cerr("Cannot write CONFIG: unsupported by chip\n"); - return 1; default: msg_cerr("Cannot write register: unknown register\n"); return 1; @@ -205,6 +188,11 @@ read_cmd = JEDEC_RDSR; break; case STATUS2: + /* This check must go first because FEATURE_RDSR2_0x15 includes FEATURE_WRSR_EXT2. */ + if ((feature_bits & FEATURE_RDSR2_0x15) == FEATURE_RDSR2_0x15) { + read_cmd = 0x15; + break; + } if (feature_bits & (FEATURE_WRSR_EXT2 | FEATURE_WRSR2)) { read_cmd = JEDEC_RDSR2; break; @@ -226,13 +214,6 @@ } msg_cerr("Cannot read SECURITY: unsupported by chip\n"); return 1; - case CONFIG: - if (feature_bits & FEATURE_CFGR) { - read_cmd = JEDEC_RDCR; - break; - } - msg_cerr("Cannot read CONFIG: unsupported by chip\n"); - return 1; default: msg_cerr("Cannot read register: unknown register\n"); return 1; -- To view, visit https://review.coreboot.org/c/flashrom/+/69399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I27e89626037dcb0ed078029efe1e919b1f3e88fe Gerrit-Change-Number: 69399 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newchange

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[M] Change in flashrom[master]: flashchips.c: enable WP for 7 entries of MX chips
by Sergii Dmytruk (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Nico Huber, Angel Pons, Nikolai Artemiev. Hello build bot (Jenkins), Nico Huber, Maciej Pijanowski, Angel Pons, Nikolai Artemiev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/66216 to look at the new patch set (#9). Change subject: flashchips.c: enable WP for 7 entries of MX chips ...................................................................... flashchips.c: enable WP for 7 entries of MX chips These weren't split: * MX25L3206E/MX25L3208E Tested: https://github.com/Dasharo/flashrom/pull/8 * MX25L6405 * MX25L6405D * MX25L6406E/MX25L6408E Tested: https://github.com/Dasharo/flashrom/pull/8 MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E/MX25L6473F was split into: * MX25L6436E/MX25L6445E/MX25L6465E - security register - WPS - tested: https://github.com/Dasharo/flashrom/pull/8 * MX25L6473E - security register - OTP TB bit in CONFIG/STATUS2 (0x15 opcode) - WPS * MX25L6473F - NO security register - OTP TB bit in CONFIG/STATUS2 (0x15 opcode) - NO WPS Change-Id: Ib3db9d39ffacd3e9e44de92c6cfb6c3ecc8615bd Tested-by: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M flashchips.c 1 file changed, 166 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/16/66216/9 -- To view, visit https://review.coreboot.org/c/flashrom/+/66216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib3db9d39ffacd3e9e44de92c6cfb6c3ecc8615bd Gerrit-Change-Number: 66216 Gerrit-PatchSet: 9 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[master]: flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}E
by Sergii Dmytruk (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Nico Huber, Angel Pons, Nikolai Artemiev. Hello build bot (Jenkins), Nico Huber, Angel Pons, Nikolai Artemiev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/66215 to look at the new patch set (#9). Change subject: flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}E ...................................................................... flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}E Change-Id: Ib0f3cb9516cea7bb678842a358a82099221e1ed9 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M flashchips.c 1 file changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/15/66215/9 -- To view, visit https://review.coreboot.org/c/flashrom/+/66215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib0f3cb9516cea7bb678842a358a82099221e1ed9 Gerrit-Change-Number: 66215 Gerrit-PatchSet: 9 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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[L] Change in flashrom[master]: flashchips.c: enable WP for W25Q32.V, W25Q32.W and W25Q32JW...M
by Sergii Dmytruk (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Nico Huber, Angel Pons, Nikolai Artemiev. Hello build bot (Jenkins), Nico Huber, Angel Pons, Nikolai Artemiev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/66214 to look at the new patch set (#9). Change subject: flashchips.c: enable WP for W25Q32.V, W25Q32.W and W25Q32JW...M ...................................................................... flashchips.c: enable WP for W25Q32.V, W25Q32.W and W25Q32JW...M Split chips: * W25Q32.V -> W25Q32BV/W25Q32CV/W25Q32DV, W25Q32FV and W25Q32JV * W25Q32.W -> W25Q32BW/W25Q32CW/W25Q32DW, W25Q32FW and W25Q32JW...Q Change-Id: Id259c27dfa6c681bbadc73b3bd7559ad6a5865f4 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M flashchips.c 1 file changed, 262 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/14/66214/9 -- To view, visit https://review.coreboot.org/c/flashrom/+/66214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id259c27dfa6c681bbadc73b3bd7559ad6a5865f4 Gerrit-Change-Number: 66214 Gerrit-PatchSet: 9 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[master]: flashchips.c: enable WP for EN25QH32 and EN25QH64
by Sergii Dmytruk (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Nico Huber, Angel Pons, Nikolai Artemiev. Hello build bot (Jenkins), Nico Huber, Angel Pons, Nikolai Artemiev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/66213 to look at the new patch set (#9). Change subject: flashchips.c: enable WP for EN25QH32 and EN25QH64 ...................................................................... flashchips.c: enable WP for EN25QH32 and EN25QH64 Split chips: * EN25QH32 -> EN25QH32 and EN25QH32B * EN25QH64 -> EN25QH64 and EN25QH64A Unlike older revisions both newly added EN25QH32B and EN25QH64A support half block (32KiB) erase operation via 0x52 opcode. Change-Id: I759f0119346235ce0bddc78cde9c461495990c25 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M flashchips.c 1 file changed, 113 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/13/66213/9 -- To view, visit https://review.coreboot.org/c/flashrom/+/66213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I759f0119346235ce0bddc78cde9c461495990c25 Gerrit-Change-Number: 66213 Gerrit-PatchSet: 9 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[master]: writeprotect_ranges.c: add more range functions
by Sergii Dmytruk (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Nico Huber, Maciej Pijanowski, Angel Pons, Nikolai Artemiev, Sergii Dmytruk. Hello build bot (Jenkins), Nico Huber, Angel Pons, Nikolai Artemiev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/66212 to look at the new patch set (#9). Change subject: writeprotect_ranges.c: add more range functions ...................................................................... writeprotect_ranges.c: add more range functions Not all chips follow the same pattern. There are differences in how CMP bit is treated or in block size used. Change-Id: Ied7b27be2ee2426af8f473432e2b01a290de2365 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M include/chipdrivers.h M include/flash.h M writeprotect.c M writeprotect_ranges.c 4 files changed, 86 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/12/66212/9 -- To view, visit https://review.coreboot.org/c/flashrom/+/66212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ied7b27be2ee2426af8f473432e2b01a290de2365 Gerrit-Change-Number: 66212 Gerrit-PatchSet: 9 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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