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Evan Benn has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67719 )
Change subject: flashchips: Add write protect bits to W25Q64JW...M
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Please take a look
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/66212 )
Change subject: writeprotect_ranges.c: add more range functions
......................................................................
Patch Set 6:
(2 comments)
Patchset:
PS3:
> There's a .tested member in the struct for flash chips. I guess it could be extended to also indicate whether WP support has been tested.
Yes that's what https://ticket.coreboot.org/issues/377 is about, not sure if you clicked ;) Good that we agree.
Maciej, Sergii, I have a straight question, would you implement support for WP in `flashchip.tested` ? That would be ideal, and so much appreciated!
File writeprotect_ranges.c:
https://review.coreboot.org/c/flashrom/+/66212/comment/ab10caa5_c65ae034
PS2, Line 20: _generic
> Sure, but I used the suffix for consistency with other similar functions: […]
Okay makes sense.
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Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67695 )
Change subject: drivers: Move (un)map_flash_region to par/spi/opaque_master
......................................................................
Patch Set 8:
(1 comment)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/67695/comment/343fcc62_9bbbe6e8
PS2, Line 1865: &mapper_phys
> Yep thank you all, I totally agree! I'm still getting the hang of the Gerrit workflow and what works […]
Alrighty this is a lot more understandable now! I split this up into several patches and rebased onto CB:67404. The second patch (ICH hwseq) is the one I really need, the later ones do some additional cleanup.
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Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/68093 )
Change subject: serprog.c: Replace custom mapper with max_rom_decode
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
I don't have the hardware to test this on, but I was asked to give this a try while refactoring CB:67695.
It turned out we need the SPI mappers anyway (for now), so this wasn't critical to that patch after all. I think it is still a decent improvement though.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67695 )
Change subject: drivers: Move (un)map_flash_region to par/spi/opaque_master
......................................................................
Patch Set 8:
(1 comment)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/67695/comment/36e2ecb4_a70012ef
PS2, Line 1865: &mapper_phys
> Yep thank you all, I totally agree! I'm still getting the hang of the Gerrit workflow and what works best for review but I really appreciate all the help!
It is our duty to introduce newcomers to the Gerrit workflows and mechanics, as we all were newcomers at some point. And given that we're going to run into each other rather frequently, we might as well work towards making the review process as pleasant as possible for everyone involved.
> I will rebase this on those patches and split it up. I think this will require temporarily adding a mapper to the opaque bus master that I then remove in a later patch, but that should be straightforward.
Sounds good. It can't be worse than that one temporary macro with 24 parameters that we devised to enable refactoring of RAM init code in a reviewable way. RAM init code is full of magic numbers, and extremely hard to test. By leveraging reproducible builds to adapt the code, most of the non-reproducible refactoring got reduced to CB:40980 which replaces the implementation without changing the magic numbers. 😄
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Change subject: ichspi: Do not mmap for hwseq
......................................................................
Abandoned
Superseded by CB:68090
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Jonathon Hall has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/68093 )
Change subject: serprog.c: Replace custom mapper with max_rom_decode
......................................................................
serprog.c: Replace custom mapper with max_rom_decode
serprog's custom mapper is actually a hack to check for a maximum chip
size. It would not have actually failed a read/write/erase attempt
since mappers are allowed to return NULL, it only printed a warning.
We can't remove custom mappers from SPI masters yet since some still
use it, but many of those are not actually needed or could be reworked,
so this is one step closer to removing SPI custom mappers.
Change-Id: If8b313708a52813b9354cbf45cb91cdd1fe36b13
Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm>
---
M serprog.c
1 file changed, 28 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/68093/1
diff --git a/serprog.c b/serprog.c
index a3a3db3..bdcf697 100644
--- a/serprog.c
+++ b/serprog.c
@@ -438,23 +438,7 @@
return 0;
}
-static void *serprog_map(const char *descr, uintptr_t phys_addr, size_t len)
-{
- /* Serprog transmits 24 bits only and assumes the underlying implementation handles any remaining bits
- * correctly (usually setting them to one either in software (for FWH/LPC) or relying on the fact that
- * the hardware observes a subset of the address bits only). Combined with the standard mapping of
- * flashrom this creates a 16 MB-wide window just below the 4 GB boundary where serprog can operate (as
- * needed for non-SPI chips). Below we make sure that the requested range is within this window. */
- if ((phys_addr & 0xFF000000) == 0xFF000000) {
- return (void*)phys_addr;
- }
- msg_pwarn(MSGHEADER "requested mapping %s is incompatible: 0x%zx bytes at 0x%0*" PRIxPTR ".\n",
- descr, len, PRIxPTR_WIDTH, phys_addr);
- return NULL;
-}
-
static struct spi_master spi_master_serprog = {
- .map_flash_region = serprog_map,
.features = SPI_MASTER_4BA,
.max_data_read = MAX_DATA_READ_UNLIMITED,
.max_data_write = MAX_DATA_WRITE_UNLIMITED,
@@ -569,7 +553,6 @@
}
static const struct par_master par_master_serprog = {
- .map_flash_region = serprog_map,
.chip_readb = serprog_chip_readb,
.chip_readw = fallback_chip_readw,
.chip_readl = fallback_chip_readl,
@@ -928,6 +911,16 @@
sp_streamed_transmit_bytes = 0;
sp_opbuf_usage = 0;
+ /* Serprog transmits 24 bits only and assumes the underlying
+ * implementation handles any remaining bits correctly (usually setting
+ * them to one either in software (for FWH/LPC) or relying on the fact
+ * that the hardware observes a subset of the address bits only). Only
+ * 16MB or smaller chips can be used with serprog. */
+ max_rom_decode.parallel = 16 * MiB;
+ max_rom_decode.lpc = 16 * MiB;
+ max_rom_decode.fwh = 16 * MiB;
+ max_rom_decode.spi = 16 * MiB;
+
if (register_shutdown(serprog_shutdown, NULL))
goto init_err_cleanup_exit;
if (serprog_buses_supported & BUS_SPI)
--
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Jonathon Hall has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/68091 )
Change subject: dummyflasher.c: Remove custom mapper from opaque_master
......................................................................
dummyflasher.c: Remove custom mapper from opaque_master
Dummy doesn't need a custom mapper on opaque_master; the returned
address is not used and the mapper has no side effects.
This is the only remaining opaque master with a custom mapper, so this
permits removing custom mapper support from opaque masters.
Change-Id: I76ae3e0c2e91ecba4fd320941bd1eff038050731
Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm>
---
M dummyflasher.c
1 file changed, 16 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/91/68091/1
diff --git a/dummyflasher.c b/dummyflasher.c
index ad734f0..22f392a 100644
--- a/dummyflasher.c
+++ b/dummyflasher.c
@@ -947,8 +947,6 @@
};
static const struct opaque_master opaque_master_dummyflasher = {
- .map_flash_region = dummy_map,
- .unmap_flash_region = dummy_unmap,
.probe = probe_variable_size,
.read = dummy_opaque_read,
.write = dummy_opaque_write,
--
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Jonathon Hall has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/68090 )
Change subject: ichspi: Do not attempt to map physical memory for hwseq
......................................................................
ichspi: Do not attempt to map physical memory for hwseq
ICH hwseq does not need to actually mmap flash, and this fails for
flash chips >16 MB, since only the top 16 MB is mapped into the address
space.
Test: Read and write flash on ICH hwseq with 32 MB flash chip.
Change-Id: Ie698071c3181e988f10b750b0e50c9700efaa1a3
Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm>
---
M ichspi.c
1 file changed, 16 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/90/68090/1
diff --git a/ichspi.c b/ichspi.c
index 7e7967e..aefbe2f 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1794,8 +1794,6 @@
};
static const struct opaque_master opaque_master_ich_hwseq = {
- .map_flash_region = physmap,
- .unmap_flash_region = physunmap,
.max_data_read = 64,
.max_data_write = 64,
.probe = ich_hwseq_probe,
--
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