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Hello Felix Singer, build bot (Jenkins), Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: flashrom.8.tmpl: document mediatek_i2c_spi programmer
......................................................................
flashrom.8.tmpl: document mediatek_i2c_spi programmer
This adds a manpage section describing the mediatek_i2c_spi programmer,
including some discussion of devices that are supported as well as which
systems use them.
Signed-off-by: Peter Marheine <pmarheine(a)chromium.org>
Change-Id: Ia63df470170fbadcabadcdad8e5acc0cde3a274b
---
M flashrom.8.tmpl
1 file changed, 38 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/25/67825/4
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Gerrit-Change-Number: 67825
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/66754 )
Change subject: writeprotect.c: skip unnecessary writes
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/66754/comment/984f48f2_d5d48b3e
PS1, Line 7: writeprotect
> nit: `writeprotect. […]
Done
File writeprotect.c:
https://review.coreboot.org/c/flashrom/+/66754/comment/d2bf76de_7ee2db2f
PS1, Line 158: old
> `actual`
Done
https://review.coreboot.org/c/flashrom/+/66754/comment/00f99442_5a39d96b
PS1, Line 159: new
> `expected`
Done
https://review.coreboot.org/c/flashrom/+/66754/comment/df275601_ea3c92ff
PS1, Line 160: old == new
> You may reuse the result from line159 one line163, […]
Done
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59709 )
Change subject: spi25_statusreg.c: support reading/writing security register
......................................................................
Patch Set 29:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/59709/comment/46c9c627_71b5602e
PS28, Line 9: Not to be confused with "secure registers" of OTP.
> include this remark in the comment above the `FEATURE_SCUR` define?
Done
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/59709/comment/26d64748_a3250614
PS28, Line 104: use special commands for modifying it
> IIRC, this path shouldn't be taken. So it's more a message for developers […]
Changed to:
```
/*
* Security register doesn't have a normal write operation. Instead,
* there are separate commands that set individual OTP bits.
*/
msg_cerr("Cannot write SECURITY: unsupported by design\n");
```
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/66216 )
Change subject: flashchips.c: enable WP for to 7 entries of MX chips
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/66216/comment/9cdac1dd_035fc6ec
PS6, Line 15: MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E/MX25L6473F was split into:
> Do you know if SFDP can be used to tell apart these chips?
All 5 of them seem to have different SFDP (either JEDEC or vendor part), so it should be doable at least by comparing against expected values (I just haven't seen flashrom code using SFDP for identification). Features like `OTP TB bit in CONFIG1/STATUS2 (0x15 opcode)` might not be derivable from SFDP.
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Nikolai Artemiev, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#29).
Change subject: spi25_statusreg.c: support reading/writing security register
......................................................................
spi25_statusreg.c: support reading/writing security register
Not to be confused with "secure registers" of OTP.
Security register is a dedicated status register for security-related
bits. You don't write its value directly, issuing special write commands
with no data set separate OTP bits to 1 automatically (WRSCUR, WPSEL
commands). No WREN is necessary, but at least some datasheets indicate
BUSY state after those write commands.
Unlike cases where OTP bit is part of SR and can only be written while
in OTP mode, security register can only be written outside of the mode.
The register is found in at least these chips by Macronix:
* MX25L6436E
* MX25L6445E
* MX25L6465E
* MX25L6473E
Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M include/flash.h
M include/spi.h
M spi25_statusreg.c
3 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/59709/29
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I'd like you to reexamine a change. Please visit
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Change subject: writeprotect.c: refuse to work with chip if OTP WPS == 1
......................................................................
writeprotect.c: refuse to work with chip if OTP WPS == 1
Perform the check right in read_wp_bits() as it's used by various WP
operations and also because its results won't make sense if WPS bit is
on and can't be changed.
Change-Id: I143186066a1d3af89809b7135886cb8b0d038085
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M cli_classic.c
M include/libflashrom.h
M writeprotect.c
3 files changed, 37 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/36/66836/2
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: writeprotect.c: skip unnecessary writes
......................................................................
writeprotect.c: skip unnecessary writes
* Don't write register because of RO and OTP bits.
* Skip the write of RW bits if register state wouldn't change by it.
Change-Id: I81d2d3fc0a103ee00ced78838d77fe33a9d3056a
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M writeprotect.c
1 file changed, 41 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/66754/2
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/68180 )
Change subject: flashchips.c: mark WP of 7 entries as tested
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/68180/comment/90e6454d_0c833011
PS1, Line 10: a850fd0aa8054a1125a9231fa3317428f15900f4
> nit: Add `commit ` before the hashes so that Gerrit makes them links: […]
Done
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