October 2022 - flashrom-gerrit

[M] Change in flashrom[1.2.x]: ichspi: Unify timeouts across all SPI operations to 30s
by Felix Singer (Code Review) 20 Oct '22

20 Oct '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/68597 ) Change subject: ichspi: Unify timeouts across all SPI operations to 30s ...................................................................... ichspi: Unify timeouts across all SPI operations to 30s Note: This patch was backported from the master branch and it was modified so that it can be applied on the 1.2.x branch. `ich_hwseq_wait_for_cycle_complete()` drops taking `timeout` as argument in favor of a fixed timeout of `30 seconds` for any given SPI operation as recommended by the SPI programming guide. Document: Alder Lake-P Client Platform SPI Programming Guide Rev 1.30 (supporting document for multi-master accessing the SPI Flash device.) Refer to below section to understand the problem in more detail and SPI operation timeout recommendation from Intel in multi-master scenarios. On Intel Chipsets that support multi-mastering access of the SPI flash may run into a timeout failure when the operation initiated from a single master just follows the SPI operational timeout recommendation as per the vendor datasheet (example: winbond spiflash W25Q256JV-DTR specification, table 9.7). In the multi-master SPI accessing scenario using hardware sequencing operation, it's impossible to know the actual status of the SPI bus prior to individual master starting the operation (SPI Cycle In Progress a.k.a SCIP bit represents the status of SPI operation on individual master). Thus, any SPI operation triggered in multi-master environment might need to account a worst case scenario where the most time consuming operation might have occupied the SPI bus from a master and an operation initiated by another master just timed out. Here is the timeout calculation for any hardware sequencing operation: Worst Case Operational Delay = (Maximum Time consumed by a SPI operation + Any marginal adjustment) Timeout Recommendation for Hardware Sequencing Operation = ((Worst Case Operational Delay) * (#No. Of SPI Master - 1) + Current Operational latency) Assume, on Intel platform with 6 SPI master like, Host CPU, CSE, EC, GbE and other reserved etc, hence, the Timeout Calculation for SPI erase Operation would look like as below: Maximum Time consumed by a SPI Operation = 5 seconds Worst Case Operational Delay = 5 seconds Timeout Recommendation for Hardware Seq Operation = 5 seconds * (6 - 1) + 5 seconds = 30 seconds BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Original-Signed-off-by: Subrata Banik <subratabanik(a)google.com> Original-Change-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/62867 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Original-Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Change-Id: I588b02da78fe26327d44bee455afb8272b34ed16 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M ichspi.c 1 file changed, 85 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/97/68597/1 diff --git a/ichspi.c b/ichspi.c index 12ee126..725bfb3 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1282,20 +1282,24 @@ Resets all error flags in HSFS. Returns 0 if the cycle completes successfully without errors within timeout us, 1 on errors. */ -static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, - unsigned int len) +static int ich_hwseq_wait_for_cycle_complete(unsigned int len) { + /* + * The SPI bus may be busy due to performing operations from other masters, hence + * introduce the long timeout of 30s to cover the worst case scenarios as well. + */ + unsigned int timeout_us = 30 * 1000 * 1000; uint16_t hsfs; uint32_t addr; - timeout /= 8; /* scale timeout duration to counter */ + timeout_us /= 8; /* scale timeout duration to counter */ while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & (HSFS_FDONE | HSFS_FCERR)) == 0) && - --timeout) { + --timeout_us) { programmer_delay(8); } REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); - if (!timeout) { + if (!timeout_us) { addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask; msg_perr("Timeout error between offset 0x%08x and " "0x%08x (= 0x%08x + %d)!\n", @@ -1378,7 +1382,6 @@ { uint32_t erase_block; uint16_t hsfc; - uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ erase_block = ich_hwseq_get_erase_block_size(addr); if (len != erase_block) { @@ -1418,7 +1421,7 @@ prettyprint_ich9_reg_hsfc(hsfc); REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + if (ich_hwseq_wait_for_cycle_complete(len)) return -1; return 0; } @@ -1427,7 +1430,6 @@ unsigned int addr, unsigned int len) { uint16_t hsfc; - uint16_t timeout = 100 * 60; uint8_t block_len; if (addr + len > flash->chip->total_size * 1024) { @@ -1455,7 +1457,7 @@ hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + if (ich_hwseq_wait_for_cycle_complete(block_len)) return 1; ich_read_data(buf, block_len, ICH9_REG_FDATA0); addr += block_len; @@ -1468,7 +1470,6 @@ static int ich_hwseq_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) { uint16_t hsfc; - uint16_t timeout = 100 * 60; uint8_t block_len; if (addr + len > flash->chip->total_size * 1024) { @@ -1497,7 +1498,7 @@ hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + if (ich_hwseq_wait_for_cycle_complete(block_len)) return -1; addr += block_len; buf += block_len; -- To view, visit https://review.coreboot.org/c/flashrom/+/68597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.2.x Gerrit-Change-Id: I588b02da78fe26327d44bee455afb8272b34ed16 Gerrit-Change-Number: 68597 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in flashrom[master]: chipset_enable.c: Mark Intel C246 as DEP
by Felix Singer (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Angel Pons. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/68594 ) Change subject: chipset_enable.c: Mark Intel C246 as DEP ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/68594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I07d6c4a60e468c61eba836db91e1335f4a762048 Gerrit-Change-Number: 68594 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 19:48:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in flashrom[master]: chipset_enable.c: Mark Intel C246 as DEP
by Angel Pons (Code Review) 20 Oct '22

20 Oct '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/68594 ) Change subject: chipset_enable.c: Mark Intel C246 as DEP ...................................................................... chipset_enable.c: Mark Intel C246 as DEP Tested reading, writing and erasing the flash chip of a Prodrive Hermes mainboard with an Intel C246 PCH. However, since ME-enabled chipsets are marked as DEP instead of OK, this one shall also be. Change-Id: I07d6c4a60e468c61eba836db91e1335f4a762048 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M chipset_enable.c 1 file changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/68594/1 diff --git a/chipset_enable.c b/chipset_enable.c index d6103c1..60b82df 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2145,7 +2145,7 @@ {0x8086, 0xa305, B_S, DEP, "Intel", "Z390", enable_flash_pch300}, {0x8086, 0xa306, B_S, NT, "Intel", "Q370", enable_flash_pch300}, {0x8086, 0xa308, B_S, NT, "Intel", "B360", enable_flash_pch300}, - {0x8086, 0xa309, B_S, NT, "Intel", "C246", enable_flash_pch300}, + {0x8086, 0xa309, B_S, DEP, "Intel", "C246", enable_flash_pch300}, {0x8086, 0xa30a, B_S, NT, "Intel", "C242", enable_flash_pch300}, {0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300}, {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300}, -- To view, visit https://review.coreboot.org/c/flashrom/+/68594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I07d6c4a60e468c61eba836db91e1335f4a762048 Gerrit-Change-Number: 68594 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in flashrom[master]: flashrom.c: Move count_max_decode_exceeding() to cli
by Angel Pons (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Edward O'Callaghan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/68438 ) Change subject: flashrom.c: Move count_max_decode_exceeding() to cli ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > It crossed my mind however I didn't want to introduce it to a user facing API pre-maturely. […] Yeah, we can introduce new APIs when someone needs them. Also, +1 to the idea of extracting the chunk of code using `limitexceeded` in `main()`. -- To view, visit https://review.coreboot.org/c/flashrom/+/68438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If050eab7db8560676c03d5005a2b391313a0d642 Gerrit-Change-Number: 68438 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Thu, 20 Oct 2022 08:37:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in flashrom[master]: [WIP] Unit tests for erase function selection algo
by Nikolai Artemiev (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Simon Buhrow, Thomas Heijligen, Aarya, Anastasia Klimchuk. Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67535 ) Change subject: [WIP] Unit tests for erase function selection algo ...................................................................... Patch Set 5: (3 comments) File tests/erase_func_algo.c: https://review.coreboot.org/c/flashrom/+/67535/comment/6900e556_f2bac54c PS5, Line 37: uint8_t buf[MOCK_CHIP_SIZE]; /* Contents of the mock chip. */ Can `buf` be moved into `struct all_state`? Then we just have one global buffer for the chip contents. We'd also need to change `memcpy(buf, &g_state.test_cases[g_state.ind].buf[start], len);` to `memcpy(buf, &g_state.buf[start], len);` etc. Then the test_case struct will only contain test parameters and can be const. https://review.coreboot.org/c/flashrom/+/67535/comment/86b59401_6286a82b PS5, Line 183: ) We can reduce global state by passing the test case as an argument here, i.e. `, const struct test_case *test_data)` https://review.coreboot.org/c/flashrom/+/67535/comment/1be779c0_93153e0d PS5, Line 501: memcmp This should probably be`!memcmp(...`, otherwise `chip_erased` has the opposite meaning of the variable name. ditto in the functions below -- To view, visit https://review.coreboot.org/c/flashrom/+/67535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8f3fdefb76e71f6f8dc295d9dead5f38642aace7 Gerrit-Change-Number: 67535 Gerrit-PatchSet: 5 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 20 Oct 2022 06:44:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashrom.c: Fix sanitisation after initialisation bug
by Edward O'Callaghan (Code Review) 20 Oct '22

20 Oct '22

Edward O'Callaghan has abandoned this change. ( https://review.coreboot.org/c/flashrom/+/66683 ) Change subject: flashrom.c: Fix sanitisation after initialisation bug ...................................................................... Abandoned fixed in HEAD. -- To view, visit https://review.coreboot.org/c/flashrom/+/66683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic226aa27003fac13f83b149e0e4243ac91750d02 Gerrit-Change-Number: 66683 Gerrit-PatchSet: 4 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: abandon

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[M] Change in flashrom[master]: flashrom.c: Move count_max_decode_exceeding() to cli
by Edward O'Callaghan (Code Review) 20 Oct '22

20 Oct '22

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/68438 ) Change subject: flashrom.c: Move count_max_decode_exceeding() to cli ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Not sure if moving this to the libflashrom API makes sense. […] It crossed my mind however I didn't want to introduce it to a user facing API pre-maturely. I think the logical step after this was to move the hunk out of `main()`: ``` unsigned int limitexceeded = count_max_decode_exceedings(fill_flash); if (limitexceeded > 0 && !force) { enum chipbustype commonbuses = fill_flash->mst->buses_supported & fill_flash->chip->bustype; /* Sometimes chip and programmer have more than one bus in common, * and the limit is not exceeded on all buses. Tell the user. */ if ((bitcount(commonbuses) > limitexceeded)) { msg_pdbg("There is at least one interface available which could support the size of\n" "the selected flash chip.\n"); } msg_cerr("This flash chip is too big for this programmer (--verbose/-V gives details).\n" "Use --force/-f to override at your own risk.\n"); ret = 1; goto out_shutdown; } ``` into a function `check_chip_support_buses(fill_flash);` after the `print_chip_support_status(fill_flash->chip);` line and also have `count_max_decode_exceedings()` as a pure function that doesn't rely on globals. That way at least all these fragments of logic are collated together into something coherent - give me a context and I will check if the bus limits are suitable for the chip/programmer pair. -- To view, visit https://review.coreboot.org/c/flashrom/+/68438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If050eab7db8560676c03d5005a2b391313a0d642 Gerrit-Change-Number: 68438 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Oct 2022 00:57:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in flashrom[master]: [WIP] Unit tests for erase function selection algo
by Anastasia Klimchuk (Code Review) 19 Oct '22

19 Oct '22

Attention is currently required from: Simon Buhrow, Thomas Heijligen, Aarya, Anastasia Klimchuk. Hello build bot (Jenkins), Simon Buhrow, Thomas Heijligen, Edward O'Callaghan, Aarya, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/67535 to look at the new patch set (#5). Change subject: [WIP] Unit tests for erase function selection algo ...................................................................... [WIP] Unit tests for erase function selection algo This patch at the moment for testing only and not ready for an actual code review. Change-Id: I8f3fdefb76e71f6f8dc295d9dead5f38642aace7 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- A tests/erase_func_algo.c M tests/meson.build M tests/tests.c M tests/tests.h 4 files changed, 585 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/35/67535/5 -- To view, visit https://review.coreboot.org/c/flashrom/+/67535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8f3fdefb76e71f6f8dc295d9dead5f38642aace7 Gerrit-Change-Number: 67535 Gerrit-PatchSet: 5 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in flashrom[master]: nicintel_eeprom.c: Fix typo
by Alexander Goncharov (Code Review) 19 Oct '22

19 Oct '22

Attention is currently required from: Felix Singer. Alexander Goncharov has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/68582 ) Change subject: nicintel_eeprom.c: Fix typo ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/flashrom/+/68582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idc0a0c475e891fc8538a7a81093520e01e1b25bf Gerrit-Change-Number: 68582 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Wed, 19 Oct 2022 20:07:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in flashrom[master]: nicintel_eeprom: refactor i210 variable into reentrant pattern
by Angel Pons (Code Review) 19 Oct '22

19 Oct '22

Attention is currently required from: Alexander Goncharov. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/66690 ) Change subject: nicintel_eeprom: refactor i210 variable into reentrant pattern ...................................................................... Patch Set 5: (1 comment) File nicintel_eeprom.c: https://review.coreboot.org/c/flashrom/+/66690/comment/1b1cc45d_28a22b54 PS5, Line 84: done_i20_write > Fixed in CB:68582. Thanks! -- To view, visit https://review.coreboot.org/c/flashrom/+/66690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ifda0d8666399ea165bac6378c57720b5560806f1 Gerrit-Change-Number: 66690 Gerrit-PatchSet: 5 Gerrit-Owner: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Comment-Date: Wed, 19 Oct 2022 19:06:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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flashrom-gerrit October 2022