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Hello build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/57797
to look at the new patch set (#2).
Change subject: remove compile guards
......................................................................
remove compile guards
The build system handles the decision when to build a file.
Exta compile guards for the source files are not neccessery.
Change-Id: I76a76e05c7a7dd27637325ab1e9d8946fd5f9076
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.de>
---
M amd_imc.c
M atahpt.c
M atapromise.c
M ene_lpc.c
M ft2232_spi.c
M ichspi.c
M it85spi.c
M it87spi.c
M linux_spi.c
M mcp6x_spi.c
M mec1308.c
M mstarddc_spi.c
M nic3com.c
M nicnatsemi.c
M nicrealtek.c
M rayer_spi.c
M satamv.c
M sb600spi.c
M usbblaster_spi.c
M wbsio_spi.c
20 files changed, 0 insertions(+), 89 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/97/57797/2
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Victor Ding has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/56475 )
Change subject: ene_lpc: remove ENE LPC programmer
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> > It's not known if the code worked on any device when merged. […]
Thank you all for looking into this, especially for the great effort to keep these two programmers alive.
What should I do next? I believe this can be useful for certain users (e.g. Lenovo G505s); however the last Chromebook using it is now EOL. I'm afraid that I won't be able to find a device to debug and verify the programmer, despite how much I'd like to keep them alive.
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David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55651 )
Change subject: ich_descriptors: Normalize chipset detection
......................................................................
Patch Set 5:
(1 comment)
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/55651/comment/473eb2b3_5f45bdb3
PS5, Line 936: if (content->ISL <= 16)
: return CHIPSET_5_SERIES_IBEX_PEAK;
> For instance, when I wrote this patch,
> I would not have guessed that a server platform will land on this ICCRIBA
> == 0 branch. Trying to predict such details can lead to walking in circles
> patch wise.
I'm sure you did what seemed right with the information that you had at the time. Intel threw a curvaball at us with this.
> For instance, I assume that it's easier to follow the code
> when it's more condensed, like after this patch. Before the entire patch
> train it was a forest of if's and nobody knew where to put anything. We
> should avoid that this happens again.
Yeah, flashrom tends to accumulate cruft as new similar-but-slightly-different hardware gets added. I'm glad you refactored this, and FWIW the original EBG patch (CB:54965) definitely looked better after rebasing.
> Only one thing I have to ask you: As the purpose of this patch was to
> normalize, please do so with explicit if's for all chipsets then.
> warn_peculiar_desc() probably shouldn't have to check anything then.
Done: CB:57793
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/56475 )
Change subject: ene_lpc: remove ENE LPC programmer
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> It's not known if the code worked on any device when merged.
I highly doubt it... first issue when testing here: missing iopl/ioperm \o/
> It's also not known if the code is device specific and what firmware, if any, is expected on the EC.
Firmware is definitely expected. Take a look at lines 138ff. These are EC fw commands.
Unfortunately, I'm having massive issues with EDI flashing atm. It looks my EC is dying .... (It worked many times before without problems.) That means I can't test/fix this programmer, anyway :/
> I'd say it's best to get it through a proper review if anybody finds a use case for it. Same story for the follow-up commit.
Ack.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55578 )
Change subject: Add Tiger Lake U Premium support
......................................................................
Patch Set 12: Code-Review+2
(2 comments)
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/55578/comment/78f6f661_6d602c55
PS3, Line 659: { "eSPI", BUS_LPC | BUS_FWH } };
> Done. […]
Thanks! that's even better :)
File flash.h:
https://review.coreboot.org/c/flashrom/+/55578/comment/76e544de_050f20ed
PS10, Line 71: BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH,
> Hard to tell. BUS_NONSPI is mostly used on older southbridges/chipsets in chipset_enable. […]
Heh, I was wondering about that comment too. Maybe it means that once we
treat all bus types similarly in common code, we won't have to check for
SPI/NONSPI explicitly anywhere.
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