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Change subject: ch341a_spi: libusb functions can handle all platforms
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
This would change the behavior on non-Linux platforms where libusb implements
this API. Without us being able to test things right away. (Hate to say it)
maybe something to post-pone after the next release?
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Change subject: ft2232_spi: reintroduce generic GPIOL control
......................................................................
Patch Set 16: Code-Review+1
(5 comments)
Patchset:
PS16:
Alan, would the new syntax suit your needs?
File ft2232_spi.c:
https://review.coreboot.org/c/flashrom/+/57810/comment/310892f1_87318f3a
PS16, Line 483: msg_perr
As the message says "warning", use msg_pwarn()?
https://review.coreboot.org/c/flashrom/+/57810/comment/9d2ecba1_f5c3f5d0
PS16, Line 484: "in the future. Use `gpiolX=C` instead.\n");
We try to keep output within 80 columns. Could add a \n after the
first sentence for instance.
https://review.coreboot.org/c/flashrom/+/57810/comment/4586c346_7eaeb773
PS16, Line 513: arg_gpiol[3] = extract_programmer_param("gpiol3");
This looks a little odd. How about moving the call into the loop?
We could still use an array for the string literals, e.g.
const char *const gpiol_params[] = { "gpiol0", "gpiol1", ...
char *const arg = extract_programmer_param(gpiol_params[pin]);
Alternatively, a single buffer could be used like this:
char gpiol_param[7];
snprintf(gpiol_param, sizeof(gpiol_param), "gpiol%d", pin);
char *const arg = extract_programmer_param(gpiol_param);
Also just noticed: In the current form, any premature `return` inside
the loop would leak some of these arg_gpiol[] pointers.
https://review.coreboot.org/c/flashrom/+/57810/comment/8d311a6c_c4f6ed80
PS16, Line 538: bool format_error = 0;
Just to mention it, don't know how reasonable it would look: For error
paths, using `goto` is common. The end of the loop body could look like
this:
free(arg);
continue;
format_error:
msg_perr("Error: ...");
free(arg);
return -2;
}
It would save us an indentation level.
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Change subject: flashrom.8: carve out `csgpiol` into its own section
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File flashrom.8.tmpl:
https://review.coreboot.org/c/flashrom/+/57893/comment/d2d2cc60_ab1d0594
PS2, Line 843: and GPIO-based chip select
Please drop this part. Basically, we'd want to revert the changes of
CB:28911 made here.
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Change subject: ft2232_spi: prevent use of reserved pins on some programmers
......................................................................
Patch Set 6: Code-Review+1
(2 comments)
File ft2232_spi.c:
https://review.coreboot.org/c/flashrom/+/57809/comment/b561e66a_b011ac32
PS6, Line 424: resered
reser*v*ed
https://review.coreboot.org/c/flashrom/+/57809/comment/0d1e69f6_5cca4339
PS6, Line 424: gets
drop one `gets` please
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Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/57808 )
Change subject: ft2232_spi: clarify the comment about gpio configuration
......................................................................
ft2232_spi: clarify the comment about gpio configuration
The comment explaining gpio levels might be easily misunderstood when
the reader misses the word `output`. Add an explicit description of
handling of the GPIOL* pins to avoid that and make things even more
clear.
Change-Id: Iaceec889a65ead8cdde917f61b2a9695d440f781
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/57808
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---
M ft2232_spi.c
1 file changed, 5 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
diff --git a/ft2232_spi.c b/ft2232_spi.c
index 0962f1c..df156d6 100644
--- a/ft2232_spi.c
+++ b/ft2232_spi.c
@@ -89,8 +89,11 @@
* "set data bits low byte" MPSSE command that sets the initial
* state and the direction of the I/O pins. `cs_bits` pins default
* to high and will be toggled during SPI transactions. All other
- * output pins will be kept low all the time. On exit, all pins
- * will be reconfigured as inputs.
+ * output pins will be kept low all the time. For some programmers,
+ * some reserved GPIOL* pins are used as outputs. Free GPIOL* pins
+ * are configured as inputs, while it's possible to use one of them
+ * as additional CS# signal through the parameter `csgpiol`. On exit,
+ * all pins will be reconfigured as inputs.
*
* The pin offsets are as follows:
* TCK/SK is bit 0.
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/57807 )
Change subject: flashrom.8: add missing entry for `--flash-contents`
......................................................................
flashrom.8: add missing entry for `--flash-contents`
Change-Id: I64a8200a86329bd26a2069c5dc39430de9f8ba09
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/57807
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---
M flashrom.8.tmpl
1 file changed, 7 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index c9620fe..788e254 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -290,6 +290,13 @@
.B "\-\-flash\-size"
Prints out the detected flash chips size.
.TP
+.B "\-\-flash\-contents <ref\-file>"
+The file contents of
+.BR <ref\-file>
+will be used to decide which parts of the flash need to be written. Providing
+this saves an initial read of the full flash chip. Be careful, if the provided
+data doesn't actually match the flash contents, results are undefined.
+.TP
.B "\-L, \-\-list\-supported"
List the flash chips, chipsets, mainboards, and external programmers
(including PCI, USB, parallel port, and serial port based devices)
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Change subject: ich_descriptors: Add explicit checks for all chipsets
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/57793/comment/4cdee6e3_96a30ceb
PS3, Line 10: A new chipset
: was added that necessitated adding back a check for an older
: chipset.
That's not accurate. It was the way that the new check was written
that made more checks necessary.
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/57793/comment/786867a3_89395d49
PS1, Line 968: if (content->ICCRIBA != 0x34)
: msg_pwarn("Unknown flash descriptor, assuming 300 series compatibility.\n");
> here too
This one had a different message.
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