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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55578 )
Change subject: Add Tiger Lake U Premium support
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/55578/comment/8e0db6d6_fbbb56c3
PS3, Line 10: uknown
unknown
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Change subject: Add Tiger Lake U Premium support
......................................................................
Patch Set 3:
(1 comment)
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/55578/comment/cb3a4998_bd1b7079
PS3, Line 659: { "eSPI", BUS_LPC | BUS_FWH } };
Not sure about this one, whether eSPI should be mapped to LPC and FWH
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Hello Nico Huber, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/55993
to look at the new patch set (#2).
Change subject: ich_descriptors_tool: Add missing Comet Point in usage
......................................................................
ich_descriptors_tool: Add missing Comet Point in usage
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Ia1e3e231944513521d5db064340a0247f1884290
---
M util/ich_descriptors_tool/ich_descriptors_tool.c
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/55993/2
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Attention is currently required from: Nico Huber.
Hello build bot (Jenkins), Nico Huber, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/55578
to look at the new patch set (#3).
Change subject: Add Tiger Lake U Premium support
......................................................................
Add Tiger Lake U Premium support
Tiger Lake has very low ICCRIBA (TGL=0x11, CNL=0x34 and CML=0x34) and
detects as uknown chipset compatible with 300 series chipset. Add a
new enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to
CHIPSET_400_SERIES_COMET_POINT except the ICCRIBA in descriptor
guessing, pprint_freq and boot straps.
TEST=Flash BIOS region on Intel i5-1135G7
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd
---
M chipset_enable.c
M ich_descriptors.c
M ichspi.c
M programmer.h
M util/ich_descriptors_tool/ich_descriptors_tool.c
5 files changed, 42 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/55578/3
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Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/55993 )
Change subject: ich_descriptors_tool: Add missing Comet Point in usage
......................................................................
ich_descriptors_tool: Add missing Comet Point in usage
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Ia1e3e231944513521d5db064340a0247f1884290
---
M util/ich_descriptors_tool/ich_descriptors_tool.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/55993/1
diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c
index bfeedc1..e738455 100644
--- a/util/ich_descriptors_tool/ich_descriptors_tool.c
+++ b/util/ich_descriptors_tool/ich_descriptors_tool.c
@@ -135,6 +135,7 @@
"\t- \"9\" or \"wildcat\" for Intel's 9 series chipsets.\n"
"\t- \"100\" or \"sunrise\" for Intel's 100 series chipsets.\n"
"\t- \"300\" or \"cannon\" for Intel's 300 series chipsets.\n"
+"\t- \"400\" or \"comet\" for Intel's 400 series chipsets.\n"
"If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n"
"the GbE blob that is required to initialize the GbE are also dumped to files.\n",
argv[0], argv[0]);
@@ -229,6 +230,9 @@
else if ((strcmp(csn, "400") == 0) ||
(strcmp(csn, "comet") == 0))
cs = CHIPSET_400_SERIES_COMET_POINT;
+ else if ((strcmp(csn, "500") == 0) ||
+ (strcmp(csn, "tiger") == 0))
+ cs = CHIPSET_500_SERIES_TIGER_POINT;
else if (strcmp(csn, "apollo") == 0)
cs = CHIPSET_APOLLO_LAKE;
else if (strcmp(csn, "gemini") == 0)
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Attention is currently required from: Nico Huber.
Hello build bot (Jenkins), Nico Huber, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/55578
to look at the new patch set (#2).
Change subject: Add Tiger Lake U Premium support
......................................................................
Add Tiger Lake U Premium support
Tiger Lake has very low ICCRIBA (TGL=0x11, CNL=0x34 and CML=0x34) and
detects as uknown chipset compatible with 300 series chipset. Add a
new enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to
CHIPSET_400_SERIES_COMET_POINT except the ICCRIBA in descriptor
guessing, pprint_freq and boot straps.
TEST=Flash BIOS region on Intel i5-1135G7
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd
---
M chipset_enable.c
M ich_descriptors.c
M ichspi.c
M programmer.h
M util/ich_descriptors_tool/ich_descriptors_tool.c
5 files changed, 39 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/55578/2
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54890 )
Change subject: programmer: Introduce default shutdown function
......................................................................
Patch Set 5: Code-Review+2
(1 comment)
Patchset:
PS5:
> There are two reasons why I thought of default shutdown function. […]
Personally, I don't mind adding something that ends up being removed later, as long as it provides some benefit. I can see why this `default_shutdown()` function may end up being unnecessary in the future, but this commit would ease (even if only slightly) follow-up works as there would be less shutdown functions to adapt and/or remove.
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