May 2021 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: programmer: Smoothen register_spi_master() API
by Nico Huber (Code Review) 13 May '21

13 May '21

Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/54066 ) Change subject: programmer: Smoothen register_spi_master() API ...................................................................... programmer: Smoothen register_spi_master() API It was impossible to register a const struct spi_master that would point to dynamically allocated `data`. Fix that so that we won't have to create more mutable globals. Change-Id: I0c753b3db050fb87d4bbe2301a7ead854f28456f Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54066 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M bitbang_spi.c M buspirate_spi.c M ch341a_spi.c M dediprog.c M digilent_spi.c M dummyflasher.c M ene_lpc.c M ft2232_spi.c M ichspi.c M it85spi.c M it87spi.c M jlink_spi.c M linux_spi.c M lspcon_i2c_spi.c M mec1308.c M mstarddc_spi.c M ni845x_spi.c M pickit2_spi.c M programmer.h M raiden_debug_spi.c M realtek_mst_i2c_spi.c M sb600spi.c M serprog.c M spi.c M stlinkv3_spi.c M usbblaster_spi.c M wbsio_spi.c 27 files changed, 33 insertions(+), 31 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Anastasia Klimchuk: Looks good to me, but someone else must approve diff --git a/bitbang_spi.c b/bitbang_spi.c index b12d81a..bb89071 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -162,7 +162,7 @@ struct bitbang_spi_master_data *data = calloc(1, sizeof(struct bitbang_spi_master_data)); data->mst = master; mst.data = data; - register_spi_master(&mst); + register_spi_master(&mst, NULL); register_shutdown(bitbang_spi_shutdown, data); /* Only mess with the bus if we're sure nobody else uses it. */ diff --git a/buspirate_spi.c b/buspirate_spi.c index eee8daa..96e9673 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -655,7 +655,7 @@ return 1; } - register_spi_master(&spi_master_buspirate); + register_spi_master(&spi_master_buspirate, NULL); return 0; } diff --git a/ch341a_spi.c b/ch341a_spi.c index 84cc3fe..f84add4 100644 --- a/ch341a_spi.c +++ b/ch341a_spi.c @@ -506,7 +506,7 @@ goto dealloc_transfers; register_shutdown(ch341a_spi_shutdown, NULL); - register_spi_master(&spi_master_ch341a_spi); + register_spi_master(&spi_master_ch341a_spi, NULL); return 0; diff --git a/dediprog.c b/dediprog.c index 4f48f47..a8fe19e 100644 --- a/dediprog.c +++ b/dediprog.c @@ -1274,7 +1274,7 @@ if (protocol() >= PROTOCOL_V2) spi_master_dediprog.features |= SPI_MASTER_4BA; - if (register_spi_master(&spi_master_dediprog) || dediprog_set_leds(LED_NONE)) + if (register_spi_master(&spi_master_dediprog, NULL) || dediprog_set_leds(LED_NONE)) return 1; return 0; diff --git a/digilent_spi.c b/digilent_spi.c index 91a28b0..5471724 100644 --- a/digilent_spi.c +++ b/digilent_spi.c @@ -457,7 +457,7 @@ spi_master_digilent_spi.data = digilent_data; register_shutdown(digilent_spi_shutdown, digilent_data); - register_spi_master(&spi_master_digilent_spi); + register_spi_master(&spi_master_digilent_spi, NULL); return 0; diff --git a/dummyflasher.c b/dummyflasher.c index ec5060d..74075f4 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -1030,7 +1030,7 @@ register_par_master(&par_master_dummy, dummy_buses_supported & (BUS_PARALLEL | BUS_LPC | BUS_FWH)); if (dummy_buses_supported & BUS_SPI) - register_spi_master(&spi_master_dummyflasher); + register_spi_master(&spi_master_dummyflasher, NULL); return 0; } diff --git a/ene_lpc.c b/ene_lpc.c index b66e96e..46f1783 100644 --- a/ene_lpc.c +++ b/ene_lpc.c @@ -572,7 +572,7 @@ if (register_shutdown(ene_leave_flash_mode, ctx_data)) goto init_err_cleanup_exit; - register_spi_master(&spi_master_ene); + register_spi_master(&spi_master_ene, NULL); msg_pdbg("%s: successfully initialized ene\n", __func__); return 0; diff --git a/ft2232_spi.c b/ft2232_spi.c index bdc6e37..8d50d20 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -626,7 +626,7 @@ free(spi_data); goto ftdi_err; } - register_spi_master(&spi_master_ft2232); + register_spi_master(&spi_master_ft2232, NULL); return 0; diff --git a/ichspi.c b/ichspi.c index e45b39a..613f3fc 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1812,7 +1812,7 @@ } ich_init_opcodes(ich_gen); ich_set_bbar(0, ich_gen); - register_spi_master(&spi_master_ich7); + register_spi_master(&spi_master_ich7, NULL); break; case CHIPSET_ICH8: default: /* Future version might behave the same */ @@ -2041,7 +2041,7 @@ register_opaque_master(&opaque_master_ich_hwseq); } else { - register_spi_master(&spi_master_ich9); + register_spi_master(&spi_master_ich9, NULL); } break; } @@ -2071,7 +2071,7 @@ /* Not sure if it speaks all these bus protocols. */ internal_buses_supported &= BUS_LPC | BUS_FWH; ich_generation = CHIPSET_ICH7; - register_spi_master(&spi_master_via); + register_spi_master(&spi_master_via, NULL); msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); diff --git a/it85spi.c b/it85spi.c index 9817c2a..4d0f988 100644 --- a/it85spi.c +++ b/it85spi.c @@ -366,7 +366,7 @@ * a debug message about it. */ /* Set this as SPI controller. */ - register_spi_master(&spi_master_it85xx); + register_spi_master(&spi_master_it85xx, NULL); return 0; } diff --git a/it87spi.c b/it87spi.c index 868b479..0760ac8 100644 --- a/it87spi.c +++ b/it87spi.c @@ -426,7 +426,7 @@ if (internal_buses_supported & BUS_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); /* FIXME: Add the SPI bus or replace the other buses with it? */ - register_spi_master(&spi_master_it87xx); + register_spi_master(&spi_master_it87xx, NULL); return 0; } diff --git a/jlink_spi.c b/jlink_spi.c index 8b5cd2c..9fe44a5 100644 --- a/jlink_spi.c +++ b/jlink_spi.c @@ -472,7 +472,7 @@ if (register_shutdown(jlink_spi_shutdown, jlink_data)) goto init_err; - register_spi_master(&spi_master_jlink_spi); + register_spi_master(&spi_master_jlink_spi, NULL); return 0; diff --git a/linux_spi.c b/linux_spi.c index 4668e7f..82741bf 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -244,7 +244,7 @@ free(spi_data); goto init_err; } - register_spi_master(&spi_master_linux); + register_spi_master(&spi_master_linux, NULL); return 0; init_err: diff --git a/lspcon_i2c_spi.c b/lspcon_i2c_spi.c index 096fb76..6b8dfe6 100644 --- a/lspcon_i2c_spi.c +++ b/lspcon_i2c_spi.c @@ -457,7 +457,7 @@ spi_master_i2c_lspcon.data = data; ret |= register_shutdown(lspcon_i2c_spi_shutdown, data); - ret |= register_spi_master(&spi_master_i2c_lspcon); + ret |= register_spi_master(&spi_master_i2c_lspcon, NULL); return ret; } diff --git a/mec1308.c b/mec1308.c index 1530d9b..70d2a79 100644 --- a/mec1308.c +++ b/mec1308.c @@ -509,7 +509,7 @@ if (register_shutdown(mec1308_shutdown, ctx_data)) goto init_err_cleanup_exit; - register_spi_master(&spi_master_mec1308); + register_spi_master(&spi_master_mec1308, NULL); msg_pdbg("%s(): successfully initialized mec1308\n", __func__); return 0; diff --git a/mstarddc_spi.c b/mstarddc_spi.c index c041bd3..32b77cd 100644 --- a/mstarddc_spi.c +++ b/mstarddc_spi.c @@ -221,7 +221,7 @@ register_shutdown(mstarddc_spi_shutdown, NULL); // Register programmer - register_spi_master(&spi_master_mstarddc); + register_spi_master(&spi_master_mstarddc, NULL); out: free(i2c_device); return ret; diff --git a/ni845x_spi.c b/ni845x_spi.c index 765da8a..df8ae0d 100644 --- a/ni845x_spi.c +++ b/ni845x_spi.c @@ -630,7 +630,7 @@ return 1; } - register_spi_master(&spi_programmer_ni845x); + register_spi_master(&spi_programmer_ni845x, NULL); return 0; } diff --git a/pickit2_spi.c b/pickit2_spi.c index 3d0c775..47316d0 100644 --- a/pickit2_spi.c +++ b/pickit2_spi.c @@ -501,7 +501,7 @@ if (register_shutdown(pickit2_shutdown, pickit2_data)) goto init_err_cleanup_exit; - register_spi_master(&spi_master_pickit2); + register_spi_master(&spi_master_pickit2, NULL); return 0; diff --git a/programmer.h b/programmer.h index 675a259..1b0cdb9 100644 --- a/programmer.h +++ b/programmer.h @@ -643,7 +643,7 @@ int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int default_spi_write_aai(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); -int register_spi_master(const struct spi_master *mst); +int register_spi_master(const struct spi_master *mst, void *data); /* The following enum is needed by ich_descriptor_tool and ich* code as well as in chipset_enable.c. */ enum ich_chipset { diff --git a/raiden_debug_spi.c b/raiden_debug_spi.c index bd7c054..c275851 100644 --- a/raiden_debug_spi.c +++ b/raiden_debug_spi.c @@ -1614,7 +1614,7 @@ return SPI_GENERIC_ERROR; } - register_spi_master(spi_config); + register_spi_master(spi_config, NULL); register_shutdown(raiden_debug_spi_shutdown, spi_config); return 0; diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 10a1dff..f0a6dce 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -515,7 +515,7 @@ ret |= register_shutdown(realtek_mst_i2c_spi_shutdown, data); spi_master_i2c_realtek_mst.data = data; - ret |= register_spi_master(&spi_master_i2c_realtek_mst); + ret |= register_spi_master(&spi_master_i2c_realtek_mst, NULL); return ret; } diff --git a/sb600spi.c b/sb600spi.c index ef9da4b..43bf407 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -786,11 +786,11 @@ /* Starting with Yangtze the SPI controller got a different interface with a much bigger buffer. */ if (amd_gen < CHIPSET_YANGTZE) - register_spi_master(&spi_master_sb600); + register_spi_master(&spi_master_sb600, NULL); else if (amd_gen == CHIPSET_YANGTZE) - register_spi_master(&spi_master_yangtze); + register_spi_master(&spi_master_yangtze, NULL); else - register_spi_master(&spi_master_promontory); + register_spi_master(&spi_master_promontory, NULL); return 0; } diff --git a/serprog.c b/serprog.c index d583a40..056d8d1 100644 --- a/serprog.c +++ b/serprog.c @@ -883,7 +883,7 @@ sp_streamed_transmit_bytes = 0; sp_opbuf_usage = 0; if (serprog_buses_supported & BUS_SPI) - register_spi_master(&spi_master_serprog); + register_spi_master(&spi_master_serprog, NULL); if (serprog_buses_supported & BUS_NONSPI) register_par_master(&par_master_serprog, serprog_buses_supported & BUS_NONSPI); return 0; diff --git a/spi.c b/spi.c index aa245d7..4ac3914 100644 --- a/spi.c +++ b/spi.c @@ -131,7 +131,7 @@ return flash->mst->spi.write_aai(flash, buf, start, len); } -int register_spi_master(const struct spi_master *mst) +int register_spi_master(const struct spi_master *mst, void *data) { struct registered_master rmst = {0}; @@ -148,5 +148,7 @@ rmst.buses_supported = BUS_SPI; rmst.spi = *mst; + if (data) + rmst.spi.data = data; return register_master(&rmst); } diff --git a/stlinkv3_spi.c b/stlinkv3_spi.c index 7e8336e..7712ec2 100644 --- a/stlinkv3_spi.c +++ b/stlinkv3_spi.c @@ -509,7 +509,7 @@ if (register_shutdown(stlinkv3_spi_shutdown, NULL)) goto err_exit; - if (register_spi_master(&spi_programmer_stlinkv3)) + if (register_spi_master(&spi_programmer_stlinkv3, NULL)) goto err_exit; return 0; diff --git a/usbblaster_spi.c b/usbblaster_spi.c index c92efe6..b652a3d 100644 --- a/usbblaster_spi.c +++ b/usbblaster_spi.c @@ -232,7 +232,7 @@ free(usbblaster_data); return -1; } - register_spi_master(&spi_master_usbblaster); + register_spi_master(&spi_master_usbblaster, NULL); return 0; } diff --git a/wbsio_spi.c b/wbsio_spi.c index 632ff72..9eed495 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -216,7 +216,7 @@ register_shutdown(wbsio_spi_shutdown, data); spi_master_wbsio.data = data; - register_spi_master(&spi_master_wbsio); + register_spi_master(&spi_master_wbsio, NULL); return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/54066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0c753b3db050fb87d4bbe2301a7ead854f28456f Gerrit-Change-Number: 54066 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[testpush]: Revert "Revert "Add Gemini Lake support""
by Nico Huber (Code Review) 13 May '21

13 May '21

Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/54277 ) Change subject: Revert "Revert "Add Gemini Lake support"" ...................................................................... Revert "Revert "Add Gemini Lake support"" This reverts commit a2b33b9f300ec22832367b10ab49fff6f179dcc5. Change-Id: Id0106ecb2612d1c7b286c3b849a42756caf741cd Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54277 --- M chipset_enable.c M ich_descriptors.c M ich_descriptors.h M ichspi.c M programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 6 files changed, 37 insertions(+), 7 deletions(-) Approvals: Nico Huber: Verified; Looks good to me, approved diff --git a/chipset_enable.c b/chipset_enable.c index 259902e..025203c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -601,6 +601,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: reg_name = "BIOS_SPI_BC"; gcs = pci_read_long(dev, 0xdc); bild = (gcs >> 7) & 1; @@ -699,6 +700,7 @@ boot_straps = boot_straps_pch8_lp; break; case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: boot_straps = boot_straps_apl; break; case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet @@ -726,6 +728,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: bbs = (gcs >> 6) & 0x1; break; default: @@ -976,6 +979,11 @@ return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); } +static int enable_flash_glk(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_GEMINI_LAKE); +} + /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately. * @@ -2076,6 +2084,7 @@ {0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100}, {0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, {0x8086, 0x5af0, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, + {0x8086, 0x31e8, B_S, DEP, "Intel", "Gemini Lake", enable_flash_glk}, {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300}, {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300}, {0x8086, 0xa305, B_S, NT, "Intel", "Z390", enable_flash_pch300}, diff --git a/ich_descriptors.c b/ich_descriptors.c index 7374984..c5f9f82 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -39,6 +39,7 @@ { switch (cs) { case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: return 6; case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: @@ -68,6 +69,7 @@ switch (cs) { case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: if (cont->NM <= MAX_NUM_MASTERS) return cont->NM; break; @@ -104,7 +106,7 @@ "5 series Ibex Peak", "6 series Cougar Point", "7 series Panther Point", "8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg", "9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point", - "C620 series Lewisburg", "300 series Cannon Point", "Apollo Lake", + "C620 series Lewisburg", "300 series Cannon Point", "Apollo Lake", "Gemini Lake", }; if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names)) cs = 0; @@ -198,7 +200,8 @@ case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: - case CHIPSET_APOLLO_LAKE: { + case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: { uint8_t size_enc; if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; @@ -269,6 +272,7 @@ case CHIPSET_400_SERIES_COMET_POINT: return freq_str[1][value]; case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: return freq_str[2][value]; case CHIPSET_ICH_UNKNOWN: default: @@ -286,6 +290,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: has_flill1 = true; break; default: @@ -462,7 +467,7 @@ desc->master.mstr[i].write & (1 << j) ? 'w' : ' '); msg_pdbg2("\n"); } - } else if (cs == CHIPSET_APOLLO_LAKE) { + } else if (cs == CHIPSET_APOLLO_LAKE || cs == CHIPSET_GEMINI_LAKE) { const char *const master_names[] = { "BIOS", "TXE", }; if (nm > (ssize_t)ARRAY_SIZE(master_names)) { msg_pdbg2("%s: number of masters too high (%d).\n", __func__, desc->content.NM); @@ -922,7 +927,9 @@ else if (content->ISL <= 16) return CHIPSET_5_SERIES_IBEX_PEAK; else if (content->FLMAP2 == 0) { - if (content->ISL != 19) + if (content->ISL == 23) + return CHIPSET_GEMINI_LAKE; + else if (content->ISL != 19) msg_pwarn("Peculiar firmware descriptor, assuming Apollo Lake compatibility.\n"); return CHIPSET_APOLLO_LAKE; } @@ -967,6 +974,7 @@ switch (guess) { case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: + case CHIPSET_GEMINI_LAKE: /* `freq_read` was repurposed, so can't check on it any more. */ return guess; case CHIPSET_100_SERIES_SUNRISE_POINT: @@ -1123,6 +1131,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; } else { @@ -1159,6 +1168,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: mmio_le_writel(control, spibar + PCH100_REG_FDOC); return mmio_le_readl(spibar + PCH100_REG_FDOD); default: diff --git a/ich_descriptors.h b/ich_descriptors.h index c6bf5d8..727a31b 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -257,7 +257,7 @@ struct ich_desc_south_strap { union { - uint32_t STRPs[18]; /* current maximum: cougar point */ + uint32_t STRPs[23]; /* current maximum: gemini lake */ struct { /* ich8 */ struct { /* STRP1 */ uint32_t ME_DISABLE :1, diff --git a/ichspi.c b/ichspi.c index e45b39a..83920b4 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1740,6 +1740,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: num_pr = 6; /* Includes GPR0 */ reg_pr0 = PCH100_REG_FPR0; swseq_data.reg_ssfsc = PCH100_REG_SSFSC; @@ -1772,6 +1773,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: num_freg = 16; break; default: @@ -1868,6 +1870,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: tmp = mmio_readl(spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); prettyprint_pch100_reg_dlock(tmp); @@ -1943,6 +1946,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: case CHIPSET_BAYTRAIL: break; default: @@ -1976,6 +1980,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: break; default: tmp = mmio_readl(spibar + ICH9_REG_FPB); @@ -2012,8 +2017,10 @@ ich_spi_mode = ich_hwseq; } - if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_APOLLO_LAKE) { - msg_pdbg("Enabling hardware sequencing by default for Apollo Lake.\n"); + if (ich_spi_mode == ich_auto && + (ich_gen == CHIPSET_APOLLO_LAKE || + ich_gen == CHIPSET_GEMINI_LAKE)) { + msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini Lake.\n"); ich_spi_mode = ich_hwseq; } diff --git a/programmer.h b/programmer.h index 675a259..7124611 100644 --- a/programmer.h +++ b/programmer.h @@ -672,6 +672,7 @@ CHIPSET_300_SERIES_CANNON_POINT, CHIPSET_APOLLO_LAKE, CHIPSET_400_SERIES_COMET_POINT, + CHIPSET_GEMINI_LAKE, }; /* ichspi.c */ diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 32eea12..bfeedc1 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -127,6 +127,7 @@ "\t- \"ich10\",\n" "\t- \"silvermont\" for chipsets from Intel's Silvermont architecture (e.g. Bay Trail),\n" "\t- \"apollo\" for Intel's Apollo Lake SoC.\n" +"\t- \"gemini\" for Intel's Gemini Lake SoC.\n" "\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" @@ -230,6 +231,8 @@ cs = CHIPSET_400_SERIES_COMET_POINT; else if (strcmp(csn, "apollo") == 0) cs = CHIPSET_APOLLO_LAKE; + else if (strcmp(csn, "gemini") == 0) + cs = CHIPSET_GEMINI_LAKE; } ret = read_ich_descriptors_from_dump(buf, len, &cs, &desc); -- To view, visit https://review.coreboot.org/c/flashrom/+/54277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: testpush Gerrit-Change-Id: Id0106ecb2612d1c7b286c3b849a42756caf741cd Gerrit-Change-Number: 54277 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: merged

1 0

Change in flashrom[testpush]: Revert "Revert "Add Gemini Lake support""
by Nico Huber (Code Review) 13 May '21

13 May '21

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54277 ) Change subject: Revert "Revert "Add Gemini Lake support"" ...................................................................... Patch Set 1: Verified+1 Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/54277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: testpush Gerrit-Change-Id: Id0106ecb2612d1c7b286c3b849a42756caf741cd Gerrit-Change-Number: 54277 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 13 May 2021 14:34:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in flashrom[testpush]: Revert "Revert "Add Gemini Lake support""
by Nico Huber (Code Review) 13 May '21

13 May '21

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54277 ) Change subject: Revert "Revert "Add Gemini Lake support"" ...................................................................... Revert "Revert "Add Gemini Lake support"" This reverts commit a2b33b9f300ec22832367b10ab49fff6f179dcc5. Change-Id: Id0106ecb2612d1c7b286c3b849a42756caf741cd Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M chipset_enable.c M ich_descriptors.c M ich_descriptors.h M ichspi.c M programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 6 files changed, 37 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/54277/1 diff --git a/chipset_enable.c b/chipset_enable.c index 259902e..025203c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -601,6 +601,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: reg_name = "BIOS_SPI_BC"; gcs = pci_read_long(dev, 0xdc); bild = (gcs >> 7) & 1; @@ -699,6 +700,7 @@ boot_straps = boot_straps_pch8_lp; break; case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: boot_straps = boot_straps_apl; break; case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet @@ -726,6 +728,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: bbs = (gcs >> 6) & 0x1; break; default: @@ -976,6 +979,11 @@ return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); } +static int enable_flash_glk(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_GEMINI_LAKE); +} + /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately. * @@ -2076,6 +2084,7 @@ {0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100}, {0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, {0x8086, 0x5af0, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, + {0x8086, 0x31e8, B_S, DEP, "Intel", "Gemini Lake", enable_flash_glk}, {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300}, {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300}, {0x8086, 0xa305, B_S, NT, "Intel", "Z390", enable_flash_pch300}, diff --git a/ich_descriptors.c b/ich_descriptors.c index 7374984..c5f9f82 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -39,6 +39,7 @@ { switch (cs) { case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: return 6; case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: @@ -68,6 +69,7 @@ switch (cs) { case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: if (cont->NM <= MAX_NUM_MASTERS) return cont->NM; break; @@ -104,7 +106,7 @@ "5 series Ibex Peak", "6 series Cougar Point", "7 series Panther Point", "8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg", "9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point", - "C620 series Lewisburg", "300 series Cannon Point", "Apollo Lake", + "C620 series Lewisburg", "300 series Cannon Point", "Apollo Lake", "Gemini Lake", }; if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names)) cs = 0; @@ -198,7 +200,8 @@ case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: - case CHIPSET_APOLLO_LAKE: { + case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: { uint8_t size_enc; if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; @@ -269,6 +272,7 @@ case CHIPSET_400_SERIES_COMET_POINT: return freq_str[1][value]; case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: return freq_str[2][value]; case CHIPSET_ICH_UNKNOWN: default: @@ -286,6 +290,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: has_flill1 = true; break; default: @@ -462,7 +467,7 @@ desc->master.mstr[i].write & (1 << j) ? 'w' : ' '); msg_pdbg2("\n"); } - } else if (cs == CHIPSET_APOLLO_LAKE) { + } else if (cs == CHIPSET_APOLLO_LAKE || cs == CHIPSET_GEMINI_LAKE) { const char *const master_names[] = { "BIOS", "TXE", }; if (nm > (ssize_t)ARRAY_SIZE(master_names)) { msg_pdbg2("%s: number of masters too high (%d).\n", __func__, desc->content.NM); @@ -922,7 +927,9 @@ else if (content->ISL <= 16) return CHIPSET_5_SERIES_IBEX_PEAK; else if (content->FLMAP2 == 0) { - if (content->ISL != 19) + if (content->ISL == 23) + return CHIPSET_GEMINI_LAKE; + else if (content->ISL != 19) msg_pwarn("Peculiar firmware descriptor, assuming Apollo Lake compatibility.\n"); return CHIPSET_APOLLO_LAKE; } @@ -967,6 +974,7 @@ switch (guess) { case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: + case CHIPSET_GEMINI_LAKE: /* `freq_read` was repurposed, so can't check on it any more. */ return guess; case CHIPSET_100_SERIES_SUNRISE_POINT: @@ -1123,6 +1131,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; } else { @@ -1159,6 +1168,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: mmio_le_writel(control, spibar + PCH100_REG_FDOC); return mmio_le_readl(spibar + PCH100_REG_FDOD); default: diff --git a/ich_descriptors.h b/ich_descriptors.h index c6bf5d8..727a31b 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -257,7 +257,7 @@ struct ich_desc_south_strap { union { - uint32_t STRPs[18]; /* current maximum: cougar point */ + uint32_t STRPs[23]; /* current maximum: gemini lake */ struct { /* ich8 */ struct { /* STRP1 */ uint32_t ME_DISABLE :1, diff --git a/ichspi.c b/ichspi.c index e45b39a..83920b4 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1740,6 +1740,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: num_pr = 6; /* Includes GPR0 */ reg_pr0 = PCH100_REG_FPR0; swseq_data.reg_ssfsc = PCH100_REG_SSFSC; @@ -1772,6 +1773,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: num_freg = 16; break; default: @@ -1868,6 +1870,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: tmp = mmio_readl(spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); prettyprint_pch100_reg_dlock(tmp); @@ -1943,6 +1946,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: case CHIPSET_BAYTRAIL: break; default: @@ -1976,6 +1980,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: break; default: tmp = mmio_readl(spibar + ICH9_REG_FPB); @@ -2012,8 +2017,10 @@ ich_spi_mode = ich_hwseq; } - if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_APOLLO_LAKE) { - msg_pdbg("Enabling hardware sequencing by default for Apollo Lake.\n"); + if (ich_spi_mode == ich_auto && + (ich_gen == CHIPSET_APOLLO_LAKE || + ich_gen == CHIPSET_GEMINI_LAKE)) { + msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini Lake.\n"); ich_spi_mode = ich_hwseq; } diff --git a/programmer.h b/programmer.h index 675a259..7124611 100644 --- a/programmer.h +++ b/programmer.h @@ -672,6 +672,7 @@ CHIPSET_300_SERIES_CANNON_POINT, CHIPSET_APOLLO_LAKE, CHIPSET_400_SERIES_COMET_POINT, + CHIPSET_GEMINI_LAKE, }; /* ichspi.c */ diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 32eea12..bfeedc1 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -127,6 +127,7 @@ "\t- \"ich10\",\n" "\t- \"silvermont\" for chipsets from Intel's Silvermont architecture (e.g. Bay Trail),\n" "\t- \"apollo\" for Intel's Apollo Lake SoC.\n" +"\t- \"gemini\" for Intel's Gemini Lake SoC.\n" "\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" @@ -230,6 +231,8 @@ cs = CHIPSET_400_SERIES_COMET_POINT; else if (strcmp(csn, "apollo") == 0) cs = CHIPSET_APOLLO_LAKE; + else if (strcmp(csn, "gemini") == 0) + cs = CHIPSET_GEMINI_LAKE; } ret = read_ich_descriptors_from_dump(buf, len, &cs, &desc); -- To view, visit https://review.coreboot.org/c/flashrom/+/54277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: testpush Gerrit-Change-Id: Id0106ecb2612d1c7b286c3b849a42756caf741cd Gerrit-Change-Number: 54277 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

1 0

Change in flashrom[master]: Add Gemini Lake support
by Angel Pons (Code Review) 13 May '21

13 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54276 ) Change subject: Add Gemini Lake support ...................................................................... Add Gemini Lake support The SPI hardware is pretty much unchanged from Apollo Lake. However, the IFD differs significantly enough to require special handling. Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Change-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77 --- M chipset_enable.c M ich_descriptors.c M ich_descriptors.h M ichspi.c M programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 6 files changed, 37 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/76/54276/1 diff --git a/chipset_enable.c b/chipset_enable.c index 259902e..025203c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -601,6 +601,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: reg_name = "BIOS_SPI_BC"; gcs = pci_read_long(dev, 0xdc); bild = (gcs >> 7) & 1; @@ -699,6 +700,7 @@ boot_straps = boot_straps_pch8_lp; break; case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: boot_straps = boot_straps_apl; break; case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet @@ -726,6 +728,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: bbs = (gcs >> 6) & 0x1; break; default: @@ -976,6 +979,11 @@ return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); } +static int enable_flash_glk(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_GEMINI_LAKE); +} + /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately. * @@ -2076,6 +2084,7 @@ {0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100}, {0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, {0x8086, 0x5af0, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, + {0x8086, 0x31e8, B_S, DEP, "Intel", "Gemini Lake", enable_flash_glk}, {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300}, {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300}, {0x8086, 0xa305, B_S, NT, "Intel", "Z390", enable_flash_pch300}, diff --git a/ich_descriptors.c b/ich_descriptors.c index 7374984..c5f9f82 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -39,6 +39,7 @@ { switch (cs) { case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: return 6; case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: @@ -68,6 +69,7 @@ switch (cs) { case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: if (cont->NM <= MAX_NUM_MASTERS) return cont->NM; break; @@ -104,7 +106,7 @@ "5 series Ibex Peak", "6 series Cougar Point", "7 series Panther Point", "8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg", "9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point", - "C620 series Lewisburg", "300 series Cannon Point", "Apollo Lake", + "C620 series Lewisburg", "300 series Cannon Point", "Apollo Lake", "Gemini Lake", }; if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names)) cs = 0; @@ -198,7 +200,8 @@ case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: - case CHIPSET_APOLLO_LAKE: { + case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: { uint8_t size_enc; if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; @@ -269,6 +272,7 @@ case CHIPSET_400_SERIES_COMET_POINT: return freq_str[1][value]; case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: return freq_str[2][value]; case CHIPSET_ICH_UNKNOWN: default: @@ -286,6 +290,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: has_flill1 = true; break; default: @@ -462,7 +467,7 @@ desc->master.mstr[i].write & (1 << j) ? 'w' : ' '); msg_pdbg2("\n"); } - } else if (cs == CHIPSET_APOLLO_LAKE) { + } else if (cs == CHIPSET_APOLLO_LAKE || cs == CHIPSET_GEMINI_LAKE) { const char *const master_names[] = { "BIOS", "TXE", }; if (nm > (ssize_t)ARRAY_SIZE(master_names)) { msg_pdbg2("%s: number of masters too high (%d).\n", __func__, desc->content.NM); @@ -922,7 +927,9 @@ else if (content->ISL <= 16) return CHIPSET_5_SERIES_IBEX_PEAK; else if (content->FLMAP2 == 0) { - if (content->ISL != 19) + if (content->ISL == 23) + return CHIPSET_GEMINI_LAKE; + else if (content->ISL != 19) msg_pwarn("Peculiar firmware descriptor, assuming Apollo Lake compatibility.\n"); return CHIPSET_APOLLO_LAKE; } @@ -967,6 +974,7 @@ switch (guess) { case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: + case CHIPSET_GEMINI_LAKE: /* `freq_read` was repurposed, so can't check on it any more. */ return guess; case CHIPSET_100_SERIES_SUNRISE_POINT: @@ -1123,6 +1131,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; } else { @@ -1159,6 +1168,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: mmio_le_writel(control, spibar + PCH100_REG_FDOC); return mmio_le_readl(spibar + PCH100_REG_FDOD); default: diff --git a/ich_descriptors.h b/ich_descriptors.h index c6bf5d8..727a31b 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -257,7 +257,7 @@ struct ich_desc_south_strap { union { - uint32_t STRPs[18]; /* current maximum: cougar point */ + uint32_t STRPs[23]; /* current maximum: gemini lake */ struct { /* ich8 */ struct { /* STRP1 */ uint32_t ME_DISABLE :1, diff --git a/ichspi.c b/ichspi.c index e45b39a..83920b4 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1740,6 +1740,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: num_pr = 6; /* Includes GPR0 */ reg_pr0 = PCH100_REG_FPR0; swseq_data.reg_ssfsc = PCH100_REG_SSFSC; @@ -1772,6 +1773,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: num_freg = 16; break; default: @@ -1868,6 +1870,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: tmp = mmio_readl(spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); prettyprint_pch100_reg_dlock(tmp); @@ -1943,6 +1946,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: case CHIPSET_BAYTRAIL: break; default: @@ -1976,6 +1980,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: break; default: tmp = mmio_readl(spibar + ICH9_REG_FPB); @@ -2012,8 +2017,10 @@ ich_spi_mode = ich_hwseq; } - if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_APOLLO_LAKE) { - msg_pdbg("Enabling hardware sequencing by default for Apollo Lake.\n"); + if (ich_spi_mode == ich_auto && + (ich_gen == CHIPSET_APOLLO_LAKE || + ich_gen == CHIPSET_GEMINI_LAKE)) { + msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini Lake.\n"); ich_spi_mode = ich_hwseq; } diff --git a/programmer.h b/programmer.h index 675a259..7124611 100644 --- a/programmer.h +++ b/programmer.h @@ -672,6 +672,7 @@ CHIPSET_300_SERIES_CANNON_POINT, CHIPSET_APOLLO_LAKE, CHIPSET_400_SERIES_COMET_POINT, + CHIPSET_GEMINI_LAKE, }; /* ichspi.c */ diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 32eea12..bfeedc1 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -127,6 +127,7 @@ "\t- \"ich10\",\n" "\t- \"silvermont\" for chipsets from Intel's Silvermont architecture (e.g. Bay Trail),\n" "\t- \"apollo\" for Intel's Apollo Lake SoC.\n" +"\t- \"gemini\" for Intel's Gemini Lake SoC.\n" "\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" @@ -230,6 +231,8 @@ cs = CHIPSET_400_SERIES_COMET_POINT; else if (strcmp(csn, "apollo") == 0) cs = CHIPSET_APOLLO_LAKE; + else if (strcmp(csn, "gemini") == 0) + cs = CHIPSET_GEMINI_LAKE; } ret = read_ich_descriptors_from_dump(buf, len, &cs, &desc); -- To view, visit https://review.coreboot.org/c/flashrom/+/54276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77 Gerrit-Change-Number: 54276 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: Free `chip` instance when tearing down a flash context
by Angel Pons (Code Review) 13 May '21

13 May '21

Attention is currently required from: Nico Huber. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/33546 ) Change subject: Free `chip` instance when tearing down a flash context ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/flashrom/+/33546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I761d7e167a43e5bf08b5b3d269b0a476e3d343c5 Gerrit-Change-Number: 33546 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 13 May 2021 11:27:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: layout: Make `struct layout_include_args` private to `layout.c`
by Angel Pons (Code Review) 13 May '21

13 May '21

Attention is currently required from: Nico Huber. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/33545 ) Change subject: layout: Make `struct layout_include_args` private to `layout.c` ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/33545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Icbfee68e85429fe41db1cad6b99f25e9f30cd672 Gerrit-Change-Number: 33545 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 13 May 2021 11:26:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: layout: Use linked list for `struct romentry`
by Angel Pons (Code Review) 13 May '21

13 May '21

Attention is currently required from: Nico Huber. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/33521 ) Change subject: layout: Use linked list for `struct romentry` ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/33521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I60a0aa1007ebcd5eb401db116f835d129b3e9732 Gerrit-Change-Number: 33521 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 13 May 2021 11:25:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: libflashrom: clear layout on flashrom_layout_release
by Nico Huber (Code Review) 13 May '21

13 May '21

Attention is currently required from: Angel Pons, Daniel Campello, Peter Marheine. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54147 ) Change subject: libflashrom: clear layout on flashrom_layout_release ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/54147/comment/459f85b0_cd5e4f6f PS3, Line 7: libflashrom > The global layout is a CLI artifact and shouldn't be accessible […] Should have grepped first, it did change. Better to get rid of these hacks, though. -- To view, visit https://review.coreboot.org/c/flashrom/+/54147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8ba4b356f2a40ccbfd4e91f81af01d5f6a6de515 Gerrit-Change-Number: 54147 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Daniel Campello <campello(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Daniel Campello <campello(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Thu, 13 May 2021 11:25:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in flashrom[master]: Pass layout directly to verify_by_layout()
by Angel Pons (Code Review) 13 May '21

13 May '21

Attention is currently required from: Nico Huber. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/33520 ) Change subject: Pass layout directly to verify_by_layout() ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/33520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id496deec85c18bdfe968df6a798b626eb9cfbed5 Gerrit-Change-Number: 33520 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 13 May 2021 11:23:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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