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Change subject: flashchips.c: add support for W25Q32JW...M
......................................................................
Patch Set 6: Code-Review+2
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Change subject: flashchips: change chip name from 'W25Q64JW' to 'W25Q64JW...M'
......................................................................
Patch Set 1: Code-Review+2
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Change subject: stlinkv3_spi.c: Clean up properly on all init error paths
......................................................................
Patch Set 2: Code-Review+2
(2 comments)
Patchset:
PS2:
LGTM and thanks for the cleanup!
File stlinkv3_spi.c:
https://review.coreboot.org/c/flashrom/+/54190/comment/a207fe85_b9f64707
PS1, Line 443: stlinkv3_command(command, sizeof(command), answer, sizeof(answer), "STLINK_BRIDGE_CLOSE");
> Oh yes, there is a STLINK_BRIDGE_INIT_SPI in stlinkv3_spi_open(), maybe it is? […]
Hello Anastasia,
First of all: many thanks for cleaning out my crappy code!
Yes the STLINK_BRIDGE_CLOSE is complementary to the STLINK_BRIDGE_INIT_SPI.
Tldr: there are multiple bridge subsystems (I2C, CAN, GPIO) on the device and they could be closed with the STLINK_BRIDGE_CLOSE command with bridge subsystem specified by the command[2] "argument". However opening is done with separate commands (STLINK_BRIDGE_INIT_SPI/CAN/GPIO).
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons,
I'd like you to reexamine a change. Please visit
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Change subject: flashchips.c: merge GD25B128B/GD25Q128B and GD25Q127C/GD25Q128C
......................................................................
flashchips.c: merge GD25B128B/GD25Q128B and GD25Q127C/GD25Q128C
The 'B' and 'C' revisions have the same vendor ID / device ID and are
mostly identical. Other than the names, the only difference between
the definitions was that the 'C' definition had FEATURE_QPI enabled and
the 'B' definition did not.
This difference appears to be a result of the 'B' definition predating
the the FEATURE_QPI feature bit and the 'C' definition being added
later. The 'B' chips also support QPI, so the merged definition has
FEATURE_QPI enabled.
Merging the entries allows flashrom to automatically identify the chip
without needing to be given the chip with the -C flag.
Chip revision history:
- The 'GD25B128B/GD25Q128B' was originally added as 'GD25Q128' in
`commit 1525b2ad16e07f035b1de70fadd05a7018ea5756` and later revised to
'GD25Q128B' and then 'GD25B128B/GD25Q128B'.
- The 'GD25Q127C/GD25Q128C' definition was added in
`commit e0c7abf219b81ad049d09a4671ebc9196153d308` as 'GD25Q128C' and
later renamed to 'GD25Q127C/GD25Q128C'
BUG=b:153598437
BRANCH=none
TEST=builds
Change-Id: I688f2e15aef61afbec728a9a81094bee56d6fbfa
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flashchips.c
1 file changed, 6 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/52883/2
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Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/53946 )
Change subject: flashchips.c: add support for W25Q32JW...M
......................................................................
Patch Set 6:
(2 comments)
File flashchips.h:
https://review.coreboot.org/c/flashrom/+/53946/comment/b139f071_2307b16a
PS6, Line 980: _M
_M added here to match the part name. Subsequent patch makes the 64Mb chip consistent.
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/53946/comment/a57f63e3_7800ffbd
PS6, Line 17583: W25Q32JW...M
I've changed the chip's name since I realized that 'IM' is not the only matching suffix, and there are also 'JW' parts with the same device ID.
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Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54291 )
Change subject: flashchips: change chip name from 'W25Q64JW' to 'W25Q64JW...M'
......................................................................
flashchips: change chip name from 'W25Q64JW' to 'W25Q64JW...M'
According to the W25Q64JW datasheet rev. E, only devices ending with the
letter 'M' have a device ID of 8017h. There are other variants with
different device IDs. This patch makes the 'W25Q64JW...M' definition
consistent with the 'W25Q32JW...M' definition.
The device ID macro defined in flashchips.h has also been renamed from
WINBOND_NEX_W25Q64JW to WINBOND_NEX_W25Q64JW_M.
BUG=b:166294558
BRANCH=none
TEST=builds
Change-Id: Ib0dc914da286a191d22e666332b1063b88db4251
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flashchips.c
M flashchips.h
2 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/91/54291/1
diff --git a/flashchips.c b/flashchips.c
index 1b281aa..ef5ea5e 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -17860,10 +17860,10 @@
{
.vendor = "Winbond",
- .name = "W25Q64JW",
+ .name = "W25Q64JW...M",
.bustype = BUS_SPI,
.manufacture_id = WINBOND_NEX_ID,
- .model_id = WINBOND_NEX_W25Q64JW,
+ .model_id = WINBOND_NEX_W25Q64JW_M,
.total_size = 8192,
.page_size = 256,
/* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
diff --git a/flashchips.h b/flashchips.h
index 4bbaef1..37eadb2 100644
--- a/flashchips.h
+++ b/flashchips.h
@@ -978,7 +978,7 @@
#define WINBOND_NEX_W25Q128_V_M 0x7018 /* W25Q128JVSM */
#define WINBOND_NEX_W25Q256JV_M 0x7019 /* W25Q256JV_M (QE=0) */
#define WINBOND_NEX_W25Q32JW_M 0x8016 /* W25Q32JW...M */
-#define WINBOND_NEX_W25Q64JW 0x8017
+#define WINBOND_NEX_W25Q64JW_M 0x8017 /* W25Q64JW...M */
#define WINBOND_NEX_W25Q128_DTR 0x8018 /* W25Q128JW_DTR */
#define WINBOND_NEX_W25Q256_DTR 0x8019 /* W25Q256JW_DTR aka W25Q256256JW-IM */
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Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons,
I'd like you to reexamine a change. Please visit
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Change subject: flashchips.c: add support for W25Q32JW...M
......................................................................
flashchips.c: add support for W25Q32JW...M
The chip was added to cros flashrom in
`commit 1fc77dd1ee27a5d6e58a82c6ed6ed390a15372d7`.
Quoting from the commit message:
> We have varied the correct chip name is reported as well as
> write and read 16MBytes of random data and verified the checksum's match.
> Further, --wp-list appears to report the correct ranges.
>
> BUG=b:130199963
> BRANCH=none
> TEST=Ran flashrom with a Dediprog SF100, RW random data and checksum matched.
Change-Id: I7425e12658dd69c4ec8d3309dd591d09a935bb4d
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flashchips.c
M flashchips.h
2 files changed, 39 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/46/53946/6
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54190 )
Change subject: stlinkv3_spi.c: Clean up properly on all init error paths
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/54190/comment/4c432dc4_766d7459
PS1, Line 7: Cleanup
> nit: The verb form has a space: `clean up`
Done
File stlinkv3_spi.c:
https://review.coreboot.org/c/flashrom/+/54190/comment/ff432a60_4e4d8e6e
PS1, Line 443: stlinkv3_command(command, sizeof(command), answer, sizeof(answer), "STLINK_BRIDGE_CLOSE");
> Looks like this might be complementary to stlinkv3_spi_open(), but I'm not sure.
Oh yes, there is a STLINK_BRIDGE_INIT_SPI in stlinkv3_spi_open(), maybe it is?
I think Miklós knows the answer! :)
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Hello build bot (Jenkins), Nico Huber, Miklós Márton, Miklós Márton, Edward O'Callaghan, Angel Pons,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: stlinkv3_spi.c: Clean up properly on all init error paths
......................................................................
stlinkv3_spi.c: Clean up properly on all init error paths
Do a cleanup: close handle and exit usb context in cases when init
fails.
If register_spi_master() fails, going to err_exit cleanup is not
needed because at that point shutdown function has already been
registered and it does the job.
BUG=b:185191942
TEST=builds
Change-Id: I9fabf48068635593bc86006c9642d8569eee8447
Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org>
---
M stlinkv3_spi.c
1 file changed, 7 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/90/54190/2
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