May 2021 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: par_masters: Reshuffle to remove forward declarations
by Edward O'Callaghan (Code Review) 24 May '21

24 May '21

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54873 ) Change subject: par_masters: Reshuffle to remove forward declarations ...................................................................... par_masters: Reshuffle to remove forward declarations Dispense with all these forward declarations by way of ordering. Just deal with all the par_masters in one go to be over and done with. BUG=none BRANCH=none TEST=builds Change-Id: I88e89992380195fee7c9de7ec57502ab980ec5df Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M atahpt.c M atapromise.c M atavia.c M gfxnvidia.c M it8212.c M nic3com.c M nicintel.c M nicnatsemi.c M nicrealtek.c M satamv.c M satasii.c 11 files changed, 258 insertions(+), 293 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/54873/1 diff --git a/atahpt.c b/atahpt.c index 620e894..327d74b 100644 --- a/atahpt.c +++ b/atahpt.c @@ -40,9 +40,19 @@ }; static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr); + chipaddr addr) +{ + OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + OUTB(val, io_base_addr + BIOS_ROM_DATA); +} + static uint8_t atahpt_chip_readb(const struct flashctx *flash, - const chipaddr addr); + const chipaddr addr) +{ + OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + return INB(io_base_addr + BIOS_ROM_DATA); +} + static const struct par_master par_master_atahpt = { .chip_readb = atahpt_chip_readb, .chip_readw = fallback_chip_readw, @@ -80,20 +90,6 @@ return 0; } -static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr) -{ - OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); - OUTB(val, io_base_addr + BIOS_ROM_DATA); -} - -static uint8_t atahpt_chip_readb(const struct flashctx *flash, - const chipaddr addr) -{ - OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); - return INB(io_base_addr + BIOS_ROM_DATA); -} - #else #error PCI port I/O access is not supported on this architecture yet. #endif diff --git a/atapromise.c b/atapromise.c index f32bdb4..4941a7c 100644 --- a/atapromise.c +++ b/atapromise.c @@ -53,20 +53,6 @@ {0}, }; -static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); -static uint8_t atapromise_chip_readb(const struct flashctx *flash, const chipaddr addr); - -static const struct par_master par_master_atapromise = { - .chip_readb = atapromise_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = atapromise_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, -}; - void *atapromise_map(const char *descr, uintptr_t phys_addr, size_t len) { /* In case fallback_map ever returns something other than NULL. */ @@ -106,6 +92,32 @@ } } +static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) +{ + uint32_t data; + + atapromise_limit_chip(flash->chip); + data = (rom_base_addr + (addr & ADDR_MASK)) << 8 | val; + OUTL(data, io_base_addr + 0x14); +} + +static uint8_t atapromise_chip_readb(const struct flashctx *flash, const chipaddr addr) +{ + atapromise_limit_chip(flash->chip); + return pci_mmio_readb(atapromise_bar + (addr & ADDR_MASK)); +} + +static const struct par_master par_master_atapromise = { + .chip_readb = atapromise_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = atapromise_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + int atapromise_init(void) { struct pci_dev *dev = NULL; @@ -150,21 +162,6 @@ return 0; } -static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) -{ - uint32_t data; - - atapromise_limit_chip(flash->chip); - data = (rom_base_addr + (addr & ADDR_MASK)) << 8 | val; - OUTL(data, io_base_addr + 0x14); -} - -static uint8_t atapromise_chip_readb(const struct flashctx *flash, const chipaddr addr) -{ - atapromise_limit_chip(flash->chip); - return pci_mmio_readb(atapromise_bar + (addr & ADDR_MASK)); -} - #else #error PCI port I/O access is not supported on this architecture yet. #endif diff --git a/atavia.c b/atavia.c index e04950a..8045e1b 100644 --- a/atavia.c +++ b/atavia.c @@ -54,19 +54,6 @@ {0}, }; -static void atavia_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); -static uint8_t atavia_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_master lpc_master_atavia = { - .chip_readb = atavia_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = atavia_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, -}; - static void *atavia_offset = NULL; static struct pci_dev *dev = NULL; @@ -119,6 +106,43 @@ return (atavia_offset != 0) ? atavia_offset : (void *)phys_addr; } +static void atavia_chip_writeb(const struct flashctx *flash, uint8_t val, const chipaddr addr) +{ + msg_pspew("%s: 0x%02x to 0x%*" PRIxPTR ".\n", __func__, val, PRIxPTR_WIDTH, addr); + pci_write_long(dev, BROM_ADDR, (addr & ~3)); + pci_write_long(dev, BROM_DATA, val << BYTE_OFFSET(addr)); + pci_write_byte(dev, BROM_ACCESS, BROM_TRIGGER | BROM_WRITE | ENABLE_BYTE(addr)); + + if (!atavia_ready(dev)) { + msg_perr("not ready after write\n"); + } +} + +static uint8_t atavia_chip_readb(const struct flashctx *flash, const chipaddr addr) +{ + pci_write_long(dev, BROM_ADDR, (addr & ~3)); + pci_write_byte(dev, BROM_ACCESS, BROM_TRIGGER | ENABLE_BYTE(addr)); + + if (!atavia_ready(dev)) { + msg_perr("not ready after read\n"); + } + + uint8_t val = (pci_read_long(dev, BROM_DATA) >> BYTE_OFFSET(addr)) & 0xff; + msg_pspew("%s: 0x%02x from 0x%*" PRIxPTR ".\n", __func__, val, PRIxPTR_WIDTH, addr); + return val; +} + +static const struct par_master lpc_master_atavia = { + .chip_readb = atavia_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = atavia_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + int atavia_init(void) { char *arg = extract_programmer_param("offset"); @@ -164,29 +188,3 @@ return 0; } - -static void atavia_chip_writeb(const struct flashctx *flash, uint8_t val, const chipaddr addr) -{ - msg_pspew("%s: 0x%02x to 0x%*" PRIxPTR ".\n", __func__, val, PRIxPTR_WIDTH, addr); - pci_write_long(dev, BROM_ADDR, (addr & ~3)); - pci_write_long(dev, BROM_DATA, val << BYTE_OFFSET(addr)); - pci_write_byte(dev, BROM_ACCESS, BROM_TRIGGER | BROM_WRITE | ENABLE_BYTE(addr)); - - if (!atavia_ready(dev)) { - msg_perr("not ready after write\n"); - } -} - -static uint8_t atavia_chip_readb(const struct flashctx *flash, const chipaddr addr) -{ - pci_write_long(dev, BROM_ADDR, (addr & ~3)); - pci_write_byte(dev, BROM_ACCESS, BROM_TRIGGER | ENABLE_BYTE(addr)); - - if (!atavia_ready(dev)) { - msg_perr("not ready after read\n"); - } - - uint8_t val = (pci_read_long(dev, BROM_DATA) >> BYTE_OFFSET(addr)) & 0xff; - msg_pspew("%s: 0x%02x from 0x%*" PRIxPTR ".\n", __func__, val, PRIxPTR_WIDTH, addr); - return val; -} diff --git a/gfxnvidia.c b/gfxnvidia.c index fe6f982..6b1efcf 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -59,9 +59,17 @@ }; static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr); + chipaddr addr) +{ + pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); +} + static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash, - const chipaddr addr); + const chipaddr addr) +{ + return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); +} + static const struct par_master par_master_gfxnvidia = { .chip_readb = gfxnvidia_chip_readb, .chip_readw = fallback_chip_readw, @@ -107,15 +115,3 @@ return 0; } - -static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr) -{ - pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); -} - -static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash, - const chipaddr addr) -{ - return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); -} diff --git a/it8212.c b/it8212.c index 2f2d43e..7c66a59 100644 --- a/it8212.c +++ b/it8212.c @@ -32,8 +32,16 @@ #define IT8212_MEMMAP_SIZE (128 * 1024) #define IT8212_MEMMAP_MASK (IT8212_MEMMAP_SIZE - 1) -static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); -static uint8_t it8212_chip_readb(const struct flashctx *flash, const chipaddr addr); +static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) +{ + pci_mmio_writeb(val, it8212_bar + (addr & IT8212_MEMMAP_MASK)); +} + +static uint8_t it8212_chip_readb(const struct flashctx *flash, const chipaddr addr) +{ + return pci_mmio_readb(it8212_bar + (addr & IT8212_MEMMAP_MASK)); +} + static const struct par_master par_master_it8212 = { .chip_readb = it8212_chip_readb, .chip_readw = fallback_chip_readw, @@ -70,13 +78,3 @@ register_par_master(&par_master_it8212, BUS_PARALLEL, NULL); return 0; } - -static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) -{ - pci_mmio_writeb(val, it8212_bar + (addr & IT8212_MEMMAP_MASK)); -} - -static uint8_t it8212_chip_readb(const struct flashctx *flash, const chipaddr addr) -{ - return pci_mmio_readb(it8212_bar + (addr & IT8212_MEMMAP_MASK)); -} diff --git a/nic3com.c b/nic3com.c index 6ff91e7..d60b03c 100644 --- a/nic3com.c +++ b/nic3com.c @@ -54,9 +54,19 @@ }; static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr); + chipaddr addr) +{ + OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + OUTB(val, io_base_addr + BIOS_ROM_DATA); +} + static uint8_t nic3com_chip_readb(const struct flashctx *flash, - const chipaddr addr); + const chipaddr addr) +{ + OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + return INB(io_base_addr + BIOS_ROM_DATA); +} + static const struct par_master par_master_nic3com = { .chip_readb = nic3com_chip_readb, .chip_readw = fallback_chip_readw, @@ -125,20 +135,6 @@ return 0; } -static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr) -{ - OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); - OUTB(val, io_base_addr + BIOS_ROM_DATA); -} - -static uint8_t nic3com_chip_readb(const struct flashctx *flash, - const chipaddr addr) -{ - OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); - return INB(io_base_addr + BIOS_ROM_DATA); -} - #else #error PCI port I/O access is not supported on this architecture yet. #endif diff --git a/nicintel.c b/nicintel.c index afd2682..3d324da 100644 --- a/nicintel.c +++ b/nicintel.c @@ -41,9 +41,17 @@ #define CSR_FCR 0x0c static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr); + chipaddr addr) +{ + pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); +} + static uint8_t nicintel_chip_readb(const struct flashctx *flash, - const chipaddr addr); + const chipaddr addr) +{ + return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); +} + static const struct par_master par_master_nicintel = { .chip_readb = nicintel_chip_readb, .chip_readw = fallback_chip_readw, @@ -103,15 +111,3 @@ return 0; } - -static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr) -{ - pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); -} - -static uint8_t nicintel_chip_readb(const struct flashctx *flash, - const chipaddr addr) -{ - return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); -} diff --git a/nicnatsemi.c b/nicnatsemi.c index 77b5440..56297fe 100644 --- a/nicnatsemi.c +++ b/nicnatsemi.c @@ -35,9 +35,35 @@ }; static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr); + chipaddr addr) +{ + OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR); + /* + * The datasheet requires 32 bit accesses to this register, but it seems + * that requirement might only apply if the register is memory mapped. + * Bits 8-31 of this register are apparently don't care, and if this + * register is I/O port mapped, 8 bit accesses to the lowest byte of the + * register seem to work fine. Due to that, we ignore the advice in the + * data sheet. + */ + OUTB(val, io_base_addr + BOOT_ROM_DATA); +} + static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash, - const chipaddr addr); + const chipaddr addr) +{ + OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR); + /* + * The datasheet requires 32 bit accesses to this register, but it seems + * that requirement might only apply if the register is memory mapped. + * Bits 8-31 of this register are apparently don't care, and if this + * register is I/O port mapped, 8 bit accesses to the lowest byte of the + * register seem to work fine. Due to that, we ignore the advice in the + * data sheet. + */ + return INB(io_base_addr + BOOT_ROM_DATA); +} + static const struct par_master par_master_nicnatsemi = { .chip_readb = nicnatsemi_chip_readb, .chip_readw = fallback_chip_readw, @@ -76,36 +102,6 @@ return 0; } -static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr) -{ - OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR); - /* - * The datasheet requires 32 bit accesses to this register, but it seems - * that requirement might only apply if the register is memory mapped. - * Bits 8-31 of this register are apparently don't care, and if this - * register is I/O port mapped, 8 bit accesses to the lowest byte of the - * register seem to work fine. Due to that, we ignore the advice in the - * data sheet. - */ - OUTB(val, io_base_addr + BOOT_ROM_DATA); -} - -static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash, - const chipaddr addr) -{ - OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR); - /* - * The datasheet requires 32 bit accesses to this register, but it seems - * that requirement might only apply if the register is memory mapped. - * Bits 8-31 of this register are apparently don't care, and if this - * register is I/O port mapped, 8 bit accesses to the lowest byte of the - * register seem to work fine. Due to that, we ignore the advice in the - * data sheet. - */ - return INB(io_base_addr + BOOT_ROM_DATA); -} - #else #error PCI port I/O access is not supported on this architecture yet. #endif diff --git a/nicrealtek.c b/nicrealtek.c index 2208179..788c088 100644 --- a/nicrealtek.c +++ b/nicrealtek.c @@ -35,8 +35,44 @@ {0}, }; -static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); -static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr); +static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) +{ + /* Output addr and data, set WE to 0, set OE to 1, set CS to 0, + * enable software access. + */ + OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24), + io_base_addr + bios_rom_addr); + /* Output addr and data, set WE to 1, set OE to 1, set CS to 1, + * enable software access. + */ + OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24), + io_base_addr + bios_rom_addr); +} + +static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr) +{ + uint8_t val; + + /* FIXME: Can we skip reading the old data and simply use 0? */ + /* Read old data. */ + val = INB(io_base_addr + bios_rom_data); + /* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0, + * enable software access. + */ + OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24), + io_base_addr + bios_rom_addr); + + /* Read new data. */ + val = INB(io_base_addr + bios_rom_data); + /* Output addr and new data, set WE to 1, set OE to 1, set CS to 1, + * enable software access. + */ + OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24), + io_base_addr + bios_rom_addr); + + return val; +} + static const struct par_master par_master_nicrealtek = { .chip_readb = nicrealtek_chip_readb, .chip_readw = fallback_chip_readw, @@ -91,44 +127,6 @@ return 0; } -static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) -{ - /* Output addr and data, set WE to 0, set OE to 1, set CS to 0, - * enable software access. - */ - OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24), - io_base_addr + bios_rom_addr); - /* Output addr and data, set WE to 1, set OE to 1, set CS to 1, - * enable software access. - */ - OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24), - io_base_addr + bios_rom_addr); -} - -static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr) -{ - uint8_t val; - - /* FIXME: Can we skip reading the old data and simply use 0? */ - /* Read old data. */ - val = INB(io_base_addr + bios_rom_data); - /* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0, - * enable software access. - */ - OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24), - io_base_addr + bios_rom_addr); - - /* Read new data. */ - val = INB(io_base_addr + bios_rom_data); - /* Output addr and new data, set WE to 1, set OE to 1, set CS to 1, - * enable software access. - */ - OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24), - io_base_addr + bios_rom_addr); - - return val; -} - #else #error PCI port I/O access is not supported on this architecture yet. #endif diff --git a/satamv.c b/satamv.c index 2640b78..30b7c34 100644 --- a/satamv.c +++ b/satamv.c @@ -38,10 +38,41 @@ #define PCI_BAR2_CONTROL 0x00c08 #define GPIO_PORT_CONTROL 0x104f0 +/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function. + * If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O). + * This code only supports indirect accesses for now. + */ + +/* Indirect access to via the I/O BAR1. */ +static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr) +{ + /* 0x80000000 selects BAR2 for remapping. */ + OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); + OUTB(val, mv_iobar + 0x80 + (addr & 0x3)); +} + +/* Indirect access to via the I/O BAR1. */ +static uint8_t satamv_indirect_chip_readb(const chipaddr addr) +{ + /* 0x80000000 selects BAR2 for remapping. */ + OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); + return INB(mv_iobar + 0x80 + (addr & 0x3)); +} + +/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr); + chipaddr addr) +{ + satamv_indirect_chip_writeb(val, addr); +} + +/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ static uint8_t satamv_chip_readb(const struct flashctx *flash, - const chipaddr addr); + const chipaddr addr) +{ + return satamv_indirect_chip_readb(addr); +} + static const struct par_master par_master_satamv = { .chip_readb = satamv_chip_readb, .chip_readw = fallback_chip_readw, @@ -153,41 +184,6 @@ return 0; } -/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function. - * If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O). - * This code only supports indirect accesses for now. - */ - -/* Indirect access to via the I/O BAR1. */ -static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr) -{ - /* 0x80000000 selects BAR2 for remapping. */ - OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); - OUTB(val, mv_iobar + 0x80 + (addr & 0x3)); -} - -/* Indirect access to via the I/O BAR1. */ -static uint8_t satamv_indirect_chip_readb(const chipaddr addr) -{ - /* 0x80000000 selects BAR2 for remapping. */ - OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); - return INB(mv_iobar + 0x80 + (addr & 0x3)); -} - -/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ -static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr) -{ - satamv_indirect_chip_writeb(val, addr); -} - -/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ -static uint8_t satamv_chip_readb(const struct flashctx *flash, - const chipaddr addr) -{ - return satamv_indirect_chip_readb(addr); -} - #else #error PCI port I/O access is not supported on this architecture yet. #endif diff --git a/satasii.c b/satasii.c index c9dfdad..0d22650 100644 --- a/satasii.c +++ b/satasii.c @@ -37,19 +37,6 @@ {0}, }; -static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); -static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_master par_master_satasii = { - .chip_readb = satasii_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = satasii_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, -}; - static uint32_t satasii_wait_done(void) { uint32_t ctrl_reg; @@ -64,6 +51,48 @@ return ctrl_reg; } +static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) +{ + uint32_t data_reg; + uint32_t ctrl_reg = satasii_wait_done(); + + /* Mask out unused/reserved bits, set writes and start transaction. */ + ctrl_reg &= 0xfcf80000; + ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); + + data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val; + pci_mmio_writel(data_reg, (sii_bar + 4)); + pci_mmio_writel(ctrl_reg, sii_bar); + + satasii_wait_done(); +} + +static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr) +{ + uint32_t ctrl_reg = satasii_wait_done(); + + /* Mask out unused/reserved bits, set reads and start transaction. */ + ctrl_reg &= 0xfcf80000; + ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); + + pci_mmio_writel(ctrl_reg, sii_bar); + + satasii_wait_done(); + + return (pci_mmio_readl(sii_bar + 4)) & 0xff; +} + +static const struct par_master par_master_satasii = { + .chip_readb = satasii_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = satasii_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + int satasii_init(void) { struct pci_dev *dev = NULL; @@ -104,34 +133,3 @@ return 0; } - -static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) -{ - uint32_t data_reg; - uint32_t ctrl_reg = satasii_wait_done(); - - /* Mask out unused/reserved bits, set writes and start transaction. */ - ctrl_reg &= 0xfcf80000; - ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); - - data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val; - pci_mmio_writel(data_reg, (sii_bar + 4)); - pci_mmio_writel(ctrl_reg, sii_bar); - - satasii_wait_done(); -} - -static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr) -{ - uint32_t ctrl_reg = satasii_wait_done(); - - /* Mask out unused/reserved bits, set reads and start transaction. */ - ctrl_reg &= 0xfcf80000; - ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); - - pci_mmio_writel(ctrl_reg, sii_bar); - - satasii_wait_done(); - - return (pci_mmio_readl(sii_bar + 4)) & 0xff; -} -- To view, visit https://review.coreboot.org/c/flashrom/+/54873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I88e89992380195fee7c9de7ec57502ab980ec5df Gerrit-Change-Number: 54873 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: drkaiser.c: Reshuffle to remove forward declarations
by Edward O'Callaghan (Code Review) 24 May '21

24 May '21

Attention is currently required from: Edward O'Callaghan. Hello build bot (Jenkins), Angel Pons, Anastasia Klimchuk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/54850 to look at the new patch set (#2). Change subject: drkaiser.c: Reshuffle to remove forward declarations ...................................................................... drkaiser.c: Reshuffle to remove forward declarations BUG=none BRANCH=none TEST=builds Change-Id: Iee550dc8055eabfe8c7c4ad32003b6eec4f1e496 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M drkaiser.c 1 file changed, 10 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/50/54850/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/54850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iee550dc8055eabfe8c7c4ad32003b6eec4f1e496 Gerrit-Change-Number: 54850 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: serprog.c: Use braces in both branches of conditional statement
by Angel Pons (Code Review) 24 May '21

24 May '21

Attention is currently required from: Nico Huber, Edward O'Callaghan, Anastasia Klimchuk. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54862 ) Change subject: serprog.c: Use braces in both branches of conditional statement ...................................................................... Patch Set 1: (1 comment) File serprog.c: https://review.coreboot.org/c/flashrom/+/54862/comment/8e460915_b0ee4e7d PS1, Line 876: } else { `else` isn't necessary here. I don't really care, though. -- To view, visit https://review.coreboot.org/c/flashrom/+/54862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4fdccbd66f0351af98811bf7c2d8e15f0a99d852 Gerrit-Change-Number: 54862 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 24 May 2021 09:54:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: serprog.c: Separate shutdown from failed init cleanup
by Angel Pons (Code Review) 24 May '21

24 May '21

Attention is currently required from: Nico Huber, Edward O'Callaghan, Anastasia Klimchuk. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54861 ) Change subject: serprog.c: Separate shutdown from failed init cleanup ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/54861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idf4ed62c19667e18cc807913180c48cb8c978805 Gerrit-Change-Number: 54861 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 24 May 2021 09:53:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: serprog.c: Use braces in both branches of conditional statement
by Angel Pons (Code Review) 24 May '21

24 May '21

Attention is currently required from: Nico Huber, Edward O'Callaghan, Anastasia Klimchuk. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54862 ) Change subject: serprog.c: Use braces in both branches of conditional statement ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/54862/comment/fb8710a5_91ee0edb PS1, Line 9: According to the style guide. Make it a full sentence? As per the coding style, if one branch of a conditional statement needs braces, all other branches need to have braces as well. -- To view, visit https://review.coreboot.org/c/flashrom/+/54862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4fdccbd66f0351af98811bf7c2d8e15f0a99d852 Gerrit-Change-Number: 54862 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 24 May 2021 09:48:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: dummyflasher.c: Extract params processing into a separate function
by Anastasia Klimchuk (Code Review) 24 May '21

24 May '21

Attention is currently required from: Nico Huber, Namyoon Woo, Edward O'Callaghan, Angel Pons. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54748 ) Change subject: dummyflasher.c: Extract params processing into a separate function ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Can you rebase on top of the other series https://review.coreboot. […] Can I do this after the chain submitted? Sure, I will resolve all conflicts, but if I rebase now and then some more changes happen in the chain, I may need to rebase again? -- To view, visit https://review.coreboot.org/c/flashrom/+/54748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I04f55f77bb4703f1d88b2191c45a22be3c97bf87 Gerrit-Change-Number: 54748 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Namyoon Woo <namyoon(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Namyoon Woo <namyoon(a)google.com> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 24 May 2021 05:04:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: serprog.c: Use braces in both branches of conditional statement
by Anastasia Klimchuk (Code Review) 24 May '21

24 May '21

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54862 ) Change subject: serprog.c: Use braces in both branches of conditional statement ...................................................................... serprog.c: Use braces in both branches of conditional statement According to the style guide. BUG=b:185191942 TEST=builds Change-Id: I4fdccbd66f0351af98811bf7c2d8e15f0a99d852 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M serprog.c 1 file changed, 13 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/54862/1 diff --git a/serprog.c b/serprog.c index a70a289..e8c0d75 100644 --- a/serprog.c +++ b/serprog.c @@ -564,8 +564,9 @@ if (baud_str == NULL || *baud_str == '\0') { baud = -1; msg_pdbg("No baudrate specified, using the hardware's defaults.\n"); - } else + } else { baud = atoi(baud_str); // FIXME: replace atoi with strtoul + } if (strlen(device) > 0) { sp_fd = sp_openserport(device, baud); if (sp_fd == SER_INV_FD) { @@ -727,11 +728,11 @@ goto init_err_cleanup_exit; } if (strlen(f_spi_suffix) == 1) { - if (!strcasecmp(f_spi_suffix, "M")) + if (!strcasecmp(f_spi_suffix, "M")) { f_spi_req *= 1000000; - else if (!strcasecmp(f_spi_suffix, "k")) + } else if (!strcasecmp(f_spi_suffix, "k")) { f_spi_req *= 1000; - else { + } else { msg_perr("Error: Garbage following 'spispeed' value.\n"); free(spispeed); goto init_err_cleanup_exit; @@ -747,17 +748,18 @@ buf[2] = (f_spi_req >> (2 * 8)) & 0xFF; buf[3] = (f_spi_req >> (3 * 8)) & 0xFF; - if (sp_check_commandavail(S_CMD_S_SPI_FREQ) == 0) + if (sp_check_commandavail(S_CMD_S_SPI_FREQ) == 0) { msg_pwarn(MSGHEADER "Warning: Setting the SPI clock rate is not supported!\n"); - else if (sp_docommand(S_CMD_S_SPI_FREQ, 4, buf, 4, buf) == 0) { + } else if (sp_docommand(S_CMD_S_SPI_FREQ, 4, buf, 4, buf) == 0) { f_spi = buf[0]; f_spi |= buf[1] << (1 * 8); f_spi |= buf[2] << (2 * 8); f_spi |= buf[3] << (3 * 8); msg_pdbg(MSGHEADER "Requested to set SPI clock frequency to %u Hz. " "It was actually set to %u Hz\n", f_spi_req, f_spi); - } else + } else { msg_pwarn(MSGHEADER "Setting SPI clock rate to %u Hz failed!\n", f_spi_req); + } } free(spispeed); bt = serprog_buses_supported; @@ -871,10 +873,12 @@ if (sp_docommand(S_CMD_S_PIN_STATE, 1, &en, 0, NULL) != 0) { msg_perr("Error: could not enable output buffers\n"); goto init_err_cleanup_exit; - } else + } else { msg_pdbg(MSGHEADER "Output drivers enabled\n"); - } else + } + } else { msg_pdbg(MSGHEADER "Warning: Programmer does not support toggling its output drivers\n"); + } sp_prev_was_write = 0; sp_streamed_transmit_ops = 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/54862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4fdccbd66f0351af98811bf7c2d8e15f0a99d852 Gerrit-Change-Number: 54862 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: serprog.c: Separate shutdown from failed init cleanup
by Anastasia Klimchuk (Code Review) 24 May '21

24 May '21

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54861 ) Change subject: serprog.c: Separate shutdown from failed init cleanup ...................................................................... serprog.c: Separate shutdown from failed init cleanup Shutdown function was covering two different jobs here: 1) the actual shutdown which is run at the end of the driver's lifecycle and 2) cleanup in cases when initialisation failed. Now, shutdown is only doing its main job (#1), and the driver itself is doing cleanup when init fails (#2). The good thing is that now resources are released/closed immediately in cases when init fails (vs shutdown function which was run at some point later), and the driver leaves clean space after itself if init fails. And very importantly this unlocks API change which plans to move register_shutdown inside register master API, see https://review.coreboot.org/c/flashrom/+/51761 BUG=b:185191942 TEST=builds Change-Id: Idf4ed62c19667e18cc807913180c48cb8c978805 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M serprog.c 1 file changed, 27 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/61/54861/1 diff --git a/serprog.c b/serprog.c index e6028aa..a70a289 100644 --- a/serprog.c +++ b/serprog.c @@ -635,33 +635,30 @@ return 1; } - if (register_shutdown(serprog_shutdown, NULL)) - return 1; - msg_pdbg(MSGHEADER "connected - attempting to synchronize\n"); sp_check_avail_automatic = 0; if (sp_synchronize()) - return 1; + goto init_err_cleanup_exit; msg_pdbg(MSGHEADER "Synchronized\n"); if (sp_docommand(S_CMD_Q_IFACE, 0, NULL, 2, &iface)) { msg_perr("Error: NAK to query interface version\n"); - return 1; + goto init_err_cleanup_exit; } if (iface != 1) { msg_perr("Error: Unknown interface version: %d\n", iface); - return 1; + goto init_err_cleanup_exit; } msg_pdbg(MSGHEADER "Interface version ok.\n"); if (sp_docommand(S_CMD_Q_CMDMAP, 0, NULL, 32, sp_cmdmap)) { msg_perr("Error: query command map not supported\n"); - return 1; + goto init_err_cleanup_exit; } sp_check_avail_automatic = 1; @@ -688,10 +685,10 @@ if (sp_check_commandavail(S_CMD_O_SPIOP) == 0) { msg_perr("Error: SPI operation not supported while the " "bustype is SPI\n"); - return 1; + goto init_err_cleanup_exit; } if (sp_docommand(S_CMD_S_BUSTYPE, 1, &bt, 0, NULL)) - return 1; + goto init_err_cleanup_exit; /* Success of any of these commands is optional. We don't need the programmer to tell us its limits, but if it doesn't, we will assume stuff, so it's in the programmers best interest @@ -727,7 +724,7 @@ if (errno != 0 || spispeed == f_spi_suffix) { msg_perr("Error: Could not convert 'spispeed'.\n"); free(spispeed); - return 1; + goto init_err_cleanup_exit; } if (strlen(f_spi_suffix) == 1) { if (!strcasecmp(f_spi_suffix, "M")) @@ -737,12 +734,12 @@ else { msg_perr("Error: Garbage following 'spispeed' value.\n"); free(spispeed); - return 1; + goto init_err_cleanup_exit; } } else if (strlen(f_spi_suffix) > 1) { msg_perr("Error: Garbage following 'spispeed' value.\n"); free(spispeed); - return 1; + goto init_err_cleanup_exit; } buf[0] = (f_spi_req >> (0 * 8)) & 0xFF; @@ -765,38 +762,38 @@ free(spispeed); bt = serprog_buses_supported; if (sp_docommand(S_CMD_S_BUSTYPE, 1, &bt, 0, NULL)) - return 1; + goto init_err_cleanup_exit; } if (serprog_buses_supported & BUS_NONSPI) { if (sp_check_commandavail(S_CMD_O_INIT) == 0) { msg_perr("Error: Initialize operation buffer " "not supported\n"); - return 1; + goto init_err_cleanup_exit; } if (sp_check_commandavail(S_CMD_O_DELAY) == 0) { msg_perr("Error: Write to opbuf: " "delay not supported\n"); - return 1; + goto init_err_cleanup_exit; } /* S_CMD_O_EXEC availability checked later. */ if (sp_check_commandavail(S_CMD_R_BYTE) == 0) { msg_perr("Error: Single byte read not supported\n"); - return 1; + goto init_err_cleanup_exit; } /* This could be translated to single byte reads (if missing), * but now we don't support that. */ if (sp_check_commandavail(S_CMD_R_NBYTES) == 0) { msg_perr("Error: Read n bytes not supported\n"); - return 1; + goto init_err_cleanup_exit; } if (sp_check_commandavail(S_CMD_O_WRITEB) == 0) { msg_perr("Error: Write to opbuf: " "write byte not supported\n"); - return 1; + goto init_err_cleanup_exit; } if (sp_docommand(S_CMD_Q_WRNMAXLEN, 0, NULL, 3, rbuf)) { @@ -815,7 +812,7 @@ if (!sp_write_n_buf) { msg_perr("Error: cannot allocate memory for " "Write-n buffer\n"); - return 1; + goto init_err_cleanup_exit; } sp_write_n_bytes = 0; } @@ -853,12 +850,12 @@ if (sp_check_commandavail(S_CMD_O_EXEC) == 0) { msg_perr("Error: Execute operation buffer not " "supported\n"); - return 1; + goto init_err_cleanup_exit; } if (sp_docommand(S_CMD_O_INIT, 0, NULL, 0, NULL)) { msg_perr("Error: NAK to initialize operation buffer\n"); - return 1; + goto init_err_cleanup_exit; } if (sp_docommand(S_CMD_Q_OPBUF, 0, NULL, 2, @@ -873,20 +870,28 @@ uint8_t en = 1; if (sp_docommand(S_CMD_S_PIN_STATE, 1, &en, 0, NULL) != 0) { msg_perr("Error: could not enable output buffers\n"); - return 1; + goto init_err_cleanup_exit; } else msg_pdbg(MSGHEADER "Output drivers enabled\n"); } else msg_pdbg(MSGHEADER "Warning: Programmer does not support toggling its output drivers\n"); + sp_prev_was_write = 0; sp_streamed_transmit_ops = 0; sp_streamed_transmit_bytes = 0; sp_opbuf_usage = 0; + + if (register_shutdown(serprog_shutdown, NULL)) + goto init_err_cleanup_exit; if (serprog_buses_supported & BUS_SPI) register_spi_master(&spi_master_serprog, NULL); if (serprog_buses_supported & BUS_NONSPI) register_par_master(&par_master_serprog, serprog_buses_supported & BUS_NONSPI, NULL); return 0; + +init_err_cleanup_exit: + serprog_shutdown(NULL); + return 1; } void serprog_delay(unsigned int usecs) -- To view, visit https://review.coreboot.org/c/flashrom/+/54861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idf4ed62c19667e18cc807913180c48cb8c978805 Gerrit-Change-Number: 54861 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: sb600spi.c: Drop sb600_ prefix for spi data struct member
by Edward O'Callaghan (Code Review) 23 May '21

23 May '21

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/54714 ) Change subject: sb600spi.c: Drop sb600_ prefix for spi data struct member ...................................................................... sb600spi.c: Drop sb600_ prefix for spi data struct member The name of the struct type already contains sb600spi_ prefix, so prefix doesn't need to be repeated in members name. BUG=b:185191942 TEST=builds Change-Id: I001ae2044453d1bc205fa253ffb773ed993f57f8 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54714 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M sb600spi.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved diff --git a/sb600spi.c b/sb600spi.c index 32071b9..c057947 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -56,7 +56,7 @@ struct sb600spi_data { struct flashctx *flash; - uint8_t *sb600_spibar; + uint8_t *spibar; }; static int find_smbus_dev_rev(uint16_t vendor, uint16_t device) @@ -207,7 +207,7 @@ unsigned char *readarr) { struct sb600spi_data *sb600_data = flash->mst->spi.data; - uint8_t *sb600_spibar = sb600_data->sb600_spibar; + uint8_t *sb600_spibar = sb600_data->spibar; /* First byte is cmd which can not be sent through the FIFO. */ unsigned char cmd = *writearr++; writecnt--; @@ -295,7 +295,7 @@ unsigned char *readarr) { struct sb600spi_data *sb600_data = flash->mst->spi.data; - uint8_t *sb600_spibar = sb600_data->sb600_spibar; + uint8_t *sb600_spibar = sb600_data->spibar; /* First byte is cmd which can not be sent through the buffer. */ unsigned char cmd = *writearr++; writecnt--; @@ -784,7 +784,7 @@ } data->flash = NULL; - data->sb600_spibar = sb600_spibar; + data->spibar = sb600_spibar; register_shutdown(sb600spi_shutdown, data); -- To view, visit https://review.coreboot.org/c/flashrom/+/54714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I001ae2044453d1bc205fa253ffb773ed993f57f8 Gerrit-Change-Number: 54714 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: sb600spi.c: Make use of new register_spi_master() API
by Edward O'Callaghan (Code Review) 23 May '21

23 May '21

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/54713 ) Change subject: sb600spi.c: Make use of new register_spi_master() API ...................................................................... sb600spi.c: Make use of new register_spi_master() API Pass pointers to dynamically allocated data to register_spi_master(). This way we can avoid mutable globals. BUG=b:185191942 TEST=builds Change-Id: Id555dc5e125309883a816e00afb26d7141fd870d Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54713 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M sb600spi.c 1 file changed, 6 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved diff --git a/sb600spi.c b/sb600spi.c index 80ff0eb..32071b9 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -570,7 +570,7 @@ return 0; } -static struct spi_master spi_master_sb600 = { +static const struct spi_master spi_master_sb600 = { .max_data_read = FIFO_SIZE_OLD, .max_data_write = FIFO_SIZE_OLD - 3, .command = sb600_spi_send_command, @@ -580,7 +580,7 @@ .write_aai = default_spi_write_aai, }; -static struct spi_master spi_master_yangtze = { +static const struct spi_master spi_master_yangtze = { .max_data_read = FIFO_SIZE_YANGTZE - 3, /* Apparently the big SPI 100 buffer is not a ring buffer. */ .max_data_write = FIFO_SIZE_YANGTZE - 3, .command = spi100_spi_send_command, @@ -590,7 +590,7 @@ .write_aai = default_spi_write_aai, }; -static struct spi_master spi_master_promontory = { +static const struct spi_master spi_master_promontory = { .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = FIFO_SIZE_YANGTZE - 3, .command = spi100_spi_send_command, @@ -787,18 +787,14 @@ data->sb600_spibar = sb600_spibar; register_shutdown(sb600spi_shutdown, data); - spi_master_sb600.data = data; - spi_master_yangtze.data = data; - spi_master_promontory.data = data; - /* Starting with Yangtze the SPI controller got a different interface with a much bigger buffer. */ if (amd_gen < CHIPSET_YANGTZE) - register_spi_master(&spi_master_sb600, NULL); + register_spi_master(&spi_master_sb600, data); else if (amd_gen == CHIPSET_YANGTZE) - register_spi_master(&spi_master_yangtze, NULL); + register_spi_master(&spi_master_yangtze, data); else - register_spi_master(&spi_master_promontory, NULL); + register_spi_master(&spi_master_promontory, data); return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/54713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id555dc5e125309883a816e00afb26d7141fd870d Gerrit-Change-Number: 54713 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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