Angel Pons has abandoned this change. ( https://review.coreboot.org/c/flashrom/+/49270 )
Change subject: bitbang_spi.c: Do not set MOSI during initialization
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Abandoned
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Drew Fustini has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/51113 )
Change subject: Add support for GD25LQ256D
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Patch Set 1:
(1 comment)
Patchset:
PS1:
I have to admit this is the first time I've looked at the flashrom source code so I may not be the best person to submit this patch. I can say though that I able able to both write and read a 32MiB binary to this part OK. I put verbose logs of reading and writing successfully to the chip in this gist: https://gist.github.com/pdp7/d3939139c07f76bb2d0bf1294b35db7a Is there additional information that would be useful for me to provide?
Thank you,
Drew
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Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/51401 )
Change subject: chipset_enable.c: Add PCI ID for Comet Lake U Base
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chipset_enable.c: Add PCI ID for Comet Lake U Base
TEST=`flashrom -r` on a kindred chromebook with a Celeron 5205U.
Change-Id: I627dcacdad167343287ac0ec26b47505c2f823ee
Signed-off-by: Sam McNally <sammc(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51401
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M chipset_enable.c
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, approved
Edward O'Callaghan: Looks good to me, approved
diff --git a/chipset_enable.c b/chipset_enable.c
index 138cb12..d5c10c4 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -2020,6 +2020,7 @@
{0x8086, 0x9d58, B_S, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100},
{0x8086, 0x9d84, B_S, DEP, "Intel", "Cannon Lake U Premium", enable_flash_pch300},
{0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400},
+ {0x8086, 0x0285, B_S, DEP, "Intel", "Comet Lake U Base", enable_flash_pch400},
{0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100},
{0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100},
{0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100},
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