February 2021 - flashrom-gerrit

Change in flashrom[master]: chipset_enable: Mark Intel C216 as DEP
by Angel Pons (Code Review) 28 Feb '21

28 Feb '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/flashrom/+/50986 ) Change subject: chipset_enable: Mark Intel C216 as DEP ...................................................................... chipset_enable: Mark Intel C216 as DEP Tested reading and writing internal flash on HP Z220 SFF. Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I97538577c32e6c40374c414f005eb3165ed2e11d Reviewed-on: https://review.coreboot.org/c/flashrom/+/50986 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/chipset_enable.c b/chipset_enable.c index 040b151..138cb12 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1849,7 +1849,7 @@ {0x8086, 0x1e48, B_FS, DEP, "Intel", "Q75", enable_flash_pch7}, {0x8086, 0x1e49, B_FS, DEP, "Intel", "B75", enable_flash_pch7}, {0x8086, 0x1e4a, B_FS, DEP, "Intel", "H77", enable_flash_pch7}, - {0x8086, 0x1e53, B_FS, NT, "Intel", "C216", enable_flash_pch7}, + {0x8086, 0x1e53, B_FS, DEP, "Intel", "C216", enable_flash_pch7}, {0x8086, 0x1e55, B_FS, DEP, "Intel", "QM77", enable_flash_pch7}, {0x8086, 0x1e56, B_FS, DEP, "Intel", "QS77", enable_flash_pch7}, {0x8086, 0x1e57, B_FS, DEP, "Intel", "HM77", enable_flash_pch7}, -- To view, visit https://review.coreboot.org/c/flashrom/+/50986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I97538577c32e6c40374c414f005eb3165ed2e11d Gerrit-Change-Number: 50986 Gerrit-PatchSet: 2 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in flashrom[master]: Add support for GD25LQ256D
by Angel Pons (Code Review) 28 Feb '21

28 Feb '21

Attention is currently required from: Drew Fustini. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/51113 ) Change subject: Add support for GD25LQ256D ...................................................................... Patch Set 1: Code-Review+1 (4 comments) File flashchips.c: https://review.coreboot.org/c/flashrom/+/51113/comment/b601db2c_1ae6cf94 PS1, Line 6718: .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER, Missing FEATURE_QPI? https://review.coreboot.org/c/flashrom/+/51113/comment/3795c395_87728745 PS1, Line 6750: spi_prettyprint_status_register_bp3_srwd According to the datasheet, this should be `spi_prettyprint_status_register_bp4_srwd` instead. https://review.coreboot.org/c/flashrom/+/51113/comment/7654655c_ec5e0ef9 PS1, Line 6751: spi_disable_blockprotect spi_disable_blockprotect_bp4_srwd https://review.coreboot.org/c/flashrom/+/51113/comment/44655ee3_6fe0cd8f PS1, Line 6757: nit: one blank line is enough here -- To view, visit https://review.coreboot.org/c/flashrom/+/51113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If1b745cac070d8deb96ce65137fd9060b148b965 Gerrit-Change-Number: 51113 Gerrit-PatchSet: 1 Gerrit-Owner: Drew Fustini <drew(a)beagleboard.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Drew Fustini <drew(a)beagleboard.org> Gerrit-Comment-Date: Sun, 28 Feb 2021 10:58:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: Add support for GD25LQ256D
by Nico Huber (Code Review) 28 Feb '21

28 Feb '21

Attention is currently required from: Drew Fustini, Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/51113 ) Change subject: Add support for GD25LQ256D ...................................................................... Patch Set 1: Code-Review+2 (3 comments) Patchset: PS1: As the datasheet seems incomplete wrt. 4-byte addressing, it would be nice to leave a TODO comment about that. Also, please upload a verbose log of a write (with changed data) run to `paste.flashrom.org`. File flashchips.c: https://review.coreboot.org/c/flashrom/+/51113/comment/8ef9c63b_bcf769e9 PS1, Line 6719: UNTESTED You can update this to PREW. https://review.coreboot.org/c/flashrom/+/51113/comment/fb174837_aece195a PS1, Line 6726: .block_erase = spi_block_erase_21, This (and the other 4-byte address commands) is not mentioned in the datasheet (rev. 2.0 I found). If flashrom didn't complain, it seems supported, though. -- To view, visit https://review.coreboot.org/c/flashrom/+/51113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If1b745cac070d8deb96ce65137fd9060b148b965 Gerrit-Change-Number: 51113 Gerrit-PatchSet: 1 Gerrit-Owner: Drew Fustini <drew(a)beagleboard.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Drew Fustini <drew(a)beagleboard.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 28 Feb 2021 10:55:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: Add support for GD25LQ256D
by Drew Fustini (Code Review) 28 Feb '21

28 Feb '21

Drew Fustini has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/51113 ) Change subject: Add support for GD25LQ256D ...................................................................... Add support for GD25LQ256D Add support for GD25LQ256D [1]. I have tested both reading and writing complete ROM to this device using FT2232H (Tigard board) [2] connected to the GD25LQ256D on the BeagleV dev board [3]. [1] https://www.gigadevice.com/flash-memory/gd25lq256d/ [2] https://github.com/tigard-tools/tigard [3] https://beagleboard.org/beaglev Suggested-by: Nico Huber <nico.h(a)gmx.de> Change-Id: If1b745cac070d8deb96ce65137fd9060b148b965 Signed-off-by: Drew Fustini <drew(a)beagleboard.org> --- M flashchips.c M flashchips.h 2 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/13/51113/1 diff --git a/flashchips.c b/flashchips.c index 4aaa8ac..920354c 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6709,6 +6709,54 @@ { .vendor = "GigaDevice", + .name = "GD25LQ256D", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25LQ256D, + .total_size = 32768, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp3_srwd, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 2000}, + }, + + + { + .vendor = "GigaDevice", .name = "GD25Q32(B)", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, diff --git a/flashchips.h b/flashchips.h index 2ad09df..1252951 100644 --- a/flashchips.h +++ b/flashchips.h @@ -399,6 +399,7 @@ #define GIGADEVICE_GD25LQ32 0x6016 #define GIGADEVICE_GD25LQ64 0x6017 /* Same as GD25LQ64B (which is faster) */ #define GIGADEVICE_GD25LQ128CD 0x6018 +#define GIGADEVICE_GD25LQ256D 0x6019 #define GIGADEVICE_GD25WQ80E 0x6514 #define GIGADEVICE_GD29GL064CAB 0x7E0601 -- To view, visit https://review.coreboot.org/c/flashrom/+/51113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If1b745cac070d8deb96ce65137fd9060b148b965 Gerrit-Change-Number: 51113 Gerrit-PatchSet: 1 Gerrit-Owner: Drew Fustini <drew(a)beagleboard.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: Add support for Adesto AT25SF128A
by Edward O'Callaghan (Code Review) 28 Feb '21

28 Feb '21

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/51097 ) Change subject: Add support for Adesto AT25SF128A ...................................................................... Add support for Adesto AT25SF128A The following adds support for the Adesto AT25SF128A-SHB-T part. We have varied the correct chip name is reported as well as write and read 16MBytes of random data and verified the checksum's match. Further, --wp-list appears to report the correct ranges. BUG=None BRANCH=none TEST=Ran flashrom with a Dediprog SF100, RW random data and checksum matched. Original-Change-Id: Ic22ca588f33753fdf492e8445324bcc0a809d3e2 Original-Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/1593201 Original-Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator(a)appspot.gserviceaccount.com> Original-Tested-by: Martin Roth <martinroth(a)chromium.org> Original-Reviewed-by: Martin Roth <martinroth(a)chromium.org> (cherry picked from commit 1fa87e058b72a2de1e9127a45e9978361de48479) Note: this does not include the changes made to writeprotect.c in the original patch, as they depend on a large amount of additional writeprotect code that is currently only present in the cros tree, and the intention here is just to reduce the diff in flashchips.c. The `.wp` field has also been removed. Change-Id: I1ce2a6699a1f0116306f668123673a1ba9c932d2 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51097 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M flashchips.c M flashchips.h 2 files changed, 39 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index 6d94a12..4aaa8ac 100644 --- a/flashchips.c +++ b/flashchips.c @@ -2293,6 +2293,44 @@ { .vendor = "Atmel", + .name = "AT25SF128A", + .bustype = BUS_SPI, + .manufacture_id = ATMEL_ID, + .model_id = ATMEL_AT25SF128A, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PR, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp4_srwd, + .unlock = spi_disable_blockprotect_bp4_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Atmel", .name = "AT25SF161", .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, diff --git a/flashchips.h b/flashchips.h index a85fa6a..2ad09df 100644 --- a/flashchips.h +++ b/flashchips.h @@ -152,6 +152,7 @@ #define ATMEL_AT25SF161 0x8601 #define ATMEL_AT25SF321 0x8701 #define ATMEL_AT25SL128A 0x4218 +#define ATMEL_AT25SF128A 0x8901 /* Adesto AT25SF128A */ #define ATMEL_AT26DF041 0x4400 #define ATMEL_AT26DF081 0x4500 /* guessed, no datasheet available */ #define ATMEL_AT26DF081A 0x4501 -- To view, visit https://review.coreboot.org/c/flashrom/+/51097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1ce2a6699a1f0116306f668123673a1ba9c932d2 Gerrit-Change-Number: 51097 Gerrit-PatchSet: 2 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in flashrom[master]: Add support for Adesto AT25SF128A
by Edward O'Callaghan (Code Review) 26 Feb '21

26 Feb '21

Attention is currently required from: Angel Pons, Nikolai Artemiev. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/51097 ) Change subject: Add support for Adesto AT25SF128A ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/51097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1ce2a6699a1f0116306f668123673a1ba9c932d2 Gerrit-Change-Number: 51097 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 26 Feb 2021 05:12:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: Add support for Adesto AT25SF128A
by Nikolai Artemiev (Code Review) 26 Feb '21

26 Feb '21

Attention is currently required from: Edward O'Callaghan. Hello Edward O'Callaghan, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/51097 to review the following change. Change subject: Add support for Adesto AT25SF128A ...................................................................... Add support for Adesto AT25SF128A The following adds support for the Adesto AT25SF128A-SHB-T part. We have varied the correct chip name is reported as well as write and read 16MBytes of random data and verified the checksum's match. Further, --wp-list appears to report the correct ranges. BUG=None BRANCH=none TEST=Ran flashrom with a Dediprog SF100, RW random data and checksum matched. Original-Change-Id: Ic22ca588f33753fdf492e8445324bcc0a809d3e2 Original-Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/1593201 Original-Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator(a)appspot.gserviceaccount.com> Original-Tested-by: Martin Roth <martinroth(a)chromium.org> Original-Reviewed-by: Martin Roth <martinroth(a)chromium.org> (cherry picked from commit 1fa87e058b72a2de1e9127a45e9978361de48479) Note: this does not include the changes made to writeprotect.c in the original patch, as they depend on a large amount of additional writeprotect code that is currently only present in the cros tree, and the intention here is just to reduce the diff in flashchips.c. The `.wp` field has also been removed. Change-Id: I1ce2a6699a1f0116306f668123673a1ba9c932d2 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M flashchips.c M flashchips.h 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/97/51097/1 diff --git a/flashchips.c b/flashchips.c index 6d94a12..4aaa8ac 100644 --- a/flashchips.c +++ b/flashchips.c @@ -2293,6 +2293,44 @@ { .vendor = "Atmel", + .name = "AT25SF128A", + .bustype = BUS_SPI, + .manufacture_id = ATMEL_ID, + .model_id = ATMEL_AT25SF128A, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PR, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp4_srwd, + .unlock = spi_disable_blockprotect_bp4_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Atmel", .name = "AT25SF161", .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, diff --git a/flashchips.h b/flashchips.h index a85fa6a..2ad09df 100644 --- a/flashchips.h +++ b/flashchips.h @@ -152,6 +152,7 @@ #define ATMEL_AT25SF161 0x8601 #define ATMEL_AT25SF321 0x8701 #define ATMEL_AT25SL128A 0x4218 +#define ATMEL_AT25SF128A 0x8901 /* Adesto AT25SF128A */ #define ATMEL_AT26DF041 0x4400 #define ATMEL_AT26DF081 0x4500 /* guessed, no datasheet available */ #define ATMEL_AT26DF081A 0x4501 -- To view, visit https://review.coreboot.org/c/flashrom/+/51097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1ce2a6699a1f0116306f668123673a1ba9c932d2 Gerrit-Change-Number: 51097 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: Add AT25DF011
by Hanno Heinrichs (Code Review) 23 Feb '21

23 Feb '21

Hanno Heinrichs has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/51048 ) Change subject: flashchips: Add AT25DF011 ...................................................................... flashchips: Add AT25DF011 Signed-off-by: Hanno Heinrichs <hanno.heinrichs(a)rwth-aachen.de> Change-Id: I5a2141f1380e864c843d6a3008fdb02dc1b75131 --- M flashchips.c M flashchips.h 2 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/48/51048/1 diff --git a/flashchips.c b/flashchips.c index 6d94a12..407a7fc 100644 --- a/flashchips.c +++ b/flashchips.c @@ -1484,6 +1484,45 @@ { .vendor = "Atmel", + .name = "AT25DF011", + .bustype = BUS_SPI, + .manufacture_id = ATMEL_ID, + .model_id = ATMEL_AT25DF011, + .total_size = 128, + .page_size = 256, + /* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_at25df, + .unlock = spi_disable_blockprotect_at2x_global_unprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, /* 2.3-3.6V & 2.7-3.6V models available */ + }, + + { + .vendor = "Atmel", .name = "AT25DF021", .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, diff --git a/flashchips.h b/flashchips.h index a85fa6a..94d2aaf 100644 --- a/flashchips.h +++ b/flashchips.h @@ -127,6 +127,7 @@ #define AMIC_A49LF040A 0x9d #define ATMEL_ID 0x1F /* Atmel (now used by Adesto) */ +#define ATMEL_AT25DF011 0x4200 #define ATMEL_AT25DF021 0x4300 #define ATMEL_AT25DF021A 0x4301 #define ATMEL_AT25DF041A 0x4401 -- To view, visit https://review.coreboot.org/c/flashrom/+/51048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5a2141f1380e864c843d6a3008fdb02dc1b75131 Gerrit-Change-Number: 51048 Gerrit-PatchSet: 1 Gerrit-Owner: Hanno Heinrichs <hanno.heinrichs(a)rwth-aachen.de> Gerrit-MessageType: newchange

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Change in flashrom[master]: Support Genesys Logic, Inc GL32xx Flash programming support
by Neil Armstrong (Code Review) 23 Feb '21

23 Feb '21

Attention is currently required from: Neil Armstrong. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/51038 to look at the new patch set (#2). Change subject: Support Genesys Logic, Inc GL32xx Flash programming support ...................................................................... Support Genesys Logic, Inc GL32xx Flash programming support The Genesys Logic, Inc USB Memory Card Reader Controller devices offers ISP (In System Programming) of their attached flash. The protocl uses vendor SCSI/USB Mass Storage CBD commands exposing the SPI Flash bus providing command sending and optimized read/write. The protocol should be compatible with the GL32xx Memory Card Reader devices, including devices with a custom VID/PID. Only the tested GL3232 devices listed in the devs has been validated, but the driver matches with all Genesys Logic, Inc mass storage devices. Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> Change-Id: I8ac27a1d5cfe3683d060fb2586482ea72f913699 --- M Makefile M flashrom.8.tmpl M flashrom.c A gl32xx_spi.c M meson.build M meson_options.txt M programmer.h 7 files changed, 642 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/38/51038/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/51038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8ac27a1d5cfe3683d060fb2586482ea72f913699 Gerrit-Change-Number: 51038 Gerrit-PatchSet: 2 Gerrit-Owner: Neil Armstrong <narmstrong(a)baylibre.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Neil Armstrong <narmstrong(a)baylibre.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: Support Genesys Logic, Inc GL32xx Flash programming support
by Neil Armstrong (Code Review) 23 Feb '21

23 Feb '21

Neil Armstrong has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/51038 ) Change subject: Support Genesys Logic, Inc GL32xx Flash programming support ...................................................................... Support Genesys Logic, Inc GL32xx Flash programming support The Genesys Logic, Inc USB Memory Card Reader Controller devices offers ISP (In System Programming) of their attached flash. The protocl uses vendor SCSI/USB Mass Storage CBD commands exposing the SPI Flash bus providing command sending and optimized read/write. The protocol should be compatible with the GL32xx Memory Card Reader devices, including devices with a custom VID/PID. Only the tested GL3232 devices listed in the devs has been validated, but the driver matches with all Genesys Logic, Inc mass storage devices. Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> Change-Id: I8ac27a1d5cfe3683d060fb2586482ea72f913699 --- M Makefile M flashrom.8.tmpl M flashrom.c A gl32xx_spi.c M meson.build M meson_options.txt M programmer.h 7 files changed, 640 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/38/51038/1 diff --git a/Makefile b/Makefile index 6d37d55..03394a8 100644 --- a/Makefile +++ b/Makefile @@ -223,6 +223,12 @@ else override CONFIG_JLINK_SPI = no endif +# gl32xx_spi is also not available for DOS +ifeq ($(CONFIG_GL32XX_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_GL32XX_SPI=yes +else +override CONFIG_GL32XX_SPI = no +endif endif # FIXME: Should we check for Cygwin/MSVC as well? @@ -448,6 +454,11 @@ else override CONFIG_CH341A_SPI = no endif +ifeq ($(CONFIG_GL32XX_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_GL32XX_SPI=yes +else +override CONFIG_GL32XX_SPI = no +endif endif ifneq ($(TARGET_OS), Linux) @@ -794,6 +805,9 @@ # Disable J-Link for now. CONFIG_JLINK_SPI ?= no +# Enable GL32xx for now +CONFIG_GL32XX_SPI ?= yes + # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no @@ -822,6 +836,7 @@ override CONFIG_PICKIT2_SPI = no override CONFIG_RAIDEN_DEBUG_SPI = no override CONFIG_STLINKV3_SPI = no +override CONFIG_GL32XX_SPI = no endif ifeq ($(CONFIG_ENABLE_LIBPCI_PROGRAMMERS), no) override CONFIG_INTERNAL = no @@ -1144,6 +1159,12 @@ PROGRAMMER_OBJS += jlink_spi.o endif +ifeq ($(CONFIG_GL32XX_SPI), yes) +FEATURE_CFLAGS += -D'CONFIG_GL32XX_SPI=1' +PROGRAMMER_OBJS += gl32xx_spi.o +NEED_LIBUSB1 += CONFIG_GL32XX_SPI +endif + ifeq ($(CONFIG_NI845X_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_NI845X_SPI=1' diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 02f60dc..1b7b7ee 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -345,6 +345,8 @@ .sp .BR "* stlinkv3_spi" " (for SPI flash ROMs attached to STMicroelectronics STLINK V3 devices)" .sp +.BR "* gl32xx_spi" " (for SPI flash ROMs attached to Genesys Logic, Inc USB Memory Card Reader Controller devices)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER-SPECIFIC INFORMATION @@ -1316,6 +1318,33 @@ If the passed frequency is not supported by the adapter the nearest lower supported frequency will be used. .SS +.BR "gl32xx_spi " programmer +This module supports SPI flash programming through the Genesys Logic, Inc USB Memory +Card Reader Controller devices. +.sp +.B " flashrom \-p gl32xx_spi" +.sp +If there is more than one compatible device connected, you can select which one +should be used by specifying its serial number with the +.sp +.B " flashrom \-p gl32xx_spi:serial=number" +.sp +syntax where +.B number +is the serial number of the device (which can be found for example in the +output of lsusb -v). +.sp +VID:PID can be changed by the product vendor. To program these devices, the custom +PID and VID should be provided as programmer params with the +.sp +.B " flashrom \-p gl32xx_spi:vid=0xXXXX:pid=0xXXXX" +.sp +syntax where +.B vid +is the vendor ID and +.B pid +is the product ID (which can be found in the output of lsusb). +.SS .SH EXAMPLES To back up and update your BIOS, run diff --git a/flashrom.c b/flashrom.c index c89abad..b9f24c6 100644 --- a/flashrom.c +++ b/flashrom.c @@ -533,6 +533,18 @@ }, #endif +#if CONFIG_GL32XX_SPI == 1 + { + .name = "gl32xx_spi", + .type = USB, + .devs.dev = devs_gl32xx_spi, + .init = gl32xx_spi_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + {0}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; diff --git a/gl32xx_spi.c b/gl32xx_spi.c new file mode 100644 index 0000000..0d36ad0 --- /dev/null +++ b/gl32xx_spi.c @@ -0,0 +1,562 @@ +/* + * This file is part of the flashrom project. + * + * Copyright 2021, BayLibre, SAS. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Driver for programming SPI flash chips attached to the Genesys Logic, Inc USB Memory + * Card Reader Controller devices. + * + * Product page: http://www.genesyslogic.com/en/product_list.php?1st=1&2nd=7 + * + * This code should work with GL3232, GL3233, GL3225, GL3226, GL3227 based products + * even probably with GL3230, GL3231, GL3223, GL3224 based products. + * + * This code has been validated with a GL3232 device. + * + * VID:PID can be changed by the product vendor, to program these devices the custom + * PID & VID should be provided as programmer params: vid= & pid= + */ + +#include "programmer.h" +#include "spi.h" +#include "usb_device.h" + +#include <libusb.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> + +#define TRANSFER_TIMEOUT_MS (200 + 800) + +#define GL32XX_SPI_VID (0x05e3) + +/* Tested devices to be filled here */ +const struct dev_entry devs_gl32xx_spi[] = { + {GL32XX_SPI_VID, 0x0764, OK, "Genesys Logic, Inc.", "GL3232"}, + {0} +}; + +/* Section 5.1: Command Block Wrapper (CBW) */ +struct command_block_wrapper { + uint8_t dCBWSignature[4]; + uint32_t dCBWTag; + uint32_t dCBWDataTransferLength; + uint8_t bmCBWFlags; + uint8_t bCBWLUN; + uint8_t bCBWCBLength; + uint8_t CBWCB[16]; +}; + +/* Section 5.2: Command Status Wrapper (CSW) */ +struct command_status_wrapper { + uint8_t dCSWSignature[4]; + uint32_t dCSWTag; + uint32_t dCSWDataResidue; + uint8_t bCSWStatus; +}; + +static int send_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint, + uint8_t *cdb, uint8_t cdb_len, uint8_t direction, int data_length, + uint32_t *ret_tag) +{ + struct command_block_wrapper cbw; + static uint32_t tag = 1; + int r, size, i = 0; + + if (cdb == NULL) + return -1; + + if (endpoint & LIBUSB_ENDPOINT_IN) { + msg_perr("%s: cannot send command on IN endpoint\n", __func__); + return -1; + } + + memset(&cbw, 0, sizeof(cbw)); + cbw.dCBWSignature[0] = 'U'; + cbw.dCBWSignature[1] = 'S'; + cbw.dCBWSignature[2] = 'B'; + cbw.dCBWSignature[3] = 'C'; + *ret_tag = tag; + cbw.dCBWTag = tag++; + cbw.dCBWDataTransferLength = data_length; + cbw.bmCBWFlags = direction; + cbw.bCBWLUN = 0; + cbw.bCBWCBLength = cdb_len; + memcpy(cbw.CBWCB, cdb, cdb_len); + + /* The transfer length must always be exactly 31 bytes. */ + do { + r = libusb_bulk_transfer(handle, endpoint, (unsigned char*)&cbw, 31, + &size, TRANSFER_TIMEOUT_MS); + if (r == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(handle, endpoint); + } + ++i; + } while ((r == LIBUSB_ERROR_PIPE) && (i<5)); + + if (r != LIBUSB_SUCCESS) { + msg_perr("%s: %s\n", __func__, libusb_strerror((enum libusb_error)r)); + return LIBUSB_ERROR(r); + } + + return 0; +} + +static int get_mass_storage_status(libusb_device_handle *handle, uint8_t endpoint, + uint32_t expected_tag) +{ + struct command_status_wrapper csw; + int r, size, i = 0; + + /* The transfer length must always be exactly 31 bytes. */ + do { + r = LIBUSB(libusb_bulk_transfer(handle, endpoint, (unsigned char*)&csw, 13, + &size, TRANSFER_TIMEOUT_MS)); + if (r == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(handle, endpoint); + } + ++i; + } while ((r == LIBUSB_ERROR_PIPE) && (i<5)); + + if (r != LIBUSB_SUCCESS) { + msg_perr("%s: %s\n", __func__, libusb_strerror((enum libusb_error)r)); + return LIBUSB_ERROR(r); + } + + if (size != 13) { + msg_perr("%s: received %d bytes (expected 13)\n", __func__, size); + return -1; + } + + if (csw.dCSWTag != expected_tag) { + msg_perr("%s: mismatched tags (expected %08X, received %08X)\n", __func__, + expected_tag, csw.dCSWTag); + return -1; + } + + if (csw.bCSWStatus) { + msg_perr("%s: Status %d DataResidue %d\n", __func__, csw.bCSWStatus, + csw.dCSWDataResidue); + return -1; + } + + return 0; +} + +struct gl32xx_spi_data { + struct usb_device *dev; + uint8_t in_ep; + uint8_t out_ep; +}; + +static struct gl32xx_spi_data * + get_gl32xx_spi_data_from_context(const struct flashctx *flash) +{ + return (struct gl32xx_spi_data *)flash->mst->spi.data; +} + +static int send_command(const struct flashctx *flash, + unsigned int write_count, + unsigned int read_count, + const unsigned char *write_buffer, + unsigned char *read_buffer) +{ + const struct gl32xx_spi_data *ctx_data = get_gl32xx_spi_data_from_context(flash); + uint8_t cbd_write[6] = {0xf3, 0x02, 0, 0, 0, 0}; + uint8_t cbd_read[6] = {0xf3, 0x04, 0, 0, 0, 0}; + uint32_t tag; + int r, size; + + /* Use a simpler command for a single-byte command */ + if (write_count == 1 && read_count == 0) { + uint8_t cbd[6] = {0xf3, 0, 0, 0, write_buffer[0], 0}; + + r = send_mass_storage_command(ctx_data->dev->handle, ctx_data->out_ep, + cbd, 6, 0, 0, &tag); + if (r) + return r; + + r = get_mass_storage_status(ctx_data->dev->handle, ctx_data->in_ep, tag); + if (r) + return r; + + return 0; + } + + if (!write_count || write_count > 0xffff || read_count > 0xff) + return -1; + + cbd_write[2] = (write_count >> 8) & 0xff; + cbd_write[3] = write_count & 0xff; + cbd_write[4] = (read_count >> 8) & 0xff; + cbd_write[5] = read_count & 0xff; + cbd_read[5] = read_count & 0xff; + + /* Write */ + r = send_mass_storage_command(ctx_data->dev->handle, ctx_data->out_ep, cbd_write, + 6, 0, write_count, &tag); + if (r) + return r; + + r = LIBUSB(libusb_bulk_transfer(ctx_data->dev->handle, ctx_data->out_ep, + (unsigned char *)write_buffer, write_count, &size, + TRANSFER_TIMEOUT_MS)); + if (r) + return r; + + r = get_mass_storage_status(ctx_data->dev->handle, ctx_data->in_ep, tag); + if (r) + return r; + + if (read_count == 0) + return 0; + + /* Read */ + r = send_mass_storage_command(ctx_data->dev->handle, ctx_data->out_ep, cbd_read, + 6, 0x80, read_count, &tag); + if (r) + return r; + + r = LIBUSB(libusb_bulk_transfer(ctx_data->dev->handle, ctx_data->in_ep, read_buffer, + read_count, &size, TRANSFER_TIMEOUT_MS)); + if (r) + return r; + + r = get_mass_storage_status(ctx_data->dev->handle, ctx_data->in_ep, tag); + if (r) + return r; + + return 0; +} + +int gl32xx_spi_write(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) +{ + const struct gl32xx_spi_data *ctx_data = get_gl32xx_spi_data_from_context(flash); + unsigned int remain = len, tx_size, pos = 0, address = start; + uint8_t cbd_write[10] = {0xe5, 0x08, 0, 0, 0, 0, 0, 0, 0, 0}; + unsigned int maxpacketsize; + uint32_t tag; + int r, size; + + if (!len) + return 0; + + r = libusb_get_max_packet_size(ctx_data->dev->device, ctx_data->out_ep); + if (r < 0) + return LIBUSB_ERROR(r); + + /* Limiting to 256bytes per command for write avoids write errors */ + maxpacketsize = min(256, r); + + while (remain) { + tx_size = min(maxpacketsize, remain); + + cbd_write[2] = address >> 24; + cbd_write[3] = (address >> 16) & 0xff; + cbd_write[4] = (address >> 8) & 0xff; + cbd_write[5] = address & 0xff; + + cbd_write[6] = tx_size >> 8; + cbd_write[7] = tx_size & 0xff; + + r = send_mass_storage_command(ctx_data->dev->handle, ctx_data->out_ep, cbd_write, + 10, 0, tx_size, &tag); + if (r) + return r; + + r = LIBUSB(libusb_bulk_transfer(ctx_data->dev->handle, ctx_data->out_ep, + (unsigned char *)&buf[pos], tx_size, &size, + TRANSFER_TIMEOUT_MS)); + if (r) + return r; + + r = get_mass_storage_status(ctx_data->dev->handle, ctx_data->in_ep, tag); + if (r) + return r; + + remain -= tx_size; + pos += tx_size; + address += tx_size; + } + + return 0; + +} + +int gl32xx_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) +{ + const struct gl32xx_spi_data *ctx_data = get_gl32xx_spi_data_from_context(flash); + unsigned int remain = len, rx_size, pos = 0, address = start; + uint8_t cbd_read[10] = {0xe4, 0x08, 0, 0, 0, 0, 0, 0, 0, 0}; + unsigned int maxpacketsize; + uint32_t tag; + int r, size; + + if (!len) + return 0; + + r = libusb_get_max_packet_size(ctx_data->dev->device, ctx_data->in_ep); + if (r < 0) + return LIBUSB_ERROR(r); + maxpacketsize = r; + + while (remain) { + rx_size = min(maxpacketsize, remain); + + cbd_read[2] = address >> 24; + cbd_read[3] = (address >> 16) & 0xff; + cbd_read[4] = (address >> 8) & 0xff; + cbd_read[5] = address & 0xff; + + cbd_read[6] = rx_size >> 8; + cbd_read[7] = rx_size & 0xff; + + r = send_mass_storage_command(ctx_data->dev->handle, ctx_data->out_ep, cbd_read, + 10, 0x80, rx_size, &tag); + if (r) + return r; + + r = LIBUSB(libusb_bulk_transfer(ctx_data->dev->handle, ctx_data->in_ep, + &buf[pos], rx_size, &size, + TRANSFER_TIMEOUT_MS)); + if (r) + return r; + + r = get_mass_storage_status(ctx_data->dev->handle, ctx_data->in_ep, tag); + if (r) + return r; + + remain -= rx_size; + pos += rx_size; + address += rx_size; + } + + return 0; + +} + +static const struct spi_master spi_master_gl32xx_spi = { + .features = SPI_MASTER_4BA, + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, + .command = send_command, + .multicommand = default_spi_send_multicommand, + .read = gl32xx_spi_read, + .write_256 = gl32xx_spi_write, + .write_aai = default_spi_write_aai, +}; + +static int match_endpoint(struct libusb_endpoint_descriptor const *descriptor, + enum libusb_endpoint_direction direction) +{ + return (((descriptor->bEndpointAddress & LIBUSB_ENDPOINT_DIR_MASK) == + direction) && + ((descriptor->bmAttributes & LIBUSB_TRANSFER_TYPE_MASK) == + LIBUSB_TRANSFER_TYPE_BULK)); +} + +static int find_endpoints(struct usb_device *dev, uint8_t *in_ep, uint8_t *out_ep) +{ + int i; + int in_count = 0; + int out_count = 0; + + for (i = 0; i < dev->interface_descriptor->bNumEndpoints; i++) { + struct libusb_endpoint_descriptor const *endpoint = + &dev->interface_descriptor->endpoint[i]; + + if (match_endpoint(endpoint, LIBUSB_ENDPOINT_IN)) { + in_count++; + *in_ep = endpoint->bEndpointAddress; + } else if (match_endpoint(endpoint, LIBUSB_ENDPOINT_OUT)) { + out_count++; + *out_ep = endpoint->bEndpointAddress; + } + } + + if (in_count != 1 || out_count != 1) { + msg_perr("Failed to find one IN and one OUT endpoint\n" + " found %d IN and %d OUT endpoints\n", + in_count, + out_count); + return 1; + } + + msg_pdbg("Found IN endpoint = 0x%02x\n", *in_ep); + msg_pdbg("Found OUT endpoint = 0x%02x\n", *out_ep); + + return 0; +} + +static int gl32xx_spi_shutdown(void * data) +{ + struct spi_master *spi_config = data; + struct gl32xx_spi_data *ctx_data = + (struct gl32xx_spi_data *)spi_config->data; + + usb_device_free(ctx_data->dev); + libusb_exit(NULL); + free(ctx_data); + free(spi_config); + + return 0; +} + +static void free_dev_list(struct usb_device **dev_lst) +{ + struct usb_device *dev = *dev_lst; + /* free devices we don't care about */ + dev = dev->next; + while (dev) + dev = usb_device_free(dev); +} + +static int gl32xx_spi_get_fw_version(struct usb_device *dev, uint8_t in_ep, + uint8_t out_ep) +{ + uint8_t cbd[6] = {0xe4, 0x01, 0, 0xc0, 0x20, 0}; + uint8_t buf[0x20]; + uint32_t tag; + int r, size; + + r = send_mass_storage_command(dev->handle, out_ep, cbd, 6, 0x80, 0x20, + &tag); + if (r) + return r; + + r = LIBUSB(libusb_bulk_transfer(dev->handle, in_ep, buf, 0x20, &size, + TRANSFER_TIMEOUT_MS)); + if (r) + return r; + + r = get_mass_storage_status(dev->handle, in_ep, tag); + if (r) + return r; + + msg_pinfo("firmware version=%c%c%c%c\n", + buf[0x14], buf[0x15], buf[0x16], buf[0x17]); + + return 0; +} + +/* This switches the MCU firmware to Flash programming mode */ +static int gl32xx_spi_switch_program_mode(struct gl32xx_spi_data *data) +{ + uint8_t cbd[6] = {0xf3, 0x06, 0, 0, 0, 0}; + uint32_t tag; + int r; + + r = send_mass_storage_command(data->dev->handle, data->out_ep, cbd, 6, 0, 0, &tag); + if (r) + return r; + + r = get_mass_storage_status(data->dev->handle, data->in_ep, tag); + + return r; +} + +#define USB_CLASS_MASS_STORAGE 8 + +int gl32xx_spi_init(void) +{ + struct usb_match match; + struct usb_device *current; + struct usb_device *device = NULL; + int found = 0; + int ret; + + usb_match_init(&match); + + usb_match_value_default(&match.vid, GL32XX_SPI_VID); + usb_match_value_default(&match.class, USB_CLASS_MASS_STORAGE); + + ret = LIBUSB(libusb_init(NULL)); + if (ret != 0) { + msg_perr("GL32xx: libusb_init failed\n"); + return ret; + } + + ret = usb_device_find(&match, &current); + if (ret != 0) { + msg_perr("GL32xx: Failed to find devices\n"); + return ret; + } + + uint8_t in_endpoint = 0; + uint8_t out_endpoint = 0; + while (current) { + device = current; + + if (find_endpoints(device, &in_endpoint, &out_endpoint)) { + msg_pdbg("GL32xx: Failed to find valid endpoints on device"); + usb_device_show(" ", current); + current = usb_device_free(current); + continue; + } + + if (usb_device_claim(device)) { + msg_pdbg("GL32xx: Failed to claim USB device"); + usb_device_show(" ", current); + current = usb_device_free(current); + continue; + } + + if (gl32xx_spi_get_fw_version(device, in_endpoint, + out_endpoint)) { + msg_pdbg("GL32xx: Failed to get Firmware version"); + usb_device_show(" ", current); + current = usb_device_free(current); + continue; + } + + found = 1; + break; + } + + if (!device || !found) { + msg_perr("GL32xx: No usable device found.\n"); + return 1; + } + + free_dev_list(&current); + + struct spi_master *spi_config = calloc(1, sizeof(struct spi_master)); + if (!spi_config) { + msg_perr("Unable to allocate space for SPI master.\n"); + return SPI_GENERIC_ERROR; + } + struct gl32xx_spi_data *data = calloc(1, sizeof(struct gl32xx_spi_data)); + if (!data) { + free(spi_config); + msg_perr("Unable to allocate space for extra SPI master data.\n"); + return SPI_GENERIC_ERROR; + } + + memcpy(spi_config, &spi_master_gl32xx_spi, sizeof(struct spi_master)); + + data->dev = device; + data->in_ep = in_endpoint; + data->out_ep = out_endpoint; + + spi_config->data = data; + + gl32xx_spi_switch_program_mode(data); + + register_spi_master(spi_config); + register_shutdown(gl32xx_spi_shutdown, spi_config); + + return 0; +} diff --git a/meson.build b/meson.build index 73df722..5d4b7e5 100644 --- a/meson.build +++ b/meson.build @@ -68,6 +68,7 @@ config_stlinkv3_spi = get_option('config_stlinkv3_spi') config_lspcon_i2c_spi = get_option('config_lspcon_i2c_spi') config_realtek_mst_i2c_spi = get_option('config_realtek_mst_i2c_spi') +config_gl32xx_spi = get_option('config_gl32xx_spi') cargs = [] deps = [] @@ -98,6 +99,7 @@ config_digilent_spi = false config_developerbox_spi = false config_pickit2_spi = false + config_gl32xx_spi = false endif # some programmers require libpci @@ -309,6 +311,10 @@ srcs += 'realtek_mst_i2c_spi.c' cargs += '-DCONFIG_REALTEK_MST_I2C_SPI=1' endif +if config_gl32xx_spi + srcs += 'gl32xx_spi.c' + cargs += '-DCONFIG_GL32XX_SPI=1' +endif # bitbanging SPI infrastructure if config_bitbang_spi diff --git a/meson_options.txt b/meson_options.txt index b599d66..8a9491d 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -40,3 +40,4 @@ option('config_stlinkv3_spi', type : 'boolean', value : true, description : 'STMicroelectronics STLINK-V3') option('config_lspcon_i2c_spi', type : 'boolean', value : false, description : 'Parade lspcon USB-C to HDMI protocol translator') option('config_realtek_mst_i2c_spi', type : 'boolean', value : true, description : 'Realtek MultiStream Transport MST') +option('config_gl32xx_spi', type : 'boolean', value : true, description : 'Genesys Logic, Inc GL32xx SPI Flash Bus') diff --git a/programmer.h b/programmer.h index 29a100b..dcbd57a 100644 --- a/programmer.h +++ b/programmer.h @@ -142,6 +142,9 @@ #if CONFIG_REALTEK_MST_I2C_SPI == 1 PROGRAMMER_REALTEK_MST_I2C_SPI, #endif +#if CONFIG_GL32XX_SPI == 1 + PROGRAMMER_GL32XX_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -842,4 +845,10 @@ int realtek_mst_i2c_spi_init(void); #endif +/* gl32xx_spi.c */ +#if CONFIG_GL32XX_SPI == 1 +int gl32xx_spi_init(void); +extern const struct dev_entry devs_gl32xx_spi[]; +#endif + #endif /* !__PROGRAMMER_H__ */ -- To view, visit https://review.coreboot.org/c/flashrom/+/51038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8ac27a1d5cfe3683d060fb2586482ea72f913699 Gerrit-Change-Number: 51038 Gerrit-PatchSet: 1 Gerrit-Owner: Neil Armstrong <narmstrong(a)baylibre.com> Gerrit-MessageType: newchange

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flashrom-gerrit February 2021