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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Nikolai Artemiev,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58736
to look at the new patch set (#4).
Change subject: ichspi: Extract handling programmer param into a function
......................................................................
ichspi: Extract handling programmer param into a function
Extract processing of ich_spi_mode into a separate function which
is called from init_ich_default. This makes init_ich_default more
readable and avoids one local variable.
TEST ME ON ICH7
BUG=b:204488958
TEST=Check that the following scenarios still behave properly:
1) probe-read-verify-erase section-write-reboot
on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E
2) probe and read on Panther Point (7 series PCH)
Change-Id: I20e2379a6fd58c9346f0a2d6daf2b8decf1f6976
Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org>
Tested-by: Anastasia Klimchuk <aklm(a)chromium.org>
Tested-by: Nico Huber <nico.h(a)gmx.de>
---
M ichspi.c
1 file changed, 37 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/36/58736/4
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Attention is currently required from: Felix Singer, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Nikolai Artemiev.
Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Nikolai Artemiev,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58735
to look at the new patch set (#4).
Change subject: ichspi: Split very long init function into two
......................................................................
ichspi: Split very long init function into two
ich_init_spi is very long, but logically it can be split. Init
function detects the chipset and then the rest of operations depends
on the chipset.
Init function is more readable now, it consists of only a switch.
Initialisation of hwseq and swseq that used to happen in the
beginning of init function now moved to init_ich_default, because
hwseq and swseq are only used for chipsets served by init_ich_default.
TEST ME ON ICH7
BUG=b:204488958
TEST=Check that the following scenarios still behave properly:
1) probe-read-verify-erase section-write-reboot
on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E
2) probe and read on Panther Point (7 series PCH)
Change-Id: I6789bc456a4878e6555831ae0b80ecbdbf62938b
Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org>
Tested-by: Anastasia Klimchuk <aklm(a)chromium.org>
Tested-by: Nico Huber <nico.h(a)gmx.de>
---
M ichspi.c
1 file changed, 268 insertions(+), 255 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/35/58735/4
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58737 )
Change subject: ichspi: Extract initialisation of swseq and hwseq into a function
......................................................................
Patch Set 3: Code-Review+2
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Attention is currently required from: Felix Singer, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Nikolai Artemiev.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58735 )
Change subject: ichspi: Split very long init function into two
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/58735/comment/d678342d_572a1381
PS3, Line 20: TEST=1) probe-read-verify-erase section-write-reboot
: on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E
: 2) probe and read on Panther Point (7 series PCH)
> If you still need a `TEST=` tag for some reason, you could do something like this: […]
Generally it seems fine to me to add all the existing test info.
About Tested-by:
You are right to ask, IMHO, as it sets somebody else's name in stone,
kind of (Git virtually never forgets). When somebody is CC'ed on Gerrit,
I guess it doesn't matter much (people could at least object). But if
not, better ask them personally. For active contributors I think we can
imply their consent :)
We don't have a rule for presence of Tested-by tags, AFAIK.
Patchset:
PS1:
> To close the comment: I could not find devices with older chipsets, but Nico saved me and tested tho […]
Sorry to disappoint. There seems to be a misunderstanding. PCHs inherited the
generation numbers from MCHs, not ICHs. So ICH7 is something different, much
older. We could ask in #flashrom and #coreboot channels for ICH7 testers. There
are some famous machines, e.g. ThinkPad X60/T60, with it. Or let's try this:
Angel, do you have any ICH7 board ready to boot? :)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/58735/comment/2b377824_4f881118
PS1, Line 1717: msg_pdbg("0x00: 0x%04x (SPIS)\n",
: mmio_readw(spibar + 0));
: msg_pdbg("0x02: 0x%04x (SPIC)\n",
: mmio_readw(spibar + 2));
: msg_pdbg("0x04: 0x%08x (SPIA)\n",
: mmio_readl(spibar + 4));
: ichspi_bbar = mmio_readl(spibar + 0x50);
: msg_pdbg("0x50: 0x%08x (BBAR)\n",
: ichspi_bbar);
: msg_pdbg("0x54: 0x%04x (PREOP)\n",
: mmio_readw(spibar + 0x54));
: msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
: mmio_readw(spibar + 0x56));
: msg_pdbg("0x58: 0x%08x (OPMENU)\n",
: mmio_readl(spibar + 0x58));
: msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
: mmio_readl(spibar + 0x5c));
> Done in CB:60272. […]
Would have preferred it here, it seems wrong to change lines and then fix
them up right away. No strong feelings, though.
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Attention is currently required from: Thomas Heijligen.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59050 )
Change subject: Makefile: Make pkg-config mandatory to find libpci
......................................................................
Patch Set 15: Code-Review+1
(2 comments)
File Makefile:
https://review.coreboot.org/c/flashrom/+/59050/comment/740bae06_48f34f9e
PS15, Line 866: USE_X86_MSR := $(if $(call filter_deps,$(DEPENDS_ON_X86_MSR)),yes,no)
Is this split done intentionally in this patch? or did it sneak into
the rebase? Risking to state the obvious: I'd prefer a separate patch ;)
If it needs to be in this patch, the commit message should cover it.
There is also an important message: we don't imply anymore that libpci
requires raw access (AFAICS).
https://review.coreboot.org/c/flashrom/+/59050/comment/d6b5c72e_baebba42
PS15, Line 882: $(filter yes, $(USE_X86_MSR) $(USE_X86_PORT_IO) $(USE_RAW_MEM_ACCESS)))
`$(filter )` picks words from the second argument, kind of the haystack.
So this could result in multiple `yes` and then the `ifeq` wouldn't match
anymore. You can turn the arguments around:
$(filter $(USE_X86_MSR) $(USE_X86_PORT_IO) $(USE_RAW_MEM_ACCESS), yes)
This can only return one `yes` because there is only one in the haystack
to find.
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Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/60114 )
Change subject: Makefile: list dependencies for RAW_MEM_ACCESS, X86_PORT_IO, X86_MSR
......................................................................
Makefile: list dependencies for RAW_MEM_ACCESS, X86_PORT_IO, X86_MSR
List all programmers which depend on the respective hwaccess features.
This is the base for a precise feature selecting in the build system.
Change-Id: I588f698780b5acd65084346bcef781cbfd1203ea
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60114
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M Makefile
1 file changed, 48 insertions(+), 9 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
diff --git a/Makefile b/Makefile
index c985ae0..9a6d7b0 100644
--- a/Makefile
+++ b/Makefile
@@ -107,6 +107,40 @@
CONFIG_PONY_SPI \
CONFIG_RAYER_SPI \
+DEPENDS_ON_RAW_MEM_ACCESS := \
+ CONFIG_ATAPROMISE \
+ CONFIG_DRKAISER \
+ CONFIG_GFXNVIDIA \
+ CONFIG_INTERNAL \
+ CONFIG_IT8212 \
+ CONFIG_NICINTEL \
+ CONFIG_NICINTEL_EEPROM \
+ CONFIG_NICINTEL_SPI \
+ CONFIG_OGP_SPI \
+ CONFIG_SATAMV \
+ CONFIG_SATASII \
+
+DEPENDS_ON_X86_MSR := \
+ CONFIG_INTERNAL \
+
+DEPENDS_ON_X86_PORT_IO := \
+ CONFIG_ATAHPT \
+ CONFIG_ATAPROMISE \
+ CONFIG_ATAVIA \
+ CONFIG_DRKAISER \
+ CONFIG_GFXNVIDIA \
+ CONFIG_INTERNAL \
+ CONFIG_NIC3COM \
+ CONFIG_NICINTEL \
+ CONFIG_NICINTEL_EEPROM \
+ CONFIG_NICINTEL_SPI \
+ CONFIG_NICNATSEMI \
+ CONFIG_NICREALTEK \
+ CONFIG_OGP_SPI \
+ CONFIG_RAYER_SPI \
+ CONFIG_SATAMV \
+ CONFIG_SATASII \
+
DEPENDS_ON_LIBPCI := \
CONFIG_ATAHPT \
CONFIG_ATAPROMISE \
@@ -255,7 +289,13 @@
# For now we disable all PCI-based programmers on Windows/MinGW (no libpci).
$(call mark_unsupported,$(DEPENDS_ON_LIBPCI))
# And programmers that need raw access.
-$(call mark_unsupported,CONFIG_RAYER_SPI)
+$(call mark_unsupported,$(DEPENDS_ON_RAW_MEM_ACCESS))
+
+else # No MinGW
+
+# NI USB-845x only supported on Windows at the moment
+$(call mark_unsupported,CONFIG_NI845X_SPI)
+
endif
ifeq ($(TARGET_OS), libpayload)
@@ -268,7 +308,9 @@
# libpayload does not provide the romsize field in struct pci_dev that the atapromise code requires.
$(call mark_unsupported,CONFIG_ATAPROMISE)
# Bus Pirate, Serprog and PonyProg are not supported with libpayload (missing serial support).
-$(call mark_unsupported,CONFIG_BUSPIRATE_SPI CONFIG_SERPROG CONFIG_PONY_SPI)
+$(call mark_unsupported,$(DEPENDS_ON_SERIAL))
+# Dediprog, Developerbox, USB-Blaster, PICkit2, CH341A and FT2232 are not supported with libpayload (missing libusb support).
+$(call mark_unsupported,$(DEPENDS_ON_LIBUSB1) $(DEPENDS_ON_LIBFTDI) $(DEPENDS_ON_LIBJAYLINK))
endif
ifeq ($(HAS_LINUX_MTD), no)
@@ -285,7 +327,7 @@
ifeq ($(TARGET_OS), Android)
# Android on x86 (currently) does not provide raw PCI port I/O operations.
-$(call mark_unsupported,CONFIG_RAYER_SPI)
+$(call mark_unsupported,$(DEPENDS_ON_X86_PORT_IO))
endif
# Disable the internal programmer on unsupported architectures (everything but x86 and mipsel)
@@ -319,18 +361,15 @@
# PCI port I/O support is unimplemented on PPC/MIPS/SPARC and unavailable on ARM.
# Right now this means the drivers below only work on x86.
ifneq ($(ARCH), x86)
-$(call mark_unsupported,CONFIG_NIC3COM CONFIG_NICREALTEK CONFIG_NICNATSEMI)
-$(call mark_unsupported,CONFIG_RAYER_SPI CONFIG_ATAHPT CONFIG_ATAPROMISE)
-$(call mark_unsupported,CONFIG_SATAMV)
+$(call mark_unsupported,$(DEPENDS_ON_X86_MSR))
+$(call mark_unsupported,$(DEPENDS_ON_X86_PORT_IO))
endif
# Additionally disable all drivers needing raw access (memory, PCI, port I/O)
# on architectures with unknown raw access properties.
# Right now those architectures are alpha hppa m68k sh s390
ifneq ($(ARCH), $(filter $(ARCH), x86 mips ppc arm sparc arc))
-$(call mark_unsupported,CONFIG_GFXNVIDIA CONFIG_SATASII CONFIG_ATAVIA)
-$(call mark_unsupported,CONFIG_DRKAISER CONFIG_NICINTEL CONFIG_NICINTEL_SPI)
-$(call mark_unsupported,CONFIG_NICINTEL_EEPROM CONFIG_OGP_SPI CONFIG_IT8212)
+$(call mark_unsupported,$(DEPENDS_ON_RAW_MEM_ACCESS))
endif
ifeq ($(TARGET_OS), $(filter $(TARGET_OS), Linux Darwin NetBSD OpenBSD))
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