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Change subject: hwaccess_x86_msr: buildfix for FreeBSD
......................................................................
Patch Set 1: Code-Review+2
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Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58477 )
Change subject: flashchips: add writeprotect bit layout map to chips
......................................................................
Patch Set 22:
(2 comments)
File flash.h:
https://review.coreboot.org/c/flashrom/+/58477/comment/3226bb7c_aac9d49a
PS21, Line 192: 0
> Why give these numbers? Is there anything to sync with?
Done
https://review.coreboot.org/c/flashrom/+/58477/comment/f4d565bb_4371dc16
PS21, Line 283: */
> We should generally try to find a better representation for the flash chips. […]
That's a good point, thanks.
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Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58570 )
Change subject: spi25_statusreg,flashchips: add SR2 read/write support
......................................................................
Patch Set 19:
(3 comments)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/58570/comment/182e9933_af57a8c5
PS18, Line 6711: FEATURE_WRSR_EXT
> The datasheet suggests this won't work, AFAICT, and I guess this path […]
At least according to datasheet rev 2.1 the WRSR (01h) command can write both registers together, I don't remember whether I tested it though.
https://review.coreboot.org/c/flashrom/+/58570/comment/13704bea_0dd976f1
PS18, Line 6872: .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
> Spurious change?
Done
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/58570/comment/c95fca3a_704e398c
PS17, Line 109: if (spi_read_register(flash, STATUS1, &sr1))
: return 1;
> Would it make sense to print an error here?
Done
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Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58475 )
Change subject: spi25_statusreg: make register read/write functions generic
......................................................................
Patch Set 16:
(12 comments)
File flash.h:
https://review.coreboot.org/c/flashrom/+/58475/comment/23162502_2572ba7a
PS15, Line 170: INVALID_REG = 0,
: STATUS1,
: STATUS2,
: CONFIG1,
> Please add entries in the commits that make use of them. Took me rather […]
Done. Yes, I had CONFIG1 for some Macronix chips, but I'll add it back later if it's needed.
File flash.h:
https://review.coreboot.org/c/flashrom/+/58475/comment/fcf847f4_b2c282fd
PS14, Line 169: enum flash_reg {
: INVALID_REG = 0,
: STATUS1,
: STATUS2,
: CONFIG1,
: };
: #define MAX_REGISTERS 4
> `MAX_REGISTERS` is only used in `writeprotect.c` AFAICS, so it would belong […]
I've made it the last element, that should be a bit more robust. It's useful if you want to iterate over all registers that flashrom knows about, though I don't have another example of doing that outside writeprotect right now.
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/58475/comment/3f1900ef_cc294e44
PS14, Line 51: int result = spi_send_multicommand(flash, cmds);
> What do you mean? What could cause problems?
I think you're referring to the fact that it declares a variable in the middle of the function? There's quite a lot of other code like that, it shouldn't cause any new problems.
https://review.coreboot.org/c/flashrom/+/58475/comment/ffe275e5_24adef03
PS14, Line 126:
> should be a tab
Done
https://review.coreboot.org/c/flashrom/+/58475/comment/15fbcf91_ecfe6b6c
PS14, Line 134:
> nit: double blank line
Done
https://review.coreboot.org/c/flashrom/+/58475/comment/8770b6c6_08bea653
PS14, Line 149:
> nit: double blank line
Done
https://review.coreboot.org/c/flashrom/+/58475/comment/4585c851_7818ee9f
PS14, Line 194: spi_write_register failed.
> Would be good to indicate which register failed: […]
Done
https://review.coreboot.org/c/flashrom/+/58475/comment/1a0216b7_f39b55f1
PS14, Line 207: spi_write_register failed.
> Ditto
Done
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/58475/comment/4a646003_8ff8b64e
PS15, Line 63: */
> I have doubts that this is true for any modern chip. "allow running RDSR […]
I'm inclined to agree, this code dates back to 2010 in commit 174f55bdec62, which doesn't mention any specific chip, but says that some chips take >100ms, which implies that the initial delay wasn't doing anything useful even then.
We can probably just switch everything over to repeated polling, WDYT?
https://review.coreboot.org/c/flashrom/+/58475/comment/7d58e45b_0890c29c
PS15, Line 84: *
> Please drop this dangling asterisk or add a line break after the first […]
Done
https://review.coreboot.org/c/flashrom/+/58475/comment/3d71c81b_5975355c
PS15, Line 89: }
> Why not use a switch/case? It would make it easier to provide proper error […]
The next commit adds nested ifs for handling chips with different ways of writing the same register, and they cant be converted to a switch/case very cleanly.
https://review.coreboot.org/c/flashrom/+/58475/comment/f17825b5_821c2d14
PS15, Line 91: not supported by chip\
> Or not supported by this function?
Done
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58475
to look at the new patch set (#16).
Change subject: spi25_statusreg: make register read/write functions generic
......................................................................
spi25_statusreg: make register read/write functions generic
This patch adds new spi_{read,write}_register() functions that take the
source/destination register as an argument. Currently they can only
access SR1, support for other registers will be added in another patch.
Since we're refactoring things, this commit also makes
spi_read_register() return an error code, making it possible to identify
error conditions that spi_read_status_register() concealed.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
BRANCH=none
Change-Id: I0a3951bbf993f2d8d830143b29d3ce16cc6901d7
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M chipdrivers.h
M flash.h
M spi25_statusreg.c
3 files changed, 76 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/75/58475/16
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#19).
Change subject: spi25_statusreg,flashchips: add SR2 read/write support
......................................................................
spi25_statusreg,flashchips: add SR2 read/write support
This patch adds support for reading and writing the second status
register and enables it on a limited set of flash chips.
Chip support for RDSR2/WRSR2/extended WRSR is represented using feature
flags to be consistent with how other SPI capabilities are represented.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
TEST=logged SR2 read/write values during wp commands
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---
M flash.h
M flashchips.c
M spi.h
M spi25_statusreg.c
4 files changed, 58 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/70/58570/19
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I'd like you to reexamine a change. Please visit
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Change subject: flashchips: add writeprotect bit layout map to chips
......................................................................
flashchips: add writeprotect bit layout map to chips
This patch adds a register bit map `struct reg_bit_info`, with fields
for storing the register, bit index, and writability of each bit that
affects the chip's write protection. This allows writeprotect code to be
independent of the register layout of any specific chip. The new fields
have been filled out for example chips.
The representation is centered around describing how bits can be
accessed and modified, rather than the layout of registers. This is
generally easier to work with in code that needs to access specific bits
and typically requires specifying the locations of fewer bits overall.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
BRANCH=none
Change-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flash.h
M flashchips.c
2 files changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/58477/22
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#23).
Change subject: flash: add structure to represent chip wp configuration
......................................................................
flash: add structure to represent chip wp configuration
Add `struct flashrom_wp_chip_config` for representing values of all WP
bits in a chip's status register(s).
It allows most WP code to store and manipulate a chip's configuration
without knowing the exact layout of bits in the chip's status registers.
Supporting other chips may require additional fields to be added to the
structure.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
BRANCH=none
Change-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flash.h
1 file changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/58478/23
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