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I'd like you to reexamine a change. Please visit
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Change subject: [RFC][OTP] dummyflasher: emulate OTP for W25Q128FV
......................................................................
[RFC][OTP] dummyflasher: emulate OTP for W25Q128FV
This adds more or less generic support for OTP emulation to dummyflasher
and immediately uses it to extend emulation for W25Q128FV with
register-based OTP, which will be used in tests.
Files with images for OTP registers can be specified via new otp<N>=
parameters for dummyflasher.
Change-Id: I1af3ac22a66104517f1fe035e034404c6b249257
Signed-off-by: Hatim Kanchwala <hatim at hatimak.me>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M dummyflasher.c
M flashrom.8.tmpl
2 files changed, 186 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/04/59404/18
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Hello build bot (Jenkins), Nico Huber, Angel Pons,
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Change subject: [RFC][OTP] tests: add tests for OTP regions
......................................................................
[RFC][OTP] tests: add tests for OTP regions
There are two sets of tests targeting two new dummyflasher chips that provide
two kinds of OTP.
Change-Id: I4ff584395367dfd52db89332d8e45d7e865276e1
Signed-off-by: Hatim Kanchwala <hatim at hatimak.me>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
A tests/chip_otp.c
M tests/meson.build
M tests/tests.c
M tests/tests.h
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I'd like you to reexamine a change. Please visit
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Change subject: [RFC][OTP] cli_classic: add options for managing OTP regions
......................................................................
[RFC][OTP] cli_classic: add options for managing OTP regions
New actions operate on OTP region specified by `--otp-region`, which is
a required option if there is more than one OTP region, otherwise it
can be omitted. Region numbering starts at 1.
All actions can be combined with `--otp-status`, which is processed
last and thus can print new state of the OTP.
Change-Id: If77694e3b1c453b3fc0561da7a9eefdbce4fbb2b
Signed-off-by: Hatim Kanchwala <hatim at hatimak.me>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M cli_classic.c
M flashrom.8.tmpl
2 files changed, 290 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/07/59407/18
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Hello build bot (Jenkins), Nico Huber, Angel Pons,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#14).
Change subject: [RFC][OTP] spi25_statusreg: support reading/writing security register
......................................................................
[RFC][OTP] spi25_statusreg: support reading/writing security register
Not to be confused with "secure registers" of OTP.
Security register is a dedicated status register for security-related
bits. You don't write its value directly, issuing corresponding write
command with no data just sets OTP bit to 1 automatically.
No WREN is necessary, but at least some datasheets indicate BUSY state
after write command.
Unlike cases where OTP bit is part of SR and can only be written while
in OTP mode, security register can only be written outside of the mode.
Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M flash.h
M spi.h
M spi25_statusreg.c
3 files changed, 58 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/59709/14
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/52883 )
Change subject: flashchips.c: merge GD25B128B/GD25Q128B and GD25Q127C/GD25Q128C
......................................................................
Patch Set 2:
(2 comments)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/52883/comment/6f46bb71_ed564385
PS2, Line 6585: GD25Q127C
this one is already wrong, since there is no QPI support. see my other comment
https://review.coreboot.org/c/flashrom/+/52883/comment/147b701a_638c9c76
PS2, Line 6274: GD25B128B
> The 25B versions don't support QPI (only regular Quad-SPI wich uses a
single wire for the command). The 25Q128B and C versions were probably
added separately because of minor differences (OTP sizes and SFDP
support?).
Just one tiny addition, since I stumbled upon that, too: What you say is right - the 25B don't support QPI. However, not all 25Q do support it. One exmaple is GD25Q127C, which lacks QPI support but has the QPI flag in flashrom. That means we already have a conflict here :/
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Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/60342 )
Change subject: hwaccess_x86_msr: fix build for FreeBSD
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/60342/comment/0ac82dfb_72cf593e
PS1, Line 7: hwaccess_x86_msr: buildfix for FreeBSD
> Nit: Make it a statement: Fix build for FreeBSD
Done
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Hello build bot (Jenkins), Nico Huber, Idwer Vollering, Paul Menzel, Angel Pons,
I'd like you to reexamine a change. Please visit
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Change subject: hwaccess_x86_msr: fix build for FreeBSD
......................................................................
hwaccess_x86_msr: fix build for FreeBSD
Add missing includes for FreeBSD
Change-Id: I2045345878392436b0ea4d6bd4f2896edc645673
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
---
M hwaccess_x86_msr.c
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/42/60342/2
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/60342 )
Change subject: hwaccess_x86_msr: buildfix for FreeBSD
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/60342/comment/e05551a2_e29719c5
PS1, Line 7: hwaccess_x86_msr: buildfix for FreeBSD
Nit: Make it a statement: Fix build for FreeBSD
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