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Change subject: [RFC][WPTST] dummyflasher: add SR2 emulation harness
......................................................................
Patch Set 13:
(3 comments)
File dummyflasher.c:
https://review.coreboot.org/c/flashrom/+/59072/comment/67d032ab_391dab68
PS12, Line 45: uint8_t emu_status;
: uint8_t emu_status2;
> Can these be an array? i.e. […]
Sure, done.
https://review.coreboot.org/c/flashrom/+/59072/comment/a31e2e4b_17dd7366
PS12, Line 164: int
> Can we use `enum flash_reg` to represent the register? […]
Good point.
https://review.coreboot.org/c/flashrom/+/59072/comment/855cea5f_ebbaf8b9
PS12, Line 337: if (writecnt == 3) {
> I think this should check a flag in emu_data to check if the supports extended WRSR instructions.
Done
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Hello build bot (Jenkins), Nico Huber, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
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Change subject: [RFC][WPTST] dummyflasher: add SR2 emulation harness
......................................................................
[RFC][WPTST] dummyflasher: add SR2 emulation harness
Prepare everything for emulating SR2 for chips that have it.
This is needed for accessing second SRP bit which is involved in write
protection. The emulated register doesn't affect anything yet and will
be tested by write-protection tests.
Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M dummyflasher.c
M flashrom.8.tmpl
2 files changed, 76 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/59072/13
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Hello build bot (Jenkins), Nico Huber, Angel Pons, Nikolai Artemiev, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59073
to look at the new patch set (#13).
Change subject: [RFC][WPTST] dummyflasher: emulate SR2 for W25Q128FV
......................................................................
[RFC][WPTST] dummyflasher: emulate SR2 for W25Q128FV
Enable emulation of SR2 for W25Q128FV and provide logic for updating
it (mask of read-only bits that can't be set from outside).
W25Q128FV has three status registers, but no plans to use the third
one yet.
Change-Id: I79f9b4a0b604663d3288ad70dcbe3ea4075dede5
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M dummyflasher.c
1 file changed, 23 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/59073/13
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Hello build bot (Jenkins), Nico Huber, Angel Pons, Nikolai Artemiev, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59074
to look at the new patch set (#13).
Change subject: [RFC][WPTST] dummyflasher: enforce write protection for W25Q128FV
......................................................................
[RFC][WPTST] dummyflasher: enforce write protection for W25Q128FV
Start taking bits related to write protection into account.
Also add "hwwp" parameter for dummy programmer that sets state of WP
pin (not inverted value).
dummyflasher doesn't store state of the chip between runs and flashrom
allows running only one command, so testing WP in this way is limited.
However, WP options can be combined with other operations and are
executed prior to them, so certain scenarios can be checked.
List possible ranges:
flashrom -p dummy:emulate=W25Q128FV,hwwp=yes --wp-list
Set a particular range and check status is correct:
flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \
--wp-enable \
--wp-range=0x00100000,0x00f00000 \
--wp-status
Enable write protection and try erasing/writing (erasing here):
# this fails
flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \
--wp-range=0,0x00c00000 \
--wp-enable \
--erase
Write protecting empty range has no effect:
# this succeeds
flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \
--wp-range=0,0 \
--wp-enable \
--erase
Change-Id: I9fd1417f941186391bd213bd355530143c8f04a0
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M dummyflasher.c
M flashrom.8.tmpl
2 files changed, 155 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/74/59074/13
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Hello build bot (Jenkins), Nico Huber, Angel Pons,
I'd like you to reexamine a change. Please visit
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Change subject: [RFC][OTP] dummyflasher: add EN25QH128 chip with OTP mode
......................................................................
[RFC][OTP] dummyflasher: add EN25QH128 chip with OTP mode
This chip demonstrates seecond kind of OTP: mode upon entering which
regular read/write/erase commands can be used to interact with OTP
content. It will also be used in tests.
Change-Id: Id5857db43ebf2613bdb5e99342d28d4e0981a6b8
Signed-off-by: Hatim Kanchwala <hatim at hatimak.me>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M dummyflasher.c
M flashrom.8.tmpl
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Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59075 )
Change subject: [RFC][WPTST] tests: test write protection
......................................................................
Patch Set 13:
(1 comment)
File tests/chip_wp.c:
https://review.coreboot.org/c/flashrom/+/59075/comment/9c765b72_3eb8086a
PS13, Line 260: 1
> I am a bit confused, this used to be 0 (successful case) and now set_mode fails? with the same input […]
This is probably because I removed support for setting power cycle / permanent protection in a recent patchset: https://review.coreboot.org/c/flashrom/+/58483/23.
The reason I removed it being that those modes aren't widely supported and have a lot of vendor-specific requirements to activate when they are supported.
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Change subject: [RFC][WPTST] dummyflasher: enforce write protection for W25Q128FV
......................................................................
Patch Set 12: Code-Review+1
(2 comments)
File dummyflasher.c:
https://review.coreboot.org/c/flashrom/+/59074/comment/5c6359ec_9c40f4f3
PS10, Line 264: /* XXX: should data->erase_to_zero be taken into account here? */
> It does look like a bug to me, thanks! […]
+1, preserving the current behavior with a FIXME comment is the best option IMO.
File dummyflasher.c:
https://review.coreboot.org/c/flashrom/+/59074/comment/52613586_ce3bec06
PS12, Line 236: if (start >= data->wp_start && start < data->wp_end)
: return true;
:
: const uint32_t last = start + len - 1;
: return (last >= data->wp_start && last < data->wp_end);
These two tests can be combined as:
const uint32_t last = start + len - 1;
return (start < data->wp_end && last >= data->wp_start);
Actually they need to combined to catch the theoretical case where the region being written strictly contains the protection region. Although that isn't an issue for now since most chips only have protection regions at one end of address space.
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Change subject: [RFC][WPTST] dummyflasher: add SR2 emulation harness
......................................................................
Patch Set 12:
(3 comments)
File dummyflasher.c:
https://review.coreboot.org/c/flashrom/+/59072/comment/ea9c0f0f_75e347b1
PS12, Line 45: uint8_t emu_status;
: uint8_t emu_status2;
Can these be an array? i.e. `uint8_t emu_status[2];`
https://review.coreboot.org/c/flashrom/+/59072/comment/027c37f9_06dd093b
PS12, Line 164: int
Can we use `enum flash_reg` to represent the register?
Also maybe add _mask to the function's name, i.e. `get_status_ro_bit_mask()`
https://review.coreboot.org/c/flashrom/+/59072/comment/cd392bc0_68aacf0b
PS12, Line 337: if (writecnt == 3) {
I think this should check a flag in emu_data to check if the supports extended WRSR instructions.
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