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I'd like you to reexamine a change. Please visit
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Change subject: [RFC][OTP] cli_classic: add options for managing OTP regions
......................................................................
[RFC][OTP] cli_classic: add options for managing OTP regions
New actions operate on OTP region specified by `--otp-region`, which is
a required option if there is more than one OTP region, otherwise it
can be omitted. Region numbering starts at 1.
All actions can be combined with `--otp-status`, which is processed
last and thus can print new state of the OTP.
Change-Id: If77694e3b1c453b3fc0561da7a9eefdbce4fbb2b
Signed-off-by: Hatim Kanchwala <hatim at hatimak.me>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M cli_classic.c
M flashrom.8.tmpl
2 files changed, 290 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/07/59407/11
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Hello build bot (Jenkins), Nico Huber, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59709
to look at the new patch set (#7).
Change subject: [RFC][OTP] spi25_statusreg: support reading/writing security register
......................................................................
[RFC][OTP] spi25_statusreg: support reading/writing security register
Not to be confused with "secure registers" of OTP.
Security register is a dedicated status register for security-related
bits. You don't write its value directly, issuing corresponding write
command with no data just sets OTP bit to 1 automatically.
No WREN is necessary, but at least some datasheets indicate BUSY state
after write command.
Unlike cases where OTP bit is part of SR and can only be written while
in OTP mode, security register can only be written outside of the mode.
Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M flash.h
M spi.h
M spi25_statusreg.c
3 files changed, 58 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/59709/7
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Hello build bot (Jenkins), Nico Huber, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59710
to look at the new patch set (#7).
Change subject: [RFC][OTP] dummyflasher: implement SCUR and OTP for MX25L6436
......................................................................
[RFC][OTP] dummyflasher: implement SCUR and OTP for MX25L6436
The chip has OTP mode, but state of OTP is stored in a security
register.
Additions:
* spi_scur parameter for dummyflasher to configure initial state of
security register
* commands for entering/leaving OTP mode (ENSO, EXSO)
* commands for reading/writing secure register (RDSCUR, WRSCUR)
Change-Id: I13716d597d305351ec27d532e9020615c397693a
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M dummyflasher.c
M flashrom.8.tmpl
M spi.h
3 files changed, 84 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/10/59710/7
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Hello build bot (Jenkins), Nico Huber, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59712
to look at the new patch set (#7).
Change subject: [RFC][OTP] flashchips,otp: support MX25L6436E "family"
......................................................................
[RFC][OTP] flashchips,otp: support MX25L6436E "family"
Also includes MX25L6445E, MX25L6465E, MX25L6473E and MX25L6473F.
It's emulated by dummy flasher and will be used in tests.
Change-Id: I7e9dbef8632d8a1ef9322286b5fb1c0b47e8007e
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M flashchips.c
M otp.h
M otp_layouts.c
3 files changed, 23 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/12/59712/7
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Hello build bot (Jenkins), Nico Huber, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59072
to look at the new patch set (#14).
Change subject: [RFC][WPTST] dummyflasher: add SR2 emulation harness
......................................................................
[RFC][WPTST] dummyflasher: add SR2 emulation harness
Prepare everything for emulating SR2 for chips that have it.
This is needed for accessing second SRP bit which is involved in write
protection. The emulated register doesn't affect anything yet and will
be tested by write-protection tests.
Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M dummyflasher.c
M flashrom.8.tmpl
2 files changed, 76 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/59072/14
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59075 )
Change subject: [RFC][WPTST] tests: test write protection
......................................................................
Patch Set 14:
(3 comments)
Patchset:
PS13:
> You need to explain what have you done in the latest patchset :) I was looking into diffs between PS […]
All changes are side-effects of rebasing onto latest WP patches which now don't support "power cycle" and "permanent" kinds of write protection.
File tests/chip_wp.c:
https://review.coreboot.org/c/flashrom/+/59075/comment/798f0c1b_2b064363
PS13, Line 260: 1
> This is probably because I removed support for setting power cycle / permanent protection in a recen […]
Yes, I just adjusted tests to account for changes in WP implementation.
https://review.coreboot.org/c/flashrom/+/59075/comment/dd553d44_bfd47639
PS13, Line 390: /* Protect first 4 KiB. */
> The comment has changed to opposite meaning, but range remains the same? Maybe I am missing somethin […]
Thanks, I forgot to update values to match what actually happens. The two ranges are complements of one another and CMP bit is not set here, that's why tests pass either way. The reason CMP isn't set is that it resides in SR2 which is written after SR1 and by that time WP is active and SR2 can't be changed due to hwwp=yes. This is a side-effect of having to specify state of WP pin before configuring WP.
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59074 )
Change subject: [RFC][WPTST] dummyflasher: enforce write protection for W25Q128FV
......................................................................
Patch Set 13:
(3 comments)
Patchset:
PS12:
> If this patch completes wp emulation in dummyflasher, can it be tested from command line? I mean doi […]
Done
File dummyflasher.c:
https://review.coreboot.org/c/flashrom/+/59074/comment/3ef96841_8ee69399
PS10, Line 264: /* XXX: should data->erase_to_zero be taken into account here? */
> +1, preserving the current behavior with a FIXME comment is the best option IMO.
Done
File dummyflasher.c:
https://review.coreboot.org/c/flashrom/+/59074/comment/fd69b4c6_2cb376df
PS12, Line 236: if (start >= data->wp_start && start < data->wp_end)
: return true;
:
: const uint32_t last = start + len - 1;
: return (last >= data->wp_start && last < data->wp_end);
> These two tests can be combined as: […]
Thanks, done.
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