November 2021 - flashrom-gerrit

Change in flashrom[master]: chipset_enable.c: Mark Intel Z390 as DEP
by Angel Pons (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Angel Pons. Angel Pons has uploaded a new patch set (#4) to the change originally created by Melvyn. ( https://review.coreboot.org/c/flashrom/+/58774 ) Change subject: chipset_enable.c: Mark Intel Z390 as DEP ...................................................................... chipset_enable.c: Mark Intel Z390 as DEP Tested read/write on GIGABYTE Z390 AORUS MASTER, incl. ME region with me_cleaner. Change-Id: If14d45c144bb32a1d1046185d4476ea29e4d0912 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Signed-off-by: melvyn2 <melvyn2(a)brcok.tk> --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/74/58774/4 -- To view, visit https://review.coreboot.org/c/flashrom/+/58774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If14d45c144bb32a1d1046185d4476ea29e4d0912 Gerrit-Change-Number: 58774 Gerrit-PatchSet: 4 Gerrit-Owner: Melvyn <melvyn2(a)brcok.tk> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: ichspi: Extract initialisation of swseq and hwseq into a function
by Anastasia Klimchuk (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Nico Huber, Edward O'Callaghan, Angel Pons. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58737 ) Change subject: ichspi: Extract initialisation of swseq and hwseq into a function ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Update: testing of the change is in progress. There are two flows that I want to test, flows correspond to init_ich7_spi and init_ich_default. I need devices with two different chipsets, and I have so far only found one (init_ich_default). For chipset which runs through init_ich_default, I tested all operations: probe->read->verify->erase->write->reboot and all successful. So at the moment one half of the patch is tested. I am currently looking for device with chipset to run through init_ich7_spi, but this is harder than I hoped :( I really want to test init_ich7_spi because I refactored long init function and moved initialisation of hwseq/swseq, I need to confirm it works after my changes. -- To view, visit https://review.coreboot.org/c/flashrom/+/58737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7d62b1b380e497b82dcae1284d752204cc541bd3 Gerrit-Change-Number: 58737 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 06:51:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: chipset_enable.c: Mark Intel Z390 as DEP
by Melvyn (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Angel Pons. Melvyn has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58774 ) Change subject: chipset_enable.c: Mark Intel Z390 as DEP ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/58774/comment/754ebce3_e0e3ffe5 PS3, Line 12: melvyn2 > I might be able to sign off this patch. That would be great, let me know what needs to be done on my end. -- To view, visit https://review.coreboot.org/c/flashrom/+/58774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If14d45c144bb32a1d1046185d4476ea29e4d0912 Gerrit-Change-Number: 58774 Gerrit-PatchSet: 3 Gerrit-Owner: Melvyn <melvyn2(a)brcok.tk> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 06:20:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Melvyn <melvyn2(a)brcok.tk> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in flashrom[master]: [RFC] tests: add test of write protection
by Sergii Dmytruk (Code Review) 09 Nov '21

09 Nov '21

Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/59075 ) Change subject: [RFC] tests: add test of write protection ...................................................................... [RFC] tests: add test of write protection Tests both WP implementation and its emulation in dummy programmer. Change-Id: I49af7f6d173eb4c56c22d80b01a473b8c499c0f8 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M tests/meson.build M tests/tests.c M tests/tests.h A tests/write_protection.c 4 files changed, 254 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/75/59075/1 diff --git a/tests/meson.build b/tests/meson.build index 30b1e78..bb08f5a 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -23,6 +23,7 @@ 'init_shutdown.c', 'layout.c', 'chip.c', + 'write_protection.c', ] mocks = [ diff --git a/tests/tests.c b/tests/tests.c index d3df356..457bf26 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -346,5 +346,13 @@ }; ret |= cmocka_run_group_tests_name("chip.c tests", chip_tests, NULL, NULL); + const struct CMUnitTest write_protection_tests[] = { + cmocka_unit_test(setup_wp_dummyflasher_test_failure), + cmocka_unit_test(setup_wp_dummyflasher_test_success), + cmocka_unit_test(full_chip_erase_with_wp_dummyflasher_test_failure), + cmocka_unit_test(partial_chip_erase_with_wp_dummyflasher_test_success), + }; + ret |= cmocka_run_group_tests_name("write_protection.c tests", write_protection_tests, NULL, NULL); + return ret; } diff --git a/tests/tests.h b/tests/tests.h index c142b45..8d08a09 100644 --- a/tests/tests.h +++ b/tests/tests.h @@ -62,4 +62,10 @@ void read_chip_test_success(void **state); void read_chip_with_dummyflasher_test_success(void **state); +/* write_protection.c */ +void setup_wp_dummyflasher_test_failure(void **state); +void setup_wp_dummyflasher_test_success(void **state); +void full_chip_erase_with_wp_dummyflasher_test_failure(void **state); +void partial_chip_erase_with_wp_dummyflasher_test_success(void **state); + #endif /* TESTS_H */ diff --git a/tests/write_protection.c b/tests/write_protection.c new file mode 100644 index 0000000..fca9e9f --- /dev/null +++ b/tests/write_protection.c @@ -0,0 +1,239 @@ +/* + * This file is part of the flashrom project. + * + * Copyright 2021 3mdeb Embedded Systems Consulting + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <include/test.h> +#include <stdio.h> +#include <string.h> + +#include "chipdrivers.h" +#include "flash.h" +#include "programmer.h" +#include "writeprotect.h" + +/* + * No mocking. Using WP emulation in dummy programmer. + */ + +static void setup_chip(struct flashrom_flashctx *flash, struct flashrom_layout **layout, + struct flashchip *chip, const char *programmer_param) +{ + flash->chip = chip; + + printf("Creating layout with one included region... "); + assert_int_equal(0, flashrom_layout_new(layout)); + assert_int_equal(0, flashrom_layout_add_region(*layout, 0, 0xfff, "head")); + assert_int_equal(0, flashrom_layout_add_region(*layout, 0x1000, chip->total_size * KiB - 1, "tail")); + + flashrom_layout_set(flash, *layout); + printf("done\n"); + + printf("Dummyflasher initialising with param=\"%s\"... ", programmer_param); + assert_int_equal(0, programmer_init(&programmer_dummy, programmer_param)); + /* Assignment below normally happens while probing, but this test is not probing. */ + flash->mst = &registered_masters[0]; + printf("done\n"); +} + +static void teardown(struct flashrom_layout **layout) +{ + printf("Dummyflasher shutdown... "); + assert_int_equal(0, programmer_shutdown()); + printf("done\n"); + + printf("Releasing layout... "); + flashrom_layout_release(*layout); + printf("done\n"); +} + +/* Setup the struct for W25Q128.V, all values come from flashchips.c */ +static const struct flashchip chip_W25Q128_V = { + .vendor = "aklm&dummyflasher", + .total_size = 16 * 1024, + .tested = TEST_OK_PREW, + .read = spi_chip_read, + .write = spi_chip_write_256, + .unlock = spi_disable_blockprotect, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | + FEATURE_WRSR2 | FEATURE_RDSR2, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .reg_bits = + { + .srp = {{STATUS1, 7, RW}, {STATUS2, 0, RW}}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = decode_range_w25, +}; + +void setup_wp_dummyflasher_test_failure(void **state) +{ + (void) state; /* unused */ + + struct flashrom_flashctx flash = { 0 }; + struct flashrom_layout *layout; + struct flashchip mock_chip = chip_W25Q128_V; + + struct wp_range range = { .chip_len = mock_chip.total_size * 1024 }; + + char *param_dup = strdup("bus=spi,emulate=W25Q128FV,wp=no"); + + setup_chip(&flash, &layout, &mock_chip, param_dup); + assert_int_equal(0, flashrom_layout_include_region(layout, "head")); + assert_int_equal(0, flashrom_layout_include_region(layout, "tail")); + + /* Invalid range. */ + range.start = 0x1000; + range.len = 0x1000; + assert_int_equal(1, wp_set_range(&flash, range)); + + teardown(&layout); + + free(param_dup); +} + +void setup_wp_dummyflasher_test_success(void **state) +{ + (void) state; /* unused */ + + struct flashrom_flashctx flash = { 0 }; + struct flashrom_layout *layout; + struct flashchip mock_chip = chip_W25Q128_V; + + enum wp_mode mode; + struct wp_range range = { .chip_len = mock_chip.total_size * 1024 }; + + char *param_dup = strdup("bus=spi,emulate=W25Q128FV,wp=no"); + + setup_chip(&flash, &layout, &mock_chip, param_dup); + assert_int_equal(0, flashrom_layout_include_region(layout, "head")); + assert_int_equal(0, flashrom_layout_include_region(layout, "tail")); + + assert_true(wp_supported(&flash)); + + /* Use first 4 KiB for a range. */ + range.len = 0x1000; + assert_int_equal(0, wp_set_range(&flash, range)); + + /* Change range to last 4 KiB. */ + range.start = 0x00fff000; + assert_int_equal(0, wp_set_range(&flash, range)); + + /* Check initial mode. */ + assert_int_equal(0, wp_get_mode(&flash, &mode)); + assert_int_equal(WP_MODE_DISABLED, mode); + + /* Switch modes. */ + assert_int_equal(0, wp_set_mode(&flash, WP_MODE_HARDWARE)); + assert_int_equal(0, wp_set_mode(&flash, WP_MODE_DISABLED)); + assert_int_equal(0, wp_set_mode(&flash, WP_MODE_POWER_CYCLE)); + assert_int_equal(1, wp_set_mode(&flash, WP_MODE_PERMANENT)); + + /* Check final mode. */ + assert_int_equal(0, wp_get_mode(&flash, &mode)); + assert_int_equal(WP_MODE_POWER_CYCLE, mode); + + teardown(&layout); + + free(param_dup); +} + +void full_chip_erase_with_wp_dummyflasher_test_failure(void **state) +{ + (void) state; /* unused */ + + struct flashrom_flashctx flash = { 0 }; + struct flashrom_layout *layout; + struct flashchip mock_chip = chip_W25Q128_V; + + char *param_dup = strdup("bus=spi,emulate=W25Q128FV,wp=yes"); + + setup_chip(&flash, &layout, &mock_chip, param_dup); + assert_int_equal(0, flashrom_layout_include_region(layout, "head")); + assert_int_equal(0, flashrom_layout_include_region(layout, "tail")); + + /* Write protection takes effect only after changing SRP values. */ + printf("Erase chip operation started.\n"); + assert_int_equal(0, do_erase(&flash)); + printf("Erase chip operation done.\n"); + + /* Protect first 4 KiB. */ + struct wp_range range = { + .chip_len = mock_chip.total_size * 1024, + .start = 0, + .len = 0x1000, + }; + assert_int_equal(0, wp_set_range(&flash, range)); + assert_int_equal(0, wp_set_mode(&flash, WP_MODE_HARDWARE)); + + /* Try erasing the chip again. */ + printf("Erase chip operation started.\n"); + assert_int_equal(1, do_erase(&flash)); + printf("Erase chip operation done.\n"); + + teardown(&layout); + + free(param_dup); +} + +void partial_chip_erase_with_wp_dummyflasher_test_success(void **state) +{ + (void) state; /* unused */ + + struct flashrom_flashctx flash = { 0 }; + struct flashrom_layout *layout; + struct flashchip mock_chip = chip_W25Q128_V; + + char *param_dup = strdup("bus=spi,emulate=W25Q128FV,wp=yes"); + + setup_chip(&flash, &layout, &mock_chip, param_dup); + assert_int_equal(0, flashrom_layout_include_region(layout, "head")); + + /* Protect everything but first 4 KiB. */ + struct wp_range range = { + .chip_len = mock_chip.total_size * 1024, + .start = 0x1000, + .len = mock_chip.total_size * 1024 - 0x1000, + }; + assert_int_equal(0, wp_set_range(&flash, range)); + assert_int_equal(0, wp_set_mode(&flash, WP_MODE_POWER_CYCLE)); + + printf("Erase chip operation started.\n"); + assert_int_equal(0, do_erase(&flash)); + printf("Erase chip operation done.\n"); + + teardown(&layout); + + free(param_dup); +} -- To view, visit https://review.coreboot.org/c/flashrom/+/59075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I49af7f6d173eb4c56c22d80b01a473b8c499c0f8 Gerrit-Change-Number: 59075 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] dummyflasher: write protection for W25Q128FV
by Sergii Dmytruk (Code Review) 09 Nov '21

09 Nov '21

Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/59074 ) Change subject: [RFC] dummyflasher: write protection for W25Q128FV ...................................................................... [RFC] dummyflasher: write protection for W25Q128FV Start taking bits related to write protection into account. Also add "wp" parameter for dummy programmer that sets state of WP pin. Change-Id: I9fd1417f941186391bd213bd355530143c8f04a0 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M dummyflasher.c M flashrom.8.tmpl 2 files changed, 159 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/74/59074/1 diff --git a/dummyflasher.c b/dummyflasher.c index bb47c3c..f355d7e 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -25,6 +25,7 @@ #include "programmer.h" #include "flashchips.h" #include "spi.h" +#include "writeprotect.h" enum emu_chip { EMULATE_NONE, @@ -60,6 +61,11 @@ unsigned int spi_blacklist_size; unsigned int spi_ignorelist_size; + bool wp; /* state of hardware write protection */ + /* wp_start == wp_end when write-protection is disabled */ + uint32_t wp_start; + uint32_t wp_end; + unsigned int spi_write_256_chunksize; uint8_t *flashchip_contents; }; @@ -166,7 +172,14 @@ uint8_t ro_bits = (status_reg == 1 ? SPI_SR_WEL | SPI_SR_WIP : 0); if (data->emu_chip == EMULATE_WINBOND_W25Q128FV) { - if (status_reg == 2) { + const bool srp0 = (data->emu_status >> 7); + const bool srp1 = (data->emu_status2 & 1); + + const bool wp_active = (srp1 || (srp0 && data->wp)); + + if (wp_active) { + ro_bits = 0xff; + } else if (status_reg == 2) { /* SUS1 (bit_7) and (R) (bit_2). */ ro_bits = 0x84; /* Once any of the lock bits (LB[1..3]) are set, they @@ -180,6 +193,81 @@ return ro_bits; } +static void update_write_protection(struct emu_data *data) +{ + if (data->emu_chip != EMULATE_WINBOND_W25Q128FV) + return; + + const struct wp_chip_state wpst = { + .srp_bit_count = 2, + .srp = {data->emu_status >> 7, data->emu_status2 & 1}, + + .bp_bit_count = 3, + .bp = + { + (data->emu_status >> 2) & 1, + (data->emu_status >> 3) & 1, + (data->emu_status >> 4) & 1 + }, + + .tb_bit_present = true, + .tb = (data->emu_status >> 5) & 1, + + .sec_bit_present = true, + .sec = (data->emu_status >> 6) & 1, + + .cmp_bit_present = true, + .cmp = (data->emu_status2 >> 6) & 1, + }; + + struct wp_range range = { .chip_len = data->emu_chip_size }; + decode_range_w25(&wpst, &range); + + data->wp_start = range.start; + data->wp_end = range.start + range.len; +} + +/* Checks whether range intersects a write-protected area of the flash if one is + * defined. */ +static bool is_write_protected(const struct emu_data *data, uint32_t start, uint32_t len) +{ + if (len == 0) + return false; + + if (start >= data->wp_start && start < data->wp_end) + return true; + + const uint32_t last = start + len - 1; + return (last >= data->wp_start && last < data->wp_end); +} + +/* Returns non-zero on error. */ +static int write_flash_part(struct emu_data *data, uint32_t start, uint32_t len, const uint8_t *buf) +{ + if (is_write_protected(data, start, len)) { + msg_perr("At least part of the write range is write protected!\n"); + return 1; + } + + memcpy(data->flashchip_contents + start, buf, len); + data->emu_modified = 1; + return 0; +} + +/* Returns non-zero on error. */ +static int erase_flash_part(struct emu_data *data, uint32_t start, uint32_t len) +{ + if (is_write_protected(data, start, len)) { + msg_perr("At least part of the erase range is write protected!\n"); + return 1; + } + + /* XXX: should data->erase_to_zero be taken into account here? */ + memset(data->flashchip_contents + start, 0xff, len); + data->emu_modified = 1; + return 0; +} + static int emulate_spi_chip_response(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, @@ -358,6 +446,8 @@ msg_pdbg2("WRSR wrote 0x%02x%02x.\n", data->emu_status2, data->emu_status); else msg_pdbg2("WRSR wrote 0x%02x.\n", data->emu_status); + + update_write_protection(data); break; case JEDEC_WRSR2: if (data->emu_status_len < 2) @@ -370,6 +460,8 @@ ro_bits = get_status_ro_bits(data, 2); data->emu_status2 &= ro_bits; data->emu_status2 |= (writearr[1] & ~ro_bits); + + update_write_protection(data); break; case JEDEC_READ: offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; @@ -397,8 +489,10 @@ msg_perr("Max BYTE PROGRAM size exceeded!\n"); return 1; } - memcpy(data->flashchip_contents + offs, writearr + 4, writecnt - 4); - data->emu_modified = 1; + if (write_flash_part(data, offs, writecnt - 4, writearr + 4)) { + msg_perr("Failed to program flash!\n"); + return 1; + } break; case JEDEC_BYTE_PROGRAM_4BA: offs = writearr[1] << 24 | writearr[2] << 16 | writearr[3] << 8 | writearr[4]; @@ -412,8 +506,10 @@ msg_perr("Max BYTE PROGRAM size exceeded!\n"); return 1; } - memcpy(data->flashchip_contents + offs, writearr + 5, writecnt - 5); - data->emu_modified = 1; + if (write_flash_part(data, offs, writecnt - 5, writearr + 5)) { + msg_perr("Failed to program flash!\n"); + return 1; + } break; case JEDEC_AAI_WORD_PROGRAM: if (!data->emu_max_aai_size) @@ -434,7 +530,10 @@ writearr[3]; /* Truncate to emu_chip_size. */ aai_offs %= data->emu_chip_size; - memcpy(data->flashchip_contents + aai_offs, writearr + 4, 2); + if (write_flash_part(data, aai_offs, 2, writearr + 4)) { + msg_perr("Failed to program flash!\n"); + return 1; + } aai_offs += 2; } else { if (writecnt < JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE) { @@ -447,10 +546,12 @@ "too long!\n"); return 1; } - memcpy(data->flashchip_contents + aai_offs, writearr + 1, 2); + if (write_flash_part(data, aai_offs, 2, writearr + 1)) { + msg_perr("Failed to program flash!\n"); + return 1; + } aai_offs += 2; } - data->emu_modified = 1; break; case JEDEC_WRDI: if (data->emu_max_aai_size) @@ -471,8 +572,10 @@ if (offs & (data->emu_jedec_se_size - 1)) msg_pdbg("Unaligned SECTOR ERASE 0x20: 0x%x\n", offs); offs &= ~(data->emu_jedec_se_size - 1); - memset(data->flashchip_contents + offs, 0xff, data->emu_jedec_se_size); - data->emu_modified = 1; + if (erase_flash_part(data, offs, data->emu_jedec_se_size)) { + msg_perr("Failed to erase flash!\n"); + return 1; + } break; case JEDEC_BE_52: if (!data->emu_jedec_be_52_size) @@ -489,8 +592,10 @@ if (offs & (data->emu_jedec_be_52_size - 1)) msg_pdbg("Unaligned BLOCK ERASE 0x52: 0x%x\n", offs); offs &= ~(data->emu_jedec_be_52_size - 1); - memset(data->flashchip_contents + offs, 0xff, data->emu_jedec_be_52_size); - data->emu_modified = 1; + if (erase_flash_part(data, offs, data->emu_jedec_be_52_size)) { + msg_perr("Failed to erase flash!\n"); + return 1; + } break; case JEDEC_BE_D8: if (!data->emu_jedec_be_d8_size) @@ -507,8 +612,10 @@ if (offs & (data->emu_jedec_be_d8_size - 1)) msg_pdbg("Unaligned BLOCK ERASE 0xd8: 0x%x\n", offs); offs &= ~(data->emu_jedec_be_d8_size - 1); - memset(data->flashchip_contents + offs, 0xff, data->emu_jedec_be_d8_size); - data->emu_modified = 1; + if (erase_flash_part(data, offs, data->emu_jedec_be_d8_size)) { + msg_perr("Failed to erase flash!\n"); + return 1; + } break; case JEDEC_CE_60: if (!data->emu_jedec_ce_60_size) @@ -523,8 +630,10 @@ } /* JEDEC_CE_60_OUTSIZE is 1 (no address) -> no offset. */ /* emu_jedec_ce_60_size is emu_chip_size. */ - memset(data->flashchip_contents, 0xff, data->emu_jedec_ce_60_size); - data->emu_modified = 1; + if (erase_flash_part(data, 0, data->emu_jedec_ce_60_size)) { + msg_perr("Failed to erase flash!\n"); + return 1; + } break; case JEDEC_CE_C7: if (!data->emu_jedec_ce_c7_size) @@ -539,8 +648,10 @@ } /* JEDEC_CE_C7_OUTSIZE is 1 (no address) -> no offset. */ /* emu_jedec_ce_c7_size is emu_chip_size. */ - memset(data->flashchip_contents, 0xff, data->emu_jedec_ce_c7_size); - data->emu_modified = 1; + if (erase_flash_part(data, 0, data->emu_jedec_ce_c7_size)) { + msg_perr("Failed to erase flash!\n"); + return 1; + } break; case JEDEC_SFDP: if (data->emu_chip != EMULATE_MACRONIX_MX25L6436) @@ -850,6 +961,21 @@ free(tmp); } + tmp = extract_programmer_param("wp"); + if (tmp) { + if (!strcmp(tmp, "yes")) { + msg_pdbg("Emulated chip will have WP enabled\n"); + data->wp = true; + } else if (!strcmp(tmp, "no")) { + msg_pdbg("Emulated chip will have WP disabled\n"); + } else { + msg_perr("wp can be \"yes\" or \"no\"\n"); + free(tmp); + return 1; + } + free(tmp); + } + tmp = extract_programmer_param("emulate"); if (!tmp) { msg_pdbg("Not emulating any flash chip.\n"); diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 989d677..000a67a 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -693,6 +693,8 @@ .sp .RB "* Macronix " MX25L6436 " SPI flash chip (8192 kB, RDID, SFDP)" .sp +.RB "* Winbond " W25Q128FV " SPI flash chip (16384 kB, RDID)" +.sp .RB "* Dummy vendor " VARIABLE_SIZE " SPI flash chip (configurable size, page write)" .sp Example: @@ -779,6 +781,19 @@ syntax where .B content is an 8-bit hexadecimal value. +.sp +.TP +.B Write protection +.sp +Chips with emulated WP: W25Q128FV. +.sp +You can simulate state of hardware protection pin (WP) with the +.sp +.B " flashrom -p dummy:wp=state" +.sp +syntax where +.B state +is "yes" or "no" (default value). .SS .BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ -- To view, visit https://review.coreboot.org/c/flashrom/+/59074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9fd1417f941186391bd213bd355530143c8f04a0 Gerrit-Change-Number: 59074 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] dummyflasher: SR2 for W25Q128FV
by Sergii Dmytruk (Code Review) 09 Nov '21

09 Nov '21

Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/59073 ) Change subject: [RFC] dummyflasher: SR2 for W25Q128FV ...................................................................... [RFC] dummyflasher: SR2 for W25Q128FV W25Q128FV has SR3 too, by the way. Change-Id: I79f9b4a0b604663d3288ad70dcbe3ea4075dede5 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M dummyflasher.c 1 file changed, 20 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/59073/1 diff --git a/dummyflasher.c b/dummyflasher.c index 7ef4a25..bb47c3c 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -161,9 +161,23 @@ } /* Status registers are base 1. */ -static uint8_t get_status_ro_bits(int status_reg) +static uint8_t get_status_ro_bits(const struct emu_data *data, int status_reg) { - return (status_reg == 1 ? SPI_SR_WEL | SPI_SR_WIP : 0); + uint8_t ro_bits = (status_reg == 1 ? SPI_SR_WEL | SPI_SR_WIP : 0); + + if (data->emu_chip == EMULATE_WINBOND_W25Q128FV) { + if (status_reg == 2) { + /* SUS1 (bit_7) and (R) (bit_2). */ + ro_bits = 0x84; + /* Once any of the lock bits (LB[1..3]) are set, they + * can't be unset. */ + ro_bits |= data->emu_status2 & (1 << 3); + ro_bits |= data->emu_status2 & (1 << 4); + ro_bits |= data->emu_status2 & (1 << 5); + } + } + + return ro_bits; } static int emulate_spi_chip_response(unsigned int writecnt, @@ -331,11 +345,11 @@ } /* FIXME: add some reasonable simulation of the busy flag */ - ro_bits = get_status_ro_bits(1); + ro_bits = get_status_ro_bits(data, 1); data->emu_status &= ro_bits; data->emu_status |= (writearr[1] & ~ro_bits); if (writecnt == 3) { - ro_bits = get_status_ro_bits(2); + ro_bits = get_status_ro_bits(data, 2); data->emu_status2 &= ro_bits; data->emu_status2 |= (writearr[2] & ~ro_bits); } @@ -353,7 +367,7 @@ break; } - ro_bits = get_status_ro_bits(2); + ro_bits = get_status_ro_bits(data, 2); data->emu_status2 &= ro_bits; data->emu_status2 |= (writearr[1] & ~ro_bits); break; @@ -904,7 +918,7 @@ data->emu_chip_size = 16 * 1024 * 1024; data->emu_max_byteprogram_size = 256; data->emu_max_aai_size = 0; - data->emu_status_len = 1; + data->emu_status_len = 2; data->emu_jedec_se_size = 4 * 1024; data->emu_jedec_be_52_size = 32 * 1024; data->emu_jedec_be_d8_size = 64 * 1024; -- To view, visit https://review.coreboot.org/c/flashrom/+/59073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I79f9b4a0b604663d3288ad70dcbe3ea4075dede5 Gerrit-Change-Number: 59073 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] dummyflasher: support emulation of SR2
by Sergii Dmytruk (Code Review) 09 Nov '21

09 Nov '21

Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/59072 ) Change subject: [RFC] dummyflasher: support emulation of SR2 ...................................................................... [RFC] dummyflasher: support emulation of SR2 This is needed for accessing second SRP bit which is involved in write protection. Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M dummyflasher.c 1 file changed, 54 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/59072/1 diff --git a/dummyflasher.c b/dummyflasher.c index 2311576..7ef4a25 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -43,6 +43,8 @@ int erase_to_zero; int emu_modified; /* is the image modified since reading it? */ uint8_t emu_status; + uint8_t emu_status2; + uint8_t emu_status_len; /* number of emulated status bytes */ /* If "freq" parameter is passed in from command line, commands will delay * for this period before returning. */ unsigned long int delay_us; @@ -158,6 +160,12 @@ return; } +/* Status registers are base 1. */ +static uint8_t get_status_ro_bits(int status_reg) +{ + return (status_reg == 1 ? SPI_SR_WEL | SPI_SR_WIP : 0); +} + static int emulate_spi_chip_response(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, @@ -165,6 +173,7 @@ struct emu_data *data) { unsigned int offs, i, toread; + uint8_t ro_bits; static int unsigned aai_offs; const unsigned char sst25vf040_rems_response[2] = {0xbf, 0x44}; const unsigned char sst25vf032b_rems_response[2] = {0xbf, 0x4a}; @@ -306,6 +315,10 @@ case JEDEC_RDSR: memset(readarr, data->emu_status, readcnt); break; + case JEDEC_RDSR2: + if (data->emu_status_len >= 2) + memset(readarr, data->emu_status2, readcnt); + break; /* FIXME: this should be chip-specific. */ case JEDEC_EWSR: case JEDEC_WREN: @@ -316,9 +329,33 @@ msg_perr("WRSR attempted, but WEL is 0!\n"); break; } + /* FIXME: add some reasonable simulation of the busy flag */ - data->emu_status = writearr[1] & ~SPI_SR_WIP; - msg_pdbg2("WRSR wrote 0x%02x.\n", data->emu_status); + ro_bits = get_status_ro_bits(1); + data->emu_status &= ro_bits; + data->emu_status |= (writearr[1] & ~ro_bits); + if (writecnt == 3) { + ro_bits = get_status_ro_bits(2); + data->emu_status2 &= ro_bits; + data->emu_status2 |= (writearr[2] & ~ro_bits); + } + + if (writecnt == 3) + msg_pdbg2("WRSR wrote 0x%02x%02x.\n", data->emu_status2, data->emu_status); + else + msg_pdbg2("WRSR wrote 0x%02x.\n", data->emu_status); + break; + case JEDEC_WRSR2: + if (data->emu_status_len < 2) + break; + if (!(data->emu_status & SPI_SR_WEL)) { + msg_perr("WRSR2 attempted, but WEL is 0!\n"); + break; + } + + ro_bits = get_status_ro_bits(2); + data->emu_status2 &= ro_bits; + data->emu_status2 |= (writearr[1] & ~ro_bits); break; case JEDEC_READ: offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; @@ -811,6 +848,7 @@ data->emu_chip_size = 128 * 1024; data->emu_max_byteprogram_size = 128; data->emu_max_aai_size = 0; + data->emu_status_len = 1; data->emu_jedec_se_size = 0; data->emu_jedec_be_52_size = 0; data->emu_jedec_be_d8_size = 32 * 1024; @@ -824,6 +862,7 @@ data->emu_chip_size = 512 * 1024; data->emu_max_byteprogram_size = 1; data->emu_max_aai_size = 0; + data->emu_status_len = 1; data->emu_jedec_se_size = 4 * 1024; data->emu_jedec_be_52_size = 32 * 1024; data->emu_jedec_be_d8_size = 0; @@ -837,6 +876,7 @@ data->emu_chip_size = 4 * 1024 * 1024; data->emu_max_byteprogram_size = 1; data->emu_max_aai_size = 2; + data->emu_status_len = 1; data->emu_jedec_se_size = 4 * 1024; data->emu_jedec_be_52_size = 32 * 1024; data->emu_jedec_be_d8_size = 64 * 1024; @@ -850,6 +890,7 @@ data->emu_chip_size = 8 * 1024 * 1024; data->emu_max_byteprogram_size = 256; data->emu_max_aai_size = 0; + data->emu_status_len = 1; data->emu_jedec_se_size = 4 * 1024; data->emu_jedec_be_52_size = 32 * 1024; data->emu_jedec_be_d8_size = 64 * 1024; @@ -863,6 +904,7 @@ data->emu_chip_size = 16 * 1024 * 1024; data->emu_max_byteprogram_size = 256; data->emu_max_aai_size = 0; + data->emu_status_len = 1; data->emu_jedec_se_size = 4 * 1024; data->emu_jedec_be_52_size = 32 * 1024; data->emu_jedec_be_d8_size = 64 * 1024; @@ -927,8 +969,16 @@ return 1; } free(status); - msg_pdbg("Initial status register is set to 0x%02x.\n", - data->emu_status); + + if (data->emu_status_len == 2) { + msg_pdbg("Initial status registers:\n" + "\tSR1 is set to 0x%02x\n" + "\tSR2 is set to 0x%02x\n", + data->emu_status, data->emu_status2); + } else { + msg_pdbg("Initial status register is set to 0x%02x.\n", + data->emu_status); + } } data->flashchip_contents = malloc(data->emu_chip_size); -- To view, visit https://review.coreboot.org/c/flashrom/+/59072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59 Gerrit-Change-Number: 59072 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] flashchips: enable write-protection for W25Q128.V
by Sergii Dmytruk (Code Review) 09 Nov '21

09 Nov '21

Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/59071 ) Change subject: [RFC] flashchips: enable write-protection for W25Q128.V ...................................................................... [RFC] flashchips: enable write-protection for W25Q128.V Emulation of this chip will support WP. This and follow up patches are based on unmerged WP patches by Nikolai Artemiev: https://review.coreboot.org/c/flashrom/+/58474/7 Change-Id: Iccb69a8d3a0dd2192e2c938caddaf07b1889ed35 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M flashchips.c 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/71/59071/1 diff --git a/flashchips.c b/flashchips.c index 434c46d..b26681d 100644 --- a/flashchips.c +++ b/flashchips.c @@ -17105,7 +17105,8 @@ .page_size = 256, /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | + FEATURE_WRSR2 | FEATURE_RDSR2, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -17133,6 +17134,15 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {{STATUS1, 7, RW}, {STATUS2, 0, RW}}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = decode_range_w25, }, { -- To view, visit https://review.coreboot.org/c/flashrom/+/59071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iccb69a8d3a0dd2192e2c938caddaf07b1889ed35 Gerrit-Change-Number: 59071 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

Change in flashrom[master]: hwaccess: replace calls to pci_(r)mmio_XXX with underlaying function
by Thomas Heijligen (Code Review) 09 Nov '21

09 Nov '21

Thomas Heijligen has abandoned this change. ( https://review.coreboot.org/c/flashrom/+/59016 ) Change subject: hwaccess: replace calls to pci_(r)mmio_XXX with underlaying function ...................................................................... Abandoned Drop this for now -- To view, visit https://review.coreboot.org/c/flashrom/+/59016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iee3d3a3ba61586117b79c005a47e1bb661e21437 Gerrit-Change-Number: 59016 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in flashrom[master]: tests: Add wraps for __xstat/__fxstat variants of stat/fstat
by Anastasia Klimchuk (Code Review) 08 Nov '21

08 Nov '21

Attention is currently required from: Nico Huber, Angel Pons. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58103 ) Change subject: tests: Add wraps for __xstat/__fxstat variants of stat/fstat ...................................................................... Patch Set 6: (1 comment) Patchset: PS5: > Let's just say it hasn't started and hope for the best. :) […] Thank you for support! :) It is hard to foresee, but chances are that can be it (no more extra wraps will be needed). If anything happens, I will return back to this question. -- To view, visit https://review.coreboot.org/c/flashrom/+/58103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4c5c243acde09dc5bb6b2a14042fcd23a49707db Gerrit-Change-Number: 58103 Gerrit-PatchSet: 6 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 08 Nov 2021 23:42:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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