November 2021 - flashrom-gerrit

Change in flashrom[master]: board_enable.c: Add ME unlock function for Clevo laptops
by Michał Żygowski (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Felix Singer, Paul Menzel, Angel Pons, Arthur Heymans, Michael Niewöhner. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/56023 ) Change subject: board_enable.c: Add ME unlock function for Clevo laptops ...................................................................... Patch Set 13: (1 comment) File meson.build: https://review.coreboot.org/c/flashrom/+/56023/comment/0a0d95cb_bdcc46c1 PS12, Line 351: srcs += 'acpi_ec.c' > should go in CB:55714 You are right. Done. -- To view, visit https://review.coreboot.org/c/flashrom/+/56023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6bf1c40900aa674e3ea4f6add12dae8b73759fbb Gerrit-Change-Number: 56023 Gerrit-PatchSet: 13 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Thu, 18 Nov 2021 11:22:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in flashrom[master]: acpi_ec: Implement basic ACPI embedded controller API
by Michał Żygowski (Code Review) 18 Nov '21

18 Nov '21

Attention is currently required from: Angel Pons, Michael Niewöhner. Hello build bot (Jenkins), Nico Huber, Sergii Dmytruk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/55714 to look at the new patch set (#12). Change subject: acpi_ec: Implement basic ACPI embedded controller API ...................................................................... acpi_ec: Implement basic ACPI embedded controller API Implement basic functions to read/write EC registers and send standard ACPI EC commands. Those may prove useful in possible future implementations of embedded controllers in flashrom and are required to support EC firmware flashing on Tuxedo laptops. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Change-Id: Ie3bae8d81c80ae2f286b619e974869e3f2f4545d --- M Makefile A acpi_ec.c A acpi_ec.h M meson.build 4 files changed, 152 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/14/55714/12 -- To view, visit https://review.coreboot.org/c/flashrom/+/55714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie3bae8d81c80ae2f286b619e974869e3f2f4545d Gerrit-Change-Number: 55714 Gerrit-PatchSet: 12 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: flashrom.8.tmpl: remove outdated warning about v1.0
by Sergii Dmytruk (Code Review) 17 Nov '21

17 Nov '21

Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/59408 ) Change subject: flashrom.8.tmpl: remove outdated warning about v1.0 ...................................................................... flashrom.8.tmpl: remove outdated warning about v1.0 Change-Id: Id7e0ce412901ccb27124a9958d5ef214ab289518 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M flashrom.8.tmpl 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/59408/1 diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 3187ab8..92da460 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -70,11 +70,6 @@ TSOP48, and BGA chips, which use various protocols such as LPC, FWH, parallel flash, or SPI. .SH OPTIONS -.B IMPORTANT: -Please note that the command line interface for flashrom will change before -flashrom 1.0. Do not use flashrom in scripts or other automated tools without -checking that your flashrom version won't interpret options in a different way. -.PP You can specify one of .BR \-h ", " \-R ", " \-L ", " \-z ", " \-E ", " \-r ", " \-w ", " \-v or no operation. -- To view, visit https://review.coreboot.org/c/flashrom/+/59408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id7e0ce412901ccb27124a9958d5ef214ab289518 Gerrit-Change-Number: 59408 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] cli_classic: add options for managing OTP regions
by Sergii Dmytruk (Code Review) 17 Nov '21

17 Nov '21

Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/59407 ) Change subject: [RFC] cli_classic: add options for managing OTP regions ...................................................................... [RFC] cli_classic: add options for managing OTP regions Change-Id: If77694e3b1c453b3fc0561da7a9eefdbce4fbb2b Signed-off-by: Hatim Kanchwala <hatim at hatimak.me> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M cli_classic.c M flashrom.8.tmpl 2 files changed, 290 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/07/59407/1 diff --git a/cli_classic.c b/cli_classic.c index d69b798..3888581 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -28,6 +28,7 @@ #include "flash.h" #include "flashchips.h" #include "fmap.h" +#include "otp.h" #include "programmer.h" #include "writeprotect.h" #include "libflashrom.h" @@ -66,6 +67,12 @@ " --wp-status show write protect status\n" " --wp-range=<start>,<len> set write protect range\n" " --wp-region <region> set write protect region\n" + " --otp-status print information about OTP regions\n" + " --otp-region <otp-region> OTP region number (base 1) to operate on\n" + " --otp-read <file> read OTP region and save it to <file>\n" + " --otp-write <file> write <file> to OTP region\n" + " --otp-erase erase OTP region\n" + " --otp-lock lock OTP region\n" " --flash-name read out the detected flash name\n" " --flash-size read out the detected flash size\n" " --fmap read ROM layout from fmap embedded in ROM\n" @@ -154,6 +161,193 @@ return 0; } +/* Parses OTP region number from an option value. Returns negative number on + * parsing error. */ +static int parse_otp_region(const char *value, int nregions) +{ + if (!value) { + msg_gdbg("OTP region not specified, using default region 1.\n"); + return 0; + } + + char *endptr = NULL; + int region = strtoul(value, &endptr, 0); + if (*endptr != '\0') { + msg_gerr("Error: Invalid otp-region argument format.\n"); + return -1; + } + + if (region < 1 || region > nregions) { + msg_gerr("Error: Value of otp-region must in the range [1, %d].\n", + nregions); + return -1; + } + + return region - 1; +} + +static int print_otp_status(struct flashctx *flash) +{ + size_t nregions; + struct flashrom_otp_region regions[FLASHROM_OTP_MAX_REGIONS]; + if (flashrom_otp_get_regions(flash, regions, &nregions)) { + msg_cerr("Failed to list OTP regions of the chip.\n"); + return 1; + } + + msg_cinfo("%s contains %d OTP region%s:\n", + flash->chip->name, (int)nregions, (nregions == 0) ? "" : "s"); + + for (unsigned int i = 0; i < nregions; i++) { + msg_cinfo(" %d. %d bytes\n", i + 1, regions[i].size); + + if (regions[i].locked) + msg_cinfo(" Permanently locked and cannot be erased or written to.\n"); + else + msg_cinfo(" Not yet locked.\n"); + } + + return 0; +} + +static int otp_cli(struct flashctx *flash, int any_otp_op, + int otp_status, int otp_read, int otp_write, int otp_erase, int otp_lock, + const char *otp_region_opt, const char *filename) +{ + int ret; + + size_t nregions; + struct flashrom_otp_region regions[FLASHROM_OTP_MAX_REGIONS]; + + if (!any_otp_op) + return 0; + + if (!flashrom_otp_chip_supported(flash)) { + msg_gerr("Error: OTP support is not implemented for this flash chip.\n"); + return 1; + } + + int region = -1; + if (otp_read || otp_write || otp_erase || otp_lock) { + if (flashrom_otp_get_regions(flash, regions, &nregions)) { + msg_cerr("Error: Failed to list OTP regions of the chip.\n"); + return 1; + } + + if (nregions > 1 && !otp_region_opt) { + msg_cerr("Error: Chip contains several OTP regions, but no --otp-region given.\n"); + return 1; + } + + region = parse_otp_region(otp_region_opt, nregions); + if (region < 0) + return 1; + } + + if (otp_read) { + const uint32_t len = regions[region].size; + uint8_t *buf = calloc(len, sizeof(*buf)); + if (!buf) { + msg_gerr("Error: Memory allocation failed.\n"); + return 1; + } + msg_gdbg("Reading OTP region...\n"); + if (flashrom_otp_read(flash, region, buf, len)) { + msg_cerr("Error: Reading OTP region failed.\n"); + free(buf); + return 1; + } + + ret = write_buf_to_file(buf, len, filename); + free(buf); + if (ret) + return 1; + } + + if (otp_write) { + const uint32_t len = regions[region].size; + uint8_t *buf = calloc(len, sizeof(*buf)); + if (!buf) { + msg_gerr("Error: Memory allocation failed.\n"); + return 1; + } + + ret = read_buf_from_file(buf, len, filename); + if (ret) { + msg_gerr("Error: Reading from file \"%s\" failed.\n", filename); + free(buf); + return 1; + } + msg_gdbg("Reading form file \"%s\" complete.\n", filename); + + msg_cinfo("Erasing OTP region...\n"); + if (flashrom_otp_erase(flash, region)) { + msg_cerr("Error: Erasing OTP region failed.\n"); + free(buf); + return 1; + } + msg_cinfo("Erasing OTP region done.\n"); + + msg_cinfo("Writing OTP region...\n"); + ret = flashrom_otp_write(flash, region, buf, len); + if (ret) { + free(buf); + msg_cerr("Error: Writing OTP region failed.\n"); + return 1; + } + msg_cinfo("Writing OTP region done.\n"); + + uint8_t *verify_buf = calloc(len, sizeof(*verify_buf)); + if (!verify_buf) { + free(buf); + msg_gerr("Error: Memory allocation failed.\n"); + return 1; + } + + msg_cinfo("Verifying written OTP region...\n"); + ret = flashrom_otp_read(flash, region, verify_buf, len); + + const bool ok = (memcmp(buf, verify_buf, len) == 0); + free(verify_buf); + free(buf); + + if (ret) { + msg_gerr("Error: Reading OTP region failed.\n"); + return 1; + } + + if (!ok) { + msg_gerr("Error: Writing OTP region failed verification.\n"); + return 1; + } + + msg_cinfo("Verifying written OTP region done.\n"); + } + + if (otp_erase) { + msg_cinfo("Erasing OTP region ...\n"); + if (flashrom_otp_erase(flash, region)) { + msg_cerr("Error: Erasing OTP region failed.\n"); + return 1; + } + msg_cinfo("Erasing OTP region done.\n"); + } + + if (otp_lock) { + msg_gdbg("Trying to lock OTP region...\n"); + if (flashrom_otp_lock(flash, region)) { + msg_cerr("Error: Failed to lock OTP region %d.\n", region + 1); + return 1; + } + msg_cinfo("Successfully locked OTP region %d.\n", region + 1); + } + + if (otp_status) + return print_otp_status(flash); + + return 0; +} + int main(int argc, char *argv[]) { const struct flashchip *chip = NULL; @@ -169,6 +363,7 @@ int flash_name = 0, flash_size = 0; int set_wp_enable = 0, set_wp_disable = 0, wp_status = 0; int set_wp_range = 0, set_wp_region = 0, wp_list = 0; + int otp_status = 0, otp_read = 0, otp_write = 0, otp_erase = 0, otp_lock = 0; int read_it = 0, extract_it = 0, write_it = 0, erase_it = 0, verify_it = 0; int dont_verify_it = 0, dont_verify_all = 0, list_supported = 0, operation_specified = 0; struct flashrom_layout *layout = NULL; @@ -186,6 +381,12 @@ OPTION_WP_ENABLE, OPTION_WP_DISABLE, OPTION_WP_LIST, + OPTION_OTP_STATUS, + OPTION_OTP_REGION, + OPTION_OTP_READ, + OPTION_OTP_WRITE, + OPTION_OTP_ERASE, + OPTION_OTP_LOCK, }; int ret = 0; unsigned int wp_start = 0, wp_len = 0; @@ -217,6 +418,12 @@ {"wp-enable", optional_argument, 0, OPTION_WP_ENABLE}, {"wp-disable", 0, 0, OPTION_WP_DISABLE}, {"wp-list", 0, 0, OPTION_WP_LIST}, + {"otp-status", 0, NULL, OPTION_OTP_STATUS}, + {"otp-region", 1, NULL, OPTION_OTP_REGION}, + {"otp-read", 1, NULL, OPTION_OTP_READ}, + {"otp-write", 1, NULL, OPTION_OTP_WRITE}, + {"otp-erase", 0, NULL, OPTION_OTP_ERASE}, + {"otp-lock", 0, NULL, OPTION_OTP_LOCK}, {"list-supported", 0, NULL, 'L'}, {"list-supported-wiki", 0, NULL, 'z'}, {"programmer", 1, NULL, 'p'}, @@ -238,6 +445,7 @@ struct layout_include_args *include_args = NULL; char *wp_mode_opt = NULL; char *wp_region = NULL; + char *otp_region_opt = NULL; /* * Safety-guard against a user who has (mistakenly) closed @@ -385,6 +593,30 @@ case OPTION_WP_DISABLE: set_wp_disable = 1; break; + case OPTION_OTP_STATUS: + otp_status = 1; + break; + case OPTION_OTP_REGION: + otp_region_opt = strdup(optarg); + break; + case OPTION_OTP_READ: + cli_classic_validate_singleop(&operation_specified); + filename = strdup(optarg); + otp_read = 1; + break; + case OPTION_OTP_WRITE: + cli_classic_validate_singleop(&operation_specified); + filename = strdup(optarg); + otp_write = 1; + break; + case OPTION_OTP_ERASE: + cli_classic_validate_singleop(&operation_specified); + otp_erase = 1; + break; + case OPTION_OTP_LOCK: + cli_classic_validate_singleop(&operation_specified); + otp_lock = 1; + break; case 'L': cli_classic_validate_singleop(&operation_specified); list_supported = 1; @@ -673,9 +905,11 @@ goto out_shutdown; } + const bool any_otp_op = + otp_status || otp_read || otp_write || otp_erase || otp_lock; + if (!(read_it | write_it | verify_it | erase_it | flash_name | flash_size - | set_wp_range | set_wp_region | set_wp_enable | - set_wp_disable | wp_status | wp_list | extract_it)) { + | any_otp)) { msg_ginfo("No operations were specified.\n"); goto out_shutdown; } @@ -824,6 +1058,11 @@ goto out_release; } + ret = otp_cli(fill_flash, any_otp_op, otp_status, otp_read, otp_write, otp_erase, otp_lock, + otp_region_opt, filename); + if (ret) + goto out_release; + flashrom_flag_set(fill_flash, FLASHROM_FLAG_FORCE, !!force); #if CONFIG_INTERNAL == 1 flashrom_flag_set(fill_flash, FLASHROM_FLAG_FORCE_BOARDMISMATCH, !!force_boardmismatch); diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 126e50c..3187ab8 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -50,7 +50,12 @@ [\fB\-E\fR|\fB\-x\fR|\fB\-r\fR <file>|\fB\-w\fR <file>|\fB\-v\fR <file>] [(\fB\-l\fR <file>|\fB\-\-ifd|\fB \-\-fmap\fR|\fB\-\-fmap-file\fR <file>) [\fB\-i\fR <image>[:<file>]]] - [\fB\-n\fR] [\fB\-N\fR] [\fB\-f\fR])] + [\fB\-n\fR] [\fB\-N\fR] [\fB\-f\fR] + [\fB\-\-otp\-status\fR] [\fB\-\-otp\-region\fR <otp\-region>] + [\fB\-\-otp\-read\fR <file>| + \fB\-\-otp\-write\fR <file>| + \fB\-\-otp\-erase\fR| + \fB\-\-otp\-lock\fR]) [\fB\-V\fR[\fBV\fR[\fBV\fR]]] [\fB-o\fR <logfile>] .SH DESCRIPTION .B flashrom @@ -140,6 +145,45 @@ Extract every region defined on the layout from flash ROM chip to a file with the same name as the extracted region. .TP +.B "\-\-otp\-status" +Print details about OTP region(s) for the chip. +.TP +.B "\-\-otp\-region <region>" +Specify OTP region number (base 1) to operation on. Can be omitted if selected +chip has only one region. +.TP +.B "\-\-otp\-read <file>" +Read OTP region +.B "<otp\-region>" +of the chip and save to +.B "<file>." +.sp +Example: +.sp +.B " flashrom \-p prog \-c chip \-\-otp\-region 2 \-\-otp\-read read_otp.bin \-\-otp-status" +.sp +will read the the 2nd OTP region, save it to +.B "read_otp.bin" +and print information about all OTP regions at the end. +.TP +.B "\-\-otp\-write <file>" +Write +.B "<file>" +to OTP region +.B "<otp\-region>" +of the chip. +.TP +.B "\-\-otp\-erase" +Erase OTP region +.B "<otp\-region>" +of the chip. +.TP +.B "\-\-otp\-lock" +Lock OTP region +.B "<otp\-region>" +of the chip against any future writes (be cautious, this action is +almost always irreversible!). +.TP .B "\-V, \-\-verbose" More verbose output. This option can be supplied multiple times (max. 3 times, i.e. @@ -1551,10 +1595,10 @@ .sp Some flash chips contain OTP memory often denoted as "security registers". They usually have a capacity in the range of some bytes to a few hundred -bytes and can be used to give devices unique IDs etc. flashrom is not able -to read or write these memories and may therefore not be able to duplicate a -chip completely. For chip types known to include OTP memories a warning is -printed when they are detected. +bytes and can be used to give devices unique IDs etc. flashrom can read and +write these memories for some chips with \-\-otp\-* operations, but writing is +possible only if they weren't yet locked. For chip types with unsupported OTP +memories a warning is printed when they are detected. .sp Similar to OTP memories are unique, factory programmed, unforgeable IDs. They are not modifiable by the user at all. -- To view, visit https://review.coreboot.org/c/flashrom/+/59407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If77694e3b1c453b3fc0561da7a9eefdbce4fbb2b Gerrit-Change-Number: 59407 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] tests: add tests for OTP regions
by Sergii Dmytruk (Code Review) 17 Nov '21

17 Nov '21

Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/59406 ) Change subject: [RFC] tests: add tests for OTP regions ...................................................................... [RFC] tests: add tests for OTP regions Change-Id: I4ff584395367dfd52db89332d8e45d7e865276e1 Signed-off-by: Hatim Kanchwala <hatim at hatimak.me> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- A tests/chip_otp.c M tests/meson.build M tests/tests.c M tests/tests.h 4 files changed, 403 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/06/59406/1 diff --git a/tests/chip_otp.c b/tests/chip_otp.c new file mode 100644 index 0000000..f0bc591 --- /dev/null +++ b/tests/chip_otp.c @@ -0,0 +1,380 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2021 3mdeb Embedded Systems Consulting + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <include/test.h> +#include <string.h> + +#include "chipdrivers.h" +#include "flash.h" +#include "libflashrom.h" +#include "otp.h" +#include "programmer.h" + +/* + * Tests in this file do not use any mocking, because using OTP emulation in + * dummyflasher programmer is sufficient + */ + +enum { MAX_REGION_SIZE = 512 }; + +/* This data is used in multiple tests */ +static uint8_t empty[MAX_REGION_SIZE]; +static uint8_t image[MAX_REGION_SIZE]; + +static void setup(struct flashrom_flashctx *flash, struct flashchip *chip, const char *programmer_param) +{ + flash->chip = chip; + + assert_int_equal(0, programmer_init(&programmer_dummy, programmer_param)); + /* Assignment below normally happens while probing, but this test is not probing. */ + flash->mst = &registered_masters[0]; + + for (unsigned int i = 0; i < MAX_REGION_SIZE; i++) { + empty[i] = 0xff; + image[i] = i; + } +} + +static void teardown(void) +{ + assert_int_equal(0, programmer_shutdown()); +} + +/* Setup the struct for W25Q128.V, all values come from flashchips.c */ +static const struct flashchip chip_W25Q40_V = { + .vendor = "aklm&dummyflasher", + .total_size = 512, + .tested = TEST_OK_PREW, + .read = spi_chip_read, + .write = spi_chip_write_256, + .unlock = spi_disable_blockprotect, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_RDSR2 | + FEATURE_WRSR_EXT, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .otp = &gd_w256_3_otp, +}; + +/* Setup the struct for EN25QH128, all values come from flashchips.c */ +static const struct flashchip chip_EN25QH128 = { + .vendor = "aklm&dummyflasher", + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_QPI, + .tested = TEST_OK_PREW, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .otp = &en512_16384otp, +}; + +void otp_regs_status_dummyflasher_test_success(void **state) +{ + (void) state; /* unused */ + + struct flashrom_flashctx flash = { 0 }; + struct flashchip mock_chip = chip_W25Q40_V; + + char *param_dup = strdup("bus=spi,emulate=W25Q40.V"); + + setup(&flash, &mock_chip, param_dup); + + assert_true(flashrom_otp_chip_supported(&flash)); + + size_t nregions; + struct flashrom_otp_region regions[FLASHROM_OTP_MAX_REGIONS]; + assert_int_equal(0, flashrom_otp_get_regions(&flash, regions, &nregions)); + assert_int_equal(3, nregions); + assert_int_equal(256, regions[0].size); + assert_false(regions[0].locked); + assert_int_equal(256, regions[1].size); + assert_false(regions[1].locked); + assert_int_equal(256, regions[2].size); + assert_false(regions[2].locked); + + bool locked; + assert_int_equal(0, flashrom_otp_status(&flash, 0, &locked)); + assert_false(locked); + assert_int_equal(0, flashrom_otp_status(&flash, 1, &locked)); + assert_false(locked); + assert_int_equal(0, flashrom_otp_status(&flash, 2, &locked)); + assert_false(locked); + + teardown(); + + free(param_dup); +} + +void otp_mode_status_dummyflasher_test_success(void **state) +{ + (void) state; /* unused */ + + struct flashrom_flashctx flash = { 0 }; + struct flashchip mock_chip = chip_EN25QH128; + + char *param_dup = strdup("bus=spi,emulate=EN25QH128"); + + setup(&flash, &mock_chip, param_dup); + + assert_true(flashrom_otp_chip_supported(&flash)); + + size_t nregions; + struct flashrom_otp_region regions[FLASHROM_OTP_MAX_REGIONS]; + assert_int_equal(0, flashrom_otp_get_regions(&flash, regions, &nregions)); + assert_int_equal(1, nregions); + assert_int_equal(512, regions[0].size); + assert_false(regions[0].locked); + + bool locked; + assert_int_equal(0, flashrom_otp_status(&flash, 0, &locked)); + assert_false(locked); + + teardown(); + + free(param_dup); +} + +void otp_regs_locking_dummyflasher_test_success(void **state) +{ + (void) state; /* unused */ + + struct flashrom_flashctx flash = { 0 }; + struct flashchip mock_chip = chip_W25Q40_V; + + char *param_dup = strdup("bus=spi,emulate=W25Q40.V"); + + setup(&flash, &mock_chip, param_dup); + + assert_int_equal(0, flashrom_otp_lock(&flash, 0)); + assert_int_equal(0, flashrom_otp_lock(&flash, 2)); + /* No such regions */ + assert_int_equal(1, flashrom_otp_lock(&flash, -1)); + assert_int_equal(1, flashrom_otp_lock(&flash, 3)); + + size_t nregions; + struct flashrom_otp_region regions[FLASHROM_OTP_MAX_REGIONS]; + assert_int_equal(0, flashrom_otp_get_regions(&flash, regions, &nregions)); + assert_int_equal(3, nregions); + assert_int_equal(256, regions[0].size); + assert_true(regions[0].locked); + assert_int_equal(256, regions[1].size); + assert_false(regions[1].locked); + assert_int_equal(256, regions[2].size); + assert_true(regions[2].locked); + + assert_int_equal(0, flashrom_otp_lock(&flash, 1)); + + bool locked; + assert_int_equal(0, flashrom_otp_status(&flash, 0, &locked)); + assert_true(locked); + assert_int_equal(0, flashrom_otp_status(&flash, 1, &locked)); + assert_true(locked); + assert_int_equal(0, flashrom_otp_status(&flash, 2, &locked)); + assert_true(locked); + + teardown(); + + free(param_dup); +} + +void otp_mode_locking_dummyflasher_test_success(void **state) +{ + (void) state; /* unused */ + + struct flashrom_flashctx flash = { 0 }; + struct flashchip mock_chip = chip_EN25QH128; + + char *param_dup = strdup("bus=spi,emulate=EN25QH128"); + + setup(&flash, &mock_chip, param_dup); + + assert_int_equal(0, flashrom_otp_lock(&flash, 0)); + + size_t nregions; + struct flashrom_otp_region regions[FLASHROM_OTP_MAX_REGIONS]; + assert_int_equal(0, flashrom_otp_get_regions(&flash, regions, &nregions)); + assert_int_equal(1, nregions); + assert_int_equal(512, regions[0].size); + assert_true(regions[0].locked); + + teardown(); + + free(param_dup); +} + +void otp_regs_ops_dummyflasher_test_success(void **state) +{ + (void) state; /* unused */ + + enum { REGION_SIZE = 256 }; + + struct flashrom_flashctx flash = { 0 }; + struct flashchip mock_chip = chip_W25Q40_V; + uint8_t buf[REGION_SIZE]; + + char *param_dup = strdup("bus=spi,emulate=W25Q40.V"); + + setup(&flash, &mock_chip, param_dup); + + /* Write image for the first region */ + assert_int_equal(0, flashrom_otp_write(&flash, 0, image, REGION_SIZE)); + + /* Check that we read back what we've written */ + assert_int_equal(0, flashrom_otp_read(&flash, 0, buf, REGION_SIZE)); + assert_memory_equal(buf, image, REGION_SIZE); + + /* Check that other regions are still empty */ + assert_int_equal(0, flashrom_otp_read(&flash, 1, buf, REGION_SIZE)); + assert_memory_equal(buf, empty, REGION_SIZE); + assert_int_equal(0, flashrom_otp_read(&flash, 2, buf, REGION_SIZE)); + assert_memory_equal(buf, empty, REGION_SIZE); + + /* Can erase regions */ + assert_int_equal(0, flashrom_otp_erase(&flash, 0)); + assert_int_equal(0, flashrom_otp_read(&flash, 0, buf, REGION_SIZE)); + assert_memory_equal(buf, empty, REGION_SIZE); + + teardown(); + + free(param_dup); +} + +void otp_mode_ops_dummyflasher_test_success(void **state) +{ + (void) state; /* unused */ + + enum { REGION_SIZE = 512 }; + + struct flashrom_flashctx flash = { 0 }; + struct flashchip mock_chip = chip_EN25QH128; + uint8_t buf[REGION_SIZE]; + + char *param_dup = strdup("bus=spi,emulate=EN25QH128"); + + setup(&flash, &mock_chip, param_dup); + + /* Write image */ + assert_int_equal(0, flashrom_otp_write(&flash, 0, image, REGION_SIZE)); + + /* Check that we read back what we've written */ + assert_int_equal(0, flashrom_otp_read(&flash, 0, buf, REGION_SIZE)); + assert_memory_equal(buf, image, REGION_SIZE); + + teardown(); + + free(param_dup); +} + +void otp_regs_in_locked_state_test_success(void **state) +{ + (void) state; /* unused */ + + enum { REGION_SIZE = 256 }; + + struct flashrom_flashctx flash = { 0 }; + struct flashchip mock_chip = chip_W25Q40_V; + uint8_t buf[REGION_SIZE]; + + char *param_dup = strdup("bus=spi,emulate=W25Q40.V"); + + setup(&flash, &mock_chip, param_dup); + + /* Write first region and lock it */ + assert_int_equal(0, flashrom_otp_write(&flash, 0, image, REGION_SIZE)); + assert_int_equal(0, flashrom_otp_lock(&flash, 0)); + + /* Lost ability to write or erase it */ + assert_int_equal(1, flashrom_otp_write(&flash, 0, image, REGION_SIZE)); + assert_int_equal(1, flashrom_otp_erase(&flash, 0)); + + /* Can still write or erase other regions */ + assert_int_equal(0, flashrom_otp_write(&flash, 1, image, REGION_SIZE)); + assert_int_equal(0, flashrom_otp_write(&flash, 2, image, REGION_SIZE)); + assert_int_equal(0, flashrom_otp_erase(&flash, 1)); + assert_int_equal(0, flashrom_otp_erase(&flash, 2)); + + /* Region's content is correct after all manipulations */ + assert_int_equal(0, flashrom_otp_read(&flash, 0, buf, REGION_SIZE)); + assert_memory_equal(buf, image, REGION_SIZE); + + teardown(); + + free(param_dup); +} + +void otp_mode_in_locked_state_test_success(void **state) +{ + (void) state; /* unused */ + + enum { REGION_SIZE = 512 }; + + struct flashrom_flashctx flash = { 0 }; + struct flashchip mock_chip = chip_EN25QH128; + uint8_t buf[REGION_SIZE]; + + char *param_dup = strdup("bus=spi,emulate=EN25QH128"); + + setup(&flash, &mock_chip, param_dup); + + /* Write first region and lock it */ + assert_int_equal(0, flashrom_otp_write(&flash, 0, image, REGION_SIZE)); + assert_int_equal(0, flashrom_otp_lock(&flash, 0)); + + /* Lost ability to write or erase it */ + assert_int_equal(1, flashrom_otp_write(&flash, 0, image, REGION_SIZE)); + assert_int_equal(1, flashrom_otp_erase(&flash, 0)); + + /* Region's content is correct after all manipulations */ + assert_int_equal(0, flashrom_otp_read(&flash, 0, buf, REGION_SIZE)); + assert_memory_equal(buf, image, REGION_SIZE); + + teardown(); + + free(param_dup); +} diff --git a/tests/meson.build b/tests/meson.build index 1cfef87..84fd336 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -24,6 +24,7 @@ 'layout.c', 'chip.c', 'chip_wp.c', + 'chip_otp.c', ] mocks = [ diff --git a/tests/tests.c b/tests/tests.c index 981b73f..29329c2 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -368,5 +368,17 @@ }; ret |= cmocka_run_group_tests_name("chip_wp.c tests", chip_wp_tests, NULL, NULL); + const struct CMUnitTest chip_otp_tests[] = { + cmocka_unit_test(otp_regs_status_dummyflasher_test_success), + cmocka_unit_test(otp_mode_status_dummyflasher_test_success), + cmocka_unit_test(otp_regs_locking_dummyflasher_test_success), + cmocka_unit_test(otp_mode_locking_dummyflasher_test_success), + cmocka_unit_test(otp_regs_ops_dummyflasher_test_success), + cmocka_unit_test(otp_mode_ops_dummyflasher_test_success), + cmocka_unit_test(otp_regs_in_locked_state_test_success), + cmocka_unit_test(otp_mode_in_locked_state_test_success), + }; + ret |= cmocka_run_group_tests_name("chip_otp.c tests", chip_otp_tests, NULL, NULL); + return ret; } diff --git a/tests/tests.h b/tests/tests.h index 6ba44a9..ad1091d 100644 --- a/tests/tests.h +++ b/tests/tests.h @@ -76,4 +76,14 @@ void full_chip_erase_with_wp_dummyflasher_test_success(void **state); void partial_chip_erase_with_wp_dummyflasher_test_success(void **state); +/* chip_otp.c */ +void otp_regs_status_dummyflasher_test_success(void **state); +void otp_mode_status_dummyflasher_test_success(void **state); +void otp_regs_locking_dummyflasher_test_success(void **state); +void otp_mode_locking_dummyflasher_test_success(void **state); +void otp_regs_ops_dummyflasher_test_success(void **state); +void otp_mode_ops_dummyflasher_test_success(void **state); +void otp_regs_in_locked_state_test_success(void **state); +void otp_mode_in_locked_state_test_success(void **state); + #endif /* TESTS_H */ -- To view, visit https://review.coreboot.org/c/flashrom/+/59406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4ff584395367dfd52db89332d8e45d7e865276e1 Gerrit-Change-Number: 59406 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

Change in flashrom[master]: [RFC] flashchips: add support for OTP to several chip models
by Sergii Dmytruk (Code Review) 17 Nov '21

17 Nov '21

Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/59405 ) Change subject: [RFC] flashchips: add support for OTP to several chip models ...................................................................... [RFC] flashchips: add support for OTP to several chip models Added configurations matches new chips in dummyflasher. Change-Id: I98491ed00d1e5fa6682bcdc4d5e132ec76447f21 Signed-off-by: Hatim Kanchwala <hatim at hatimak.me> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M Makefile M flashchips.c M meson.build M otp.h A otp_layouts.c 5 files changed, 227 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/05/59405/1 diff --git a/Makefile b/Makefile index 74acbfc..7e8d0b0 100644 --- a/Makefile +++ b/Makefile @@ -314,7 +314,7 @@ sst28sf040.o 82802ab.o \ sst49lfxxxc.o sst_fwhub.o edi.o flashchips.o spi.o spi25.o spi25_statusreg.o \ spi95.o opaque.o sfdp.o en29lv640b.o at45db.o s25f.o \ - otp.o writeprotect.o writeprotect_ranges.o + otp.o otp_layouts.o writeprotect.o writeprotect_ranges.o ############################################################################### # Library code. diff --git a/flashchips.c b/flashchips.c index b26681d..6bad720 100644 --- a/flashchips.c +++ b/flashchips.c @@ -21,6 +21,7 @@ #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" +#include "otp.h" /** * List of supported flash chips. @@ -4955,8 +4956,8 @@ .model_id = EON_EN25Q16, .total_size = 2048, .page_size = 256, - /* OTP: D16 512B/Q16 128B total; enter 0x3A */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + /* OTP: D16 512B/Q16 128B total */ + .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -4985,6 +4986,7 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, + .otp = &en128_2048otp, }, { @@ -4995,8 +4997,7 @@ .model_id = EON_EN25Q32, .total_size = 4096, .page_size = 256, - /* OTP: 512B total; enter 0x3A */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5021,6 +5022,7 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, + .otp = &en512_4096otp, }, { @@ -5031,8 +5033,7 @@ .model_id = EON_EN25Q40, .total_size = 512, .page_size = 256, - /* OTP: 256B total; enter 0x3A */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5057,6 +5058,7 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, + .otp = &en256_512otp, }, { @@ -5067,8 +5069,7 @@ .model_id = EON_EN25Q64, .total_size = 8192, .page_size = 256, - /* OTP: 512B total; enter 0x3A */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5093,6 +5094,7 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, + .otp = &en512_8192otp, }, { @@ -5103,8 +5105,7 @@ .model_id = EON_EN25Q80, .total_size = 1024, .page_size = 256, - /* OTP: 256B total; enter 0x3A */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5129,6 +5130,7 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, + .otp = &en256_1024otp, }, { @@ -5140,9 +5142,8 @@ .total_size = 16384, .page_size = 256, /* supports SFDP */ - /* OTP: 512B total; enter 0x3A */ /* QPI enable 0x38, disable 0xFF */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_QPI, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5167,6 +5168,7 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, + .otp = &en512_16384otp, }, { @@ -5178,9 +5180,8 @@ .total_size = 2048, .page_size = 256, /* supports SFDP */ - /* OTP: 512B total; enter 0x3A */ /* QPI enable 0x38, disable 0xFF */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_QPI, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5205,6 +5206,7 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, + .otp = &en512_2048otp, }, { @@ -5216,9 +5218,8 @@ .total_size = 4096, .page_size = 256, /* supports SFDP */ - /* OTP: 512B total; enter 0x3A */ /* QPI enable 0x38, disable 0xFF */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_QPI, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5243,6 +5244,7 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, + .otp = &en512_4096otp, }, { @@ -5254,9 +5256,8 @@ .total_size = 8192, .page_size = 256, /* supports SFDP */ - /* OTP: 512B total; enter 0x3A */ /* QPI enable 0x38, disable 0xFF */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_QPI, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5281,6 +5282,7 @@ .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, + .otp = &en512_8192otp, }, { @@ -6588,9 +6590,9 @@ .model_id = GIGADEVICE_GD25Q128, .total_size = 16384, .page_size = 256, - /* OTP: 1536B total; read 0x48; write 0x42, erase 0x44 */ /* QPI: enable 0x38, disable 0xFF */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_QPI | + FEATURE_RDSR2 | FEATURE_WRSR2, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -6619,6 +6621,7 @@ .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .otp = &gd512_3_otp, }, { @@ -7022,8 +7025,7 @@ .model_id = GIGADEVICE_GD25VQ21B, .total_size = 256, .page_size = 256, - /* OTP: 1536B total; read 0x48, write 0x42, erase 0x44 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_QPI, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -7051,6 +7053,7 @@ .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2300, 3600}, + .otp = &gd512_3_otp, }, { @@ -7101,8 +7104,8 @@ .model_id = GIGADEVICE_GD25VQ41B, .total_size = 512, .page_size = 256, - /* OTP: 1536B total; read 0x48, write 0x42, erase 0x44 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_QPI | + FEATURE_RDSR2 | FEATURE_WRSR2, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -7130,6 +7133,7 @@ .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2300, 3600}, + .otp = &gd512_3_otp, }, { @@ -17684,8 +17688,9 @@ .total_size = 512, .page_size = 256, /* supports SFDP */ - /* OTP: 756B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + /* OTP: read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_RDSR2 | + FEATURE_WRSR_EXT, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -17713,6 +17718,7 @@ .write = spi_chip_write_256, /* Multi I/O supported */ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .otp = &gd_w256_3_otp, }, { diff --git a/meson.build b/meson.build index 7520943..31c12e8 100644 --- a/meson.build +++ b/meson.build @@ -386,6 +386,7 @@ srcs += 'libflashrom.c' srcs += 'opaque.c' srcs += 'otp.c' +srcs += 'otp_layouts.c' srcs += 'print.c' srcs += 'programmer.c' srcs += 'programmer_table.c' diff --git a/otp.h b/otp.h index cd8f7bd..5782f70 100644 --- a/otp.h +++ b/otp.h @@ -60,4 +60,14 @@ } regions[FLASHROM_OTP_MAX_REGIONS + 1]; /* We need one more than maximum */ }; +extern struct otp en128_2048otp; +extern struct otp en256_512otp; +extern struct otp en512_4096otp; +extern struct otp en256_1024otp; +extern struct otp en512_2048otp; +extern struct otp en512_16384otp; +extern struct otp en512_8192otp; +extern struct otp gd_w256_3_otp; +extern struct otp gd512_3_otp; + #endif /* !__OTP_H__ */ diff --git a/otp_layouts.c b/otp_layouts.c new file mode 100644 index 0000000..114ac2d --- /dev/null +++ b/otp_layouts.c @@ -0,0 +1,183 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2016 Hatim Kanchwala <hatim(a)hatimak.me> + * Copyright (C) 2021 3mdeb Embedded Systems Consulting + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "otp.h" +#include "spi.h" + +/* + * Eon (OTP mode) + * + * Because OTP region is mapped at the end of address space, structures differ + * based on region and flash sizes. + */ + +/* EN25Q16 */ +struct otp en128_2048otp = { + .feature_bits = OTP_KIND_MODE | OTP_MODE_CLEAR_BP | OTP_MODE_LOCK_WHILE_IN, + .otp_enter_opcode = JEDEC_ENTER_OTP, + .otp_exit_opcode = JEDEC_WRDI, + .regions = + { + { + .addr = 0x1FF000, + .size = 128, + .status_bit = {STATUS1, 7, OTP}, + }, + }, +}; + +/* EN25Q40 */ +struct otp en256_512otp = { + .feature_bits = OTP_KIND_MODE | OTP_MODE_CLEAR_BP | OTP_MODE_LOCK_WHILE_IN, + .otp_enter_opcode = JEDEC_ENTER_OTP, + .otp_exit_opcode = JEDEC_WRDI, + .regions = + { + { + .addr = 0x07F000, + .size = 256, + .status_bit = {STATUS1, 7, OTP}, + }, + }, +}; + +/* EN25Q80(A) */ +struct otp en256_1024otp = { + .feature_bits = OTP_KIND_MODE | OTP_MODE_CLEAR_BP | OTP_MODE_LOCK_WHILE_IN, + .otp_enter_opcode = JEDEC_ENTER_OTP, + .otp_exit_opcode = JEDEC_WRDI, + .regions = + { + { + .addr = 0x0FF000, + .size = 256, + .status_bit = {STATUS1, 7, OTP}, + }, + }, +}; + +/* EN25QH16 */ +struct otp en512_2048otp = { + .feature_bits = OTP_KIND_MODE | OTP_MODE_CLEAR_BP | OTP_MODE_LOCK_WHILE_IN, + .otp_enter_opcode = JEDEC_ENTER_OTP, + .otp_exit_opcode = JEDEC_WRDI, + .regions = + { + { + .addr = 0x1FF000, + .size = 512, + .status_bit = {STATUS1, 7, OTP}, + }, + }, +}; + +/* EN25Q32(A/B), EN25QH32 */ +struct otp en512_4096otp = { + .feature_bits = OTP_KIND_MODE | OTP_MODE_CLEAR_BP | OTP_MODE_LOCK_WHILE_IN, + .otp_enter_opcode = JEDEC_ENTER_OTP, + .otp_exit_opcode = JEDEC_WRDI, + .regions = + { + { + .addr = 0x3FF000, + .size = 512, + .status_bit = {STATUS1, 7, OTP}, + }, + }, +}; + +/* EN25Q64, EN25QH64 */ +struct otp en512_8192otp = { + .feature_bits = OTP_KIND_MODE | OTP_MODE_CLEAR_BP | OTP_MODE_LOCK_WHILE_IN, + .otp_enter_opcode = JEDEC_ENTER_OTP, + .otp_exit_opcode = JEDEC_WRDI, + .regions = + { + { + .addr = 0x7FF000, + .size = 512, + .status_bit = {STATUS1, 7, OTP}, + }, + }, +}; + +/* EN25Q128, EN25QH128 */ +struct otp en512_16384otp = { + .feature_bits = OTP_KIND_MODE | OTP_MODE_CLEAR_BP | OTP_MODE_LOCK_WHILE_IN, + .otp_enter_opcode = JEDEC_ENTER_OTP, + .otp_exit_opcode = JEDEC_WRDI, + .regions = + { + { + .addr = 0xFFF000, + .size = 512, + .status_bit = {STATUS1, 7, OTP}, + }, + }, +}; + +/* + * GigaDevice and Winbond (secure registers) + * + * Sizes and addresses differ, although all regions tend to be of the same size. + */ + +/* W25Q40.V */ +struct otp gd_w256_3_otp = { + .feature_bits = OTP_KIND_REGS, + .regions = + { + { + .addr = 0x001000, + .size = 256, + .status_bit = {STATUS2, 3, OTP}, + }, { + .addr = 0x002000, + .size = 256, + .status_bit = {STATUS2, 4, OTP}, + }, { + .addr = 0x003000, + .size = 256, + .status_bit = {STATUS2, 5, OTP}, + }, + }, +}; + +/* GD25VQ21B, GD25VQ41B, GD25Q128C */ +struct otp gd512_3_otp = { + .feature_bits = OTP_KIND_REGS, + .regions = + { + { + .addr = 0x001000, + .size = 512, + .status_bit = {STATUS2, 3, OTP}, + }, { + .addr = 0x002000, + .size = 512, + .status_bit = {STATUS2, 4, OTP}, + }, { + .addr = 0x003000, + .size = 512, + .status_bit = {STATUS2, 5, OTP}, + }, + }, +}; -- To view, visit https://review.coreboot.org/c/flashrom/+/59405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I98491ed00d1e5fa6682bcdc4d5e132ec76447f21 Gerrit-Change-Number: 59405 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] dummyflasher: add EN25QH128 and W25Q40.V with OTP
by Sergii Dmytruk (Code Review) 17 Nov '21

17 Nov '21

Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/59404 ) Change subject: [RFC] dummyflasher: add EN25QH128 and W25Q40.V with OTP ...................................................................... [RFC] dummyflasher: add EN25QH128 and W25Q40.V with OTP These chips demonstrate two kinds of OTP: mode (Eon) and security registers (Winbond) and will be used in tests. Change-Id: I1af3ac22a66104517f1fe035e034404c6b249257 Signed-off-by: Hatim Kanchwala <hatim at hatimak.me> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M dummyflasher.c M flashrom.8.tmpl 2 files changed, 308 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/04/59404/1 diff --git a/dummyflasher.c b/dummyflasher.c index 7bdcba4..82db268 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -2,6 +2,7 @@ * This file is part of the flashrom project. * * Copyright (C) 2009,2010 Carl-Daniel Hailfinger + * Copyright (C) 2016 Hatim Kanchwala <hatim at hatimak.me> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -26,14 +27,17 @@ #include "flashchips.h" #include "spi.h" +/* Comments reflect what's implemented for a specific chip (might be incomplete) */ enum emu_chip { - EMULATE_NONE, - EMULATE_ST_M25P10_RES, - EMULATE_SST_SST25VF040_REMS, - EMULATE_SST_SST25VF032B, - EMULATE_MACRONIX_MX25L6436, - EMULATE_WINBOND_W25Q128FV, - EMULATE_VARIABLE_SIZE, + EMULATE_NONE, /* SR1 */ + EMULATE_ST_M25P10_RES, /* SR1 */ + EMULATE_SST_SST25VF040_REMS, /* SR1 */ + EMULATE_SST_SST25VF032B, /* SR1, SFDP */ + EMULATE_MACRONIX_MX25L6436, /* SR1 */ + EMULATE_WINBOND_W25Q128FV, /* SR1-2 */ + EMULATE_VARIABLE_SIZE, /* SR1 */ + EMULATE_EON_EN25QH128, /* SR1, OTP (mode) */ + EMULATE_WINBOND_W25Q40_V, /* SR1-2, OTP (sec. regs) */ }; struct emu_data { @@ -67,6 +71,15 @@ unsigned int spi_write_256_chunksize; uint8_t *flashchip_contents; + + /* Specific to EN25QH128 */ + uint8_t otp_mode; + uint8_t otp_bit; + + uint8_t otp_region_count; + uint16_t otp_region_size; /* this assumes regions of equal size */ + char *otp_image_path[FLASHROM_OTP_MAX_REGIONS]; /* path to a persistent image on disk */ + uint8_t *otp_region[FLASHROM_OTP_MAX_REGIONS]; /* data of the region */ }; /* A legit complete SFDP table based on the MX25L6436E (rev. 1.8) datasheet. */ @@ -170,7 +183,8 @@ { uint8_t ro_bits = (status_reg == 1 ? SPI_SR_WEL | SPI_SR_WIP : 0); - if (data->emu_chip == EMULATE_WINBOND_W25Q128FV) { + if (data->emu_chip == EMULATE_WINBOND_W25Q128FV || + data->emu_chip == EMULATE_WINBOND_W25Q40_V) { const bool srp0 = (data->emu_status >> 7); const bool srp1 = (data->emu_status2 & 1); @@ -179,7 +193,7 @@ if (wp_active) { ro_bits = 0xff; } else if (status_reg == 2) { - /* SUS1 (bit_7) and (R) (bit_2). */ + /* SUS (bit_7) and (R) (bit_2). */ ro_bits = 0x84; /* Once any of the lock bits (LB[1..3]) are set, they * can't be unset. */ @@ -275,11 +289,14 @@ { unsigned int offs, i, toread; uint8_t ro_bits; + uint8_t region; static int unsigned aai_offs; const unsigned char sst25vf040_rems_response[2] = {0xbf, 0x44}; const unsigned char sst25vf032b_rems_response[2] = {0xbf, 0x4a}; const unsigned char mx25l6436_rems_response[2] = {0xc2, 0x16}; const unsigned char w25q128fv_rems_response[2] = {0xef, 0x17}; + const unsigned char en25qh128_rems_response[2] = {0x1c, 0x17}; + const unsigned char w25q40v_rems_response[2] = {0xef, 0x12}; if (writecnt == 0) { msg_perr("No command sent to the chip!\n"); @@ -342,6 +359,14 @@ if (readcnt > 0) memset(readarr, 0x17, readcnt); break; + case EMULATE_EON_EN25QH128: + if (readcnt > 0) + memset(readarr, 0x17, readcnt); + break; + case EMULATE_WINBOND_W25Q40_V: + if (readcnt > 0) + memset(readarr, 0x12, readcnt); + break; default: /* ignore */ break; } @@ -369,6 +394,14 @@ for (i = 0; i < readcnt; i++) readarr[i] = w25q128fv_rems_response[(offs + i) % 2]; break; + case EMULATE_EON_EN25QH128: + for (i = 0; i < readcnt; i++) + readarr[i] = en25qh128_rems_response[(offs + i) % 2]; + break; + case EMULATE_WINBOND_W25Q40_V: + for (i = 0; i < readcnt; i++) + readarr[i] = w25q40v_rems_response[(offs + i) % 2]; + break; default: /* ignore */ break; } @@ -409,11 +442,31 @@ if (readcnt > 3) readarr[3] = PROGDEV_ID & 0xff; break; + case EMULATE_EON_EN25QH128: + if (readcnt > 0) + readarr[0] = 0x1c; + if (readcnt > 1) + readarr[1] = 0x70; + if (readcnt > 2) + readarr[2] = 0x18; + break; + case EMULATE_WINBOND_W25Q40_V: + if (readcnt > 0) + readarr[0] = 0xef; + if (readcnt > 1) + readarr[1] = 0x40; + if (readcnt > 2) + readarr[2] = 0x13; + break; default: /* ignore */ break; } break; case JEDEC_RDSR: + if (data->emu_chip == EMULATE_EON_EN25QH128 && data->otp_mode) { + memset(readarr, (data->emu_status & 0x7F) | (data->otp_bit << 7), readcnt); + break; + } memset(readarr, data->emu_status, readcnt); break; case JEDEC_RDSR2: @@ -431,6 +484,12 @@ break; } + if (data->emu_chip == EMULATE_EON_EN25QH128 && data->otp_mode) { + data->otp_bit = 1; + msg_pdbg("OTP bit set...\n"); + break; + } + /* FIXME: add some reasonable simulation of the busy flag */ ro_bits = get_status_ro_bits(data, 1); data->emu_status &= ro_bits; @@ -465,6 +524,14 @@ break; case JEDEC_READ: offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; + if (data->emu_chip == EMULATE_EON_EN25QH128 && data->otp_mode) { + if ((offs >> 12) != 0xfff || (offs & 0xfff) >= 0x200) { + msg_perr("Address out of range\n"); + break; + } + memcpy(readarr, data->otp_region[0] + (offs & 0xfff), readcnt); + break; + } /* Truncate to emu_chip_size. */ offs %= data->emu_chip_size; if (readcnt > 0) @@ -479,6 +546,18 @@ break; case JEDEC_BYTE_PROGRAM: offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; + if (data->emu_chip == EMULATE_EON_EN25QH128 && data->otp_mode) { + if (data->otp_bit) { + msg_perr("OTP bit is set, cannot program OTP sector anymore\n"); + break; + } + if ((offs >> 12) != 0xfff || (offs & 0xfff) >= 0x200) { + msg_perr("Address out of range\n"); + break; + } + memcpy(data->otp_region[0] + (offs & 0xfff), writearr + 4, writecnt - 4); + break; + } /* Truncate to emu_chip_size. */ offs %= data->emu_chip_size; if (writecnt < 5) { @@ -556,6 +635,10 @@ case JEDEC_WRDI: if (data->emu_max_aai_size) data->emu_status &= ~SPI_SR_AAI; + if (data->emu_chip == EMULATE_EON_EN25QH128) { + data->otp_mode = 0; + msg_pdbg("Left OTP mode...\n"); + } break; case JEDEC_SE: if (!data->emu_jedec_se_size) @@ -569,6 +652,18 @@ return 1; } offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; + if (data->emu_chip == EMULATE_EON_EN25QH128 && data->otp_mode) { + if (data->otp_bit) { + msg_perr("OTP bit is set, cannot erase OTP sector anymore\n"); + break; + } + if ((offs >> 12) != 0xfff || (offs & 0xfff) >= 0x200) { + msg_perr("Address out of range\n"); + break; + } + memset(data->otp_region[0], 0xff, data->otp_region_size); + break; + } if (offs & (data->emu_jedec_se_size - 1)) msg_pdbg("Unaligned SECTOR ERASE 0x20: 0x%x\n", offs); offs &= ~(data->emu_jedec_se_size - 1); @@ -688,6 +783,88 @@ "continuous chunk produces undefined results " "after that point.\n"); break; + case JEDEC_READ_SEC_REG: + if (data->emu_chip != EMULATE_WINBOND_W25Q40_V) + break; + + if (writecnt != JEDEC_READ_SEC_REG_OUTSIZE) { + msg_perr("READ SECURITY REGISTER size not proper!\n"); + break; + } + /* writearr[1..3] holds the address, writearr[1] must be 0x00, + * (writearr[2..3] & 01ff) holds the byte address pointing to within + * the security register range, and (writearr[2] & 0xf0) must be either + * of 0x01, 0x02 or 0x03 corresponding to security register 1, 2 or 3 resp. */ + if (writearr[1] || (writearr[2] & 0x0e)) + break; + offs = (writearr[2] & 0x01) << 8 | writearr[3]; + /* Truncate to security register size. */ + offs %= data->otp_region_size; + if (readcnt > 0) { + region = (writearr[2] & 0xf0) >> 4; + if (region > 0 && region < FLASHROM_OTP_MAX_REGIONS) + memcpy(readarr, data->otp_region[region - 1] + offs, readcnt); + } + break; + case JEDEC_PROG_BYTE_SEC_REG: + if (data->emu_chip != EMULATE_WINBOND_W25Q40_V) + break; + + if (writecnt < JEDEC_PROG_BYTE_SEC_REG_OUTSIZE) { + msg_perr("PROGRAM SECURITY REGISTER size too short!\n"); + break; + } + /* writearr[1..3] holds the address, writearr[1] must be 0x00, + * (writearr[2..3] & 01ff) holds the byte address pointing to within + * the security register range, and (writearr[2] & 0xf0) must be either + * of 0x01, 0x02 or 0x03 corresponding to security register 1, 2 or 3 resp. */ + if (writearr[1] || (writearr[2] & 0x0e)) + break; + offs = (writearr[2] & 0x01) << 8 | writearr[3]; + /* Truncate to security register size. */ + offs %= data->otp_region_size; + + region = (writearr[2] >> 4); + if (region > 0 && region < FLASHROM_OTP_MAX_REGIONS) { + --region; + uint8_t ls_bit_pos = 3 + region; + /* If corresponding Lock Bits are set then the register is locked against + * any further write attempts. */ + if (!(data->emu_status2 & (1 << ls_bit_pos))) + memcpy(data->otp_region[region] + offs, writearr + 4, writecnt - 4); + } + break; + case JEDEC_ERASE_SEC_REG: + if (data->emu_chip != EMULATE_WINBOND_W25Q40_V) + break; + + if (writecnt != JEDEC_ERASE_SEC_REG_OUTSIZE) { + msg_perr("ERASE SECURITY REGISTER size not proper!\n"); + break; + } + /* writearr[1..3] holds the address, writearr[1] must be 0x00, + * (writearr[2..3] & 01ff) holds the byte address pointing to within + * the security register range, and (writearr[2] & 0xf0) must be either + * of 0x01, 0x02 or 0x03 corresponding to security register 1, 2 or 3 resp. */ + if (writearr[1] || (writearr[2] & 0x0e)) + break; + + region = (writearr[2] >> 4); + if (region > 0 && region < FLASHROM_OTP_MAX_REGIONS) { + --region; + uint8_t ls_bit_pos = 3 + region; + /* If corresponding Lock Bits are set then the register + * is locked against any further erase attempts. */ + if (!(data->emu_status2 & (1 << ls_bit_pos))) + memset(data->otp_region[region], 0xff, data->otp_region_size); + } + break; + case JEDEC_ENTER_OTP: /* enter OTP for Eon chips */ + if (data->emu_chip != EMULATE_EON_EN25QH128) + break; + data->otp_mode = 1; + msg_pdbg("Entered OTP mode...\n"); + break; default: /* No special response. */ break; @@ -724,6 +901,8 @@ case EMULATE_MACRONIX_MX25L6436: case EMULATE_WINBOND_W25Q128FV: case EMULATE_VARIABLE_SIZE: + case EMULATE_EON_EN25QH128: + case EMULATE_WINBOND_W25Q40_V: if (emulate_spi_chip_response(writecnt, readcnt, writearr, readarr, emu_data)) { msg_pdbg("Invalid command sent to flash chip!\n"); @@ -746,16 +925,32 @@ { msg_pspew("%s\n", __func__); struct emu_data *emu_data = (struct emu_data *)data; - if (emu_data->emu_chip != EMULATE_NONE) { - if (emu_data->emu_persistent_image && emu_data->emu_modified) { - msg_pdbg("Writing %s\n", emu_data->emu_persistent_image); - write_buf_to_file(emu_data->flashchip_contents, - emu_data->emu_chip_size, - emu_data->emu_persistent_image); - } - free(emu_data->emu_persistent_image); - free(emu_data->flashchip_contents); + if (emu_data->emu_chip == EMULATE_NONE) { + free(data); + return 0; } + + if (emu_data->emu_persistent_image && emu_data->emu_modified) { + msg_pdbg("Writing %s\n", emu_data->emu_persistent_image); + write_buf_to_file(emu_data->flashchip_contents, + emu_data->emu_chip_size, + emu_data->emu_persistent_image); + } + free(emu_data->emu_persistent_image); + free(emu_data->flashchip_contents); + + for (uint8_t region = 0; region < emu_data->otp_region_count; ++region) { + if (emu_data->otp_image_path[region]) { + msg_pdbg("Writing %s\n", emu_data->otp_image_path[region]); + write_buf_to_file(emu_data->otp_region[region], + emu_data->otp_region_size, + emu_data->otp_image_path[region]); + } + + free(emu_data->otp_region[region]); + free(emu_data->otp_image_path[region]); + } + free(data); return 0; } @@ -1052,6 +1247,36 @@ data->emu_jedec_ce_c7_size = data->emu_chip_size; msg_pdbg("Emulating Winbond W25Q128FV SPI flash chip (RDID)\n"); } + if (!strcmp(tmp, "EN25QH128")) { + data->emu_chip = EMULATE_EON_EN25QH128; + data->emu_chip_size = 16 * 1024 * 1024; + data->emu_max_byteprogram_size = 256; + data->emu_max_aai_size = 0; + data->emu_status_len = 1; + data->emu_jedec_se_size = 4 * 1024; + data->emu_jedec_be_52_size = 32 * 1024; + data->emu_jedec_be_d8_size = 64 * 1024; + data->emu_jedec_ce_60_size = data->emu_chip_size; + data->emu_jedec_ce_c7_size = data->emu_chip_size; + data->otp_region_count = 1; + data->otp_region_size = 512; + msg_pdbg("Emulating Eon EN25QH128 SPI flash chip (RDID)\n"); + } + if (!strcmp(tmp, "W25Q40.V")) { + data->emu_chip = EMULATE_WINBOND_W25Q40_V; + data->emu_chip_size = 512 * 1024; + data->emu_max_byteprogram_size = 256; + data->emu_max_aai_size = 0; + data->emu_status_len = 2; + data->emu_jedec_se_size = 4 * 1024; + data->emu_jedec_be_52_size = 32 * 1024; + data->emu_jedec_be_d8_size = 64 * 1024; + data->emu_jedec_ce_60_size = data->emu_chip_size; + data->emu_jedec_ce_c7_size = data->emu_chip_size; + data->otp_region_count = 3; + data->otp_region_size = 256; + msg_pdbg("Emulating Winbond W25Q40.V SPI flash chip (RDID)\n"); + } /* The name of variable-size virtual chip. A 4 MiB flash example: * flashrom -p dummy:emulate=VARIABLE_SIZE,size=4194304 @@ -1133,6 +1358,14 @@ return 1; } + for (uint8_t region = 0; region < data->otp_region_count; ++region) { + data->otp_region[region] = malloc(data->otp_region_size); + if (!data->otp_region[region]) { + msg_perr("Out of memory!\n"); + return 1; + } + } + return 0; } @@ -1169,13 +1402,9 @@ /* Will be freed by shutdown function if necessary. */ data->emu_persistent_image = extract_programmer_param("image"); - if (!data->emu_persistent_image) { - /* Nothing else to do. */ - goto dummy_init_out; - } /* We will silently (in default verbosity) ignore the file if it does not exist (yet) or the size does * not match the emulated chip. */ - if (!stat(data->emu_persistent_image, &image_stat)) { + if (data->emu_persistent_image && !stat(data->emu_persistent_image, &image_stat)) { msg_pdbg("Found persistent image %s, %jd B ", data->emu_persistent_image, (intmax_t)image_stat.st_size); if ((uintmax_t)image_stat.st_size == data->emu_chip_size) { @@ -1194,10 +1423,51 @@ } } + /* Silently (in default verbosity) ignore files that don't exist (yet) + * or whose size does not match the security register size on chip. */ + for (uint8_t region = 0; region < data->otp_region_count; ++region) { + const uint16_t region_size = data->otp_region_size; + + char param_name[8]; + char *image_path; + + msg_pdbg("Filling fake security sector with 0xff, size %d bytes\n", region_size); + memset(data->otp_region[region], 0xff, region_size); + + snprintf(param_name, sizeof(param_name), "otp%d", region + 1); + + image_path = extract_programmer_param(param_name); + if (!image_path) + continue; + + data->otp_image_path[region] = image_path; + + if (stat(image_path, &image_stat)) { + msg_pdbg("OTP region image doesn't exist: %s\n", image_path); + continue; + } + + msg_pdbg("Found persistent image %s, %jd B for security sector, ", image_path, + (intmax_t)image_stat.st_size); + if (image_stat.st_size == region_size) { + msg_pdbg("matches.\n"); + msg_pdbg("Reading %s\n", image_path); + read_buf_from_file(data->otp_region[region], region_size, image_path); + } else { + msg_pdbg("doesn't match.\n"); + } + } + dummy_init_out: if (register_shutdown(dummy_shutdown, data)) { free(data->emu_persistent_image); free(data->flashchip_contents); + + for (uint8_t region = 0; region < data->otp_region_count; ++region) { + free(data->otp_region[region]); + free(data->otp_image_path[region]); + } + free(data); return 1; } diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 000a67a..126e50c 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -695,6 +695,10 @@ .sp .RB "* Winbond " W25Q128FV " SPI flash chip (16384 kB, RDID)" .sp +.RB "* Eon " EN25QH128 " SPI flash chip (16384 kB, RDID, OTP)" +.sp +.RB "* Winbond " W25Q40.V " SPI flash chip (512 kB, RDID, OTP)" +.sp .RB "* Dummy vendor " VARIABLE_SIZE " SPI flash chip (configurable size, page write)" .sp Example: @@ -722,7 +726,17 @@ where the chip contents on flashrom shutdown are written to. .sp Example: -.B "flashrom -p dummy:emulate=M25P10.RES,image=dummy.bin" +.sp +.B " flashrom -p dummy:emulate=M25P10.RES,image=dummy.bin" +.sp +Chips that support OTP allow specifying images of OTP regions via parameters of +the form +.B otpN +where +.B N +stands for region number (base 1): +.sp +.B " flashrom \-p dummy:emulate=W25Q40.V,otp1=otp1.bin,otp3=otp3.bin" .TP .B SPI write chunk size .sp -- To view, visit https://review.coreboot.org/c/flashrom/+/59404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1af3ac22a66104517f1fe035e034404c6b249257 Gerrit-Change-Number: 59404 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

Change in flashrom[master]: [RFC] libflashrom,otp: add OTP regions management API
by Sergii Dmytruk (Code Review) 17 Nov '21

17 Nov '21

Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/59403 ) Change subject: [RFC] libflashrom,otp: add OTP regions management API ...................................................................... [RFC] libflashrom,otp: add OTP regions management API This implements both OTP mode and secure registers variants. Some "unusual" configurations (chips that have no lock bits) aren't implemented here, but can be added later when this core functionality is in place. Change-Id: Idf222b20973bf99a4e65e0fa8e464232969fd7e1 Signed-off-by: Hatim Kanchwala <hatim at hatimak.me> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M Makefile M libflashrom.h M meson.build A otp.c M otp.h 5 files changed, 488 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/03/59403/1 diff --git a/Makefile b/Makefile index b196d98..74acbfc 100644 --- a/Makefile +++ b/Makefile @@ -313,7 +313,8 @@ CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \ sst28sf040.o 82802ab.o \ sst49lfxxxc.o sst_fwhub.o edi.o flashchips.o spi.o spi25.o spi25_statusreg.o \ - spi95.o opaque.o sfdp.o en29lv640b.o at45db.o writeprotect.o s25f.o + spi95.o opaque.o sfdp.o en29lv640b.o at45db.o s25f.o \ + otp.o writeprotect.o writeprotect_ranges.o ############################################################################### # Library code. diff --git a/libflashrom.h b/libflashrom.h index 3bd6855..dfc3448 100644 --- a/libflashrom.h +++ b/libflashrom.h @@ -117,4 +117,22 @@ void flashrom_layout_release(struct flashrom_layout *); void flashrom_layout_set(struct flashrom_flashctx *, const struct flashrom_layout *); +/** @ingroup flashrom-otp */ +struct flashrom_otp_region { + uint32_t size; + bool locked; +}; + +#define FLASHROM_OTP_MAX_REGIONS 4 + +bool flashrom_otp_chip_supported(const struct flashrom_flashctx *); + +int flashrom_otp_get_regions(struct flashrom_flashctx *, struct flashrom_otp_region *regions, size_t *count); +int flashrom_otp_status(struct flashrom_flashctx *, int region, bool *locked); +int flashrom_otp_lock(struct flashrom_flashctx *, int region); + +int flashrom_otp_read(struct flashrom_flashctx *, int region, void *buffer, size_t buffer_len); +int flashrom_otp_write(struct flashrom_flashctx *, int region, const void *buffer, size_t buffer_len); +int flashrom_otp_erase(struct flashrom_flashctx *, int region); + #endif /* !__LIBFLASHROM_H__ */ diff --git a/meson.build b/meson.build index 85f40ba..7520943 100644 --- a/meson.build +++ b/meson.build @@ -385,6 +385,7 @@ srcs += 'layout.c' srcs += 'libflashrom.c' srcs += 'opaque.c' +srcs += 'otp.c' srcs += 'print.c' srcs += 'programmer.c' srcs += 'programmer_table.c' diff --git a/otp.c b/otp.c new file mode 100644 index 0000000..431b2ad --- /dev/null +++ b/otp.c @@ -0,0 +1,456 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2016 Hatim Kanchwala <hatim at hatimak.me> + * Copyright (C) 2021 3mdeb Embedded Systems Consulting + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "otp.h" + +#include "chipdrivers.h" +#include "flash.h" + +/* + * TODO: Datasheets show 4 registers for program, but single 1024 B register + * for read and/or erase. + * TODO: These chips have one control bit for all OTP regions. + * + * GD25VQ16C, GD25VQ40C, GD25VQ80C, GD25Q16B, GD25Q32B, GD25Q64B, + * GD25Q80(B), GD25Q128B + */ + +/* + * TODO: some chips have a separate Security Register which must be modified + * with special opcodes (see Adesto AT25SF641 chip for example). + */ + +static bool bp_is_stashed; +static uint8_t stashed_bp_value; + +/* Determines number of OTP regions of a flash. */ +static int count_otp_regions(const struct flashctx *flash) +{ + int count = 0; + struct otp_region *regions = flash->chip->otp->regions; + + while (regions[count].size != 0) + count++; + return count; +} + +/** + * @brief Determine if OTP operations are supported for the chip. + * + * @param[in] flash Initialized flash context. + * + * @return @c true if WP operations are supported, + * @c false if WP operations are not suported. + */ +bool flashrom_otp_chip_supported(const struct flashrom_flashctx *flash) +{ + if (flash->chip->otp == NULL) + return false; + + const int kind = (flash->chip->otp->feature_bits & (OTP_KIND_MODE | OTP_KIND_REGS)); + if (kind != OTP_KIND_MODE && kind != OTP_KIND_REGS) + return false; + + const int nregions = count_otp_regions(flash); + if (nregions == 0) + return false; + + for (int i = 0; i < nregions; i++) + if (flash->chip->otp->regions[i].status_bit.reg == INVALID_REG) + return false; + + return true; +} + +/** + * @brief Retrieve list of OTP regions for a flash chip. + * + * @param[in] flash An initialized flash context with a supported chip. + * @param[out] regions Array of at least @c FLASHROM_OTP_MAX_REGIONS elements. + * @param[out] count Number of filled in regions. + * + * @return 0 on success + */ +int flashrom_otp_get_regions(struct flashrom_flashctx *flash, + struct flashrom_otp_region *regions, + size_t *count) +{ + *count = count_otp_regions(flash); + + for (size_t i = 0; i < *count; i++) { + regions[i].size = flash->chip->otp->regions[i].size; + if (flashrom_otp_status(flash, i, &regions[i].locked)) + return 1; + } + + return 0; +} + +static int read_reg_bit(struct flashctx *flash, struct reg_bit_info bit, uint8_t *value) +{ + *value = 0; + + if (bit.reg == INVALID_REG) + return 1; + + if (spi_read_register(flash, bit.reg, value)) + return 1; + + *value = (*value >> bit.bit_index) & 1; + + return 0; +} + +static int write_reg_bit(struct flashctx *flash, struct reg_bit_info bit, uint8_t value) +{ + uint8_t reg_value; + if (read_reg_bit(flash, bit, &reg_value)) + return 1; + + reg_value &= ~(1 << bit.bit_index); + reg_value |= ((value & 1) << bit.bit_index); + + return spi_write_register(flash, bit.reg, reg_value); +} + +/* Some standard error checking used by program and erase functions. */ +static int otp_error_check(struct flashctx *flash, int region, size_t len) +{ + const int nregions = count_otp_regions(flash); + if (region < 0 || region >= nregions) { + msg_cdbg("Trying to access non-existent OTP region %d\n%s has only %d OTP regions\n", + region + 1, flash->chip->name, nregions); + return 1; + } + if (len > flash->chip->otp->regions[region].size) { + msg_cdbg("OTP region for %s is %d bytes\n", flash->chip->name, + flash->chip->otp->regions[region].size); + return 1; + } + return 0; +} + +static int get_bp_bits(struct flashctx *flash, uint8_t *bp) +{ + struct flashrom_wp_chip_config cfg; + if (flashrom_wp_read_chip_config(flash, &cfg)) + return 1; + + *bp = 0; + for (size_t i = 0; i < cfg.bp_bit_count; i++) + *bp = (*bp << 1) | cfg.bp[i]; + + return 0; +} + +static int set_bp_bits(struct flashctx *flash, uint8_t bp) +{ + struct flashrom_wp_chip_config cfg; + if (flashrom_wp_read_chip_config(flash, &cfg)) + return 1; + + for (size_t i = 0; i < cfg.bp_bit_count; i++) + cfg.bp[i] = (bp >> (cfg.bp_bit_count - i + 1)) & 1; + + return flashrom_wp_write_chip_config(flash, &cfg); +} + +static int enter_otp_mode(struct flashctx *flash) +{ + if (!(flash->chip->otp->feature_bits & OTP_KIND_MODE)) + return 0; + + uint8_t bp; + if (get_bp_bits(flash, &bp)) { + msg_cerr("Failed to read BP bits before entering OTP mode...\n"); + return 1; + } + + if ((flash->chip->otp->feature_bits & OTP_MODE_CLEAR_BP) && bp != 0) { + msg_cdbg("Need to unset all BP bits before entering OTP mode...\n"); + msg_cdbg("BP bits will be restored to 0x%02x\n", bp); + stashed_bp_value = bp; + bp_is_stashed = true; + + if (set_bp_bits(flash, 0)) { + msg_cdbg("Couldn't unset BP bits\n"); + return 1; + } + } + + return spi_otp_mode_enter(flash); +} + +static int exit_otp_mode(struct flashctx *flash) +{ + if (!(flash->chip->otp->feature_bits & OTP_KIND_MODE)) + return 0; + + int result = spi_otp_mode_exit(flash); + if (result) { + msg_cdbg("Couldn't exit OTP mode\n"); + return result; + } + + /* Should only be set if OTP_MODE_CLEAR_BP is present. */ + if (bp_is_stashed) { + bp_is_stashed = false; + msg_cdbg("Restoring BP bits to their state prior to entering OTP mode ...\n"); + if (set_bp_bits(flash, stashed_bp_value)) + msg_cdbg("Couldn't restore BP bits\n"); + } + + return result; +} + +/** + * @brief Query status of an OTP region for a flash chip. + * + * @param[in] flash An initialized flash context with a supported chip. + * @param[in] region Base zero index of the OTP region. + * @param[out] locked Whether the region is already locked. + * + * @return 0 on success + */ +int flashrom_otp_status(struct flashrom_flashctx *flash, int region, bool *locked) +{ + struct otp *otp = flash->chip->otp; + + if (otp_error_check(flash, region, 0)) { + msg_cerr("%s failed\n", __func__); + return 1; + } + + if (enter_otp_mode(flash)) { + msg_cerr("Error: Failed to enter OTP mode.\n"); + return 1; + } + + uint8_t status; + int result = 0; + if (read_reg_bit(flash, otp->regions[region].status_bit, &status)) { + msg_cerr("Error: Failed to query status of OTP region %d.\n", + region + 1); + result = 1; + } + + if (exit_otp_mode(flash)) { + msg_cerr("Error: Failed to leave OTP mode.\n"); + return 1; + } + + *locked = status; + return result; +} + +/** + * @brief Read @p len bytes from OTP region. + * + * @param[in] flash An initialized flash context with a supported chip. + * @param[in] region Base zero index of the OTP region. + * @param[out] buf Buffer for the data. + * @param[in] len Buffer size. + * + * @return 0 on success + */ +int flashrom_otp_read(struct flashctx *flash, int region, void *buf, size_t len) +{ + struct otp *otp = flash->chip->otp; + + int result = otp_error_check(flash, region, len); + if (result) { + msg_cerr("%s failed\n", __func__); + return result; + } + + if (enter_otp_mode(flash)) { + msg_cerr("Error: Failed to enter OTP mode.\n"); + return 1; + } + + if (flash->chip->otp->feature_bits & OTP_KIND_MODE) + result = flash->chip->read(flash, buf, otp->regions[region].addr, len); + else if (flash->chip->otp->feature_bits & OTP_KIND_REGS) + result = spi_sec_reg_read(flash, buf, otp->regions[region].addr, len); + else + result = 1; + + if (exit_otp_mode(flash)) { + msg_cerr("Error: Failed to leave OTP mode.\n"); + return 1; + } + + if (result) + msg_cerr("%s failed\n", __func__); + return result; +} + +/** + * @brief Write @p len bytes to OTP region. + * + * @param[in] flash An initialized flash context with a supported chip. + * @param[in] region Base zero index of the OTP region. + * @param[in] buf Buffer with the data. + * @param[in] len Buffer size. + * + * @return 0 on success + */ +int flashrom_otp_write(struct flashctx *flash, int region, const void *buf, size_t len) +{ + struct otp *otp = flash->chip->otp; + + int result = otp_error_check(flash, region, len); + if (result) { + msg_cerr("%s failed\n", __func__); + return result; + } + + bool locked; + if (flashrom_otp_status(flash, region, &locked)) + return 1; + + if (locked) { + msg_cdbg("OTP region %d is permanently locked and cannot be written to\n", + region + 1); + msg_cerr("%s failed\n", __func__); + return 1; + } + + if (enter_otp_mode(flash)) { + msg_cerr("Error: Failed to enter OTP mode.\n"); + return 1; + } + + if (flash->chip->otp->feature_bits & OTP_KIND_MODE) + result = flash->chip->write(flash, buf, otp->regions[region].addr, len); + else if (flash->chip->otp->feature_bits & OTP_KIND_REGS) + result = spi_sec_reg_prog(flash, buf, flash->chip->otp->regions[region].addr, len); + else + result = 1; + + if (exit_otp_mode(flash)) { + msg_cerr("Error: Failed to leave OTP mode.\n"); + return 1; + } + + if (result) + msg_cerr("%s failed\n", __func__); + return result; +} + +/** + * @brief Erase OTP region. + * + * @param[in] flash An initialized flash context with a supported chip. + * @param[in] region Base zero index of the OTP region. + * + * @return 0 on success + */ +int flashrom_otp_erase(struct flashctx *flash, int region) +{ + struct otp *otp = flash->chip->otp; + + int result = otp_error_check(flash, region, 0); + if (result) { + msg_cdbg("%s failed\n", __func__); + return result; + } + + bool locked; + if (flashrom_otp_status(flash, region, &locked)) + return 1; + + if (locked) { + msg_cdbg("OTP region %d is permanently locked and cannot be written to\n", + region + 1); + msg_cdbg("%s failed\n", __func__); + return 1; + } + + if (enter_otp_mode(flash)) { + msg_cerr("Error: Failed to enter OTP mode.\n"); + return 1; + } + + if (flash->chip->otp->feature_bits & OTP_KIND_MODE) + result = spi_block_erase_20(flash, otp->regions[region].addr, otp->regions[region].size); + else if (flash->chip->otp->feature_bits & OTP_KIND_REGS) + result = spi_sec_reg_erase(flash, flash->chip->otp->regions[region].addr); + else + result = 1; + + if (exit_otp_mode(flash)) { + msg_cerr("Error: Failed to leave OTP mode.\n"); + return 1; + } + + if (result) + msg_cdbg("%s failed\n", __func__); + return result; +} + +/** + * @brief Lock OTP region. + * + * @param[in] flash An initialized flash context with a supported chip. + * @param[in] region Base zero index of the OTP region. + * + * @return 0 on success or if the region is already locked + */ +int flashrom_otp_lock(struct flashctx *flash, int region) +{ + struct otp *otp = flash->chip->otp; + + if (otp_error_check(flash, region, 0)) { + msg_cerr("%s failed\n", __func__); + return 1; + } + + struct reg_bit_info status_bit = otp->regions[region].status_bit; + + bool locked; + if (flashrom_otp_status(flash, region, &locked)) + return 1; + + if (locked) { + msg_cdbg("OTP modifier bit is already set and it's one-time-programmable\n"); + return 1; + } + + if ((otp->feature_bits & OTP_MODE_LOCK_WHILE_IN) && enter_otp_mode(flash)) { + msg_cerr("Error: Failed to enter OTP mode.\n"); + return 1; + } + + int result = write_reg_bit(flash, status_bit, 1); + + if ((otp->feature_bits & OTP_MODE_LOCK_WHILE_IN) && exit_otp_mode(flash)) { + msg_cerr("Error: Failed to leave OTP mode.\n"); + return 1; + } + + if (result || flashrom_otp_status(flash, region, &locked) || !locked) { + msg_cerr("Unable to set OTP modifier bit\n"); + return 1; + } + + return 0; +} diff --git a/otp.h b/otp.h index 635d6cb..cd8f7bd 100644 --- a/otp.h +++ b/otp.h @@ -47,6 +47,17 @@ /* These opcodes are different for different manufacturers. */ uint8_t otp_enter_opcode; uint8_t otp_exit_opcode; + + struct otp_region { + /* This address corresponds to the first byte in the OTP memory region. */ + uint32_t addr; + uint32_t size; /* in bytes */ + + /* Usually, setting this modifier bit will permanently lock the + * corresponding OTP region against writes. + * Not all chips have a modifier bit (AMIC, Macronix). */ + struct reg_bit_info status_bit; + } regions[FLASHROM_OTP_MAX_REGIONS + 1]; /* We need one more than maximum */ }; #endif /* !__OTP_H__ */ -- To view, visit https://review.coreboot.org/c/flashrom/+/59403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idf222b20973bf99a4e65e0fa8e464232969fd7e1 Gerrit-Change-Number: 59403 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] spi: add functions for OTP regions
by Sergii Dmytruk (Code Review) 17 Nov '21

17 Nov '21

Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/59402 ) Change subject: [RFC] spi: add functions for OTP regions ...................................................................... [RFC] spi: add functions for OTP regions These are functions for entering/leaving OTP mode and reading/writing/erasing secure registers. Also introduces part of the structure that describes OTP, because new code uses it. This one and other patches resurrecting the work of Hatim Kanchwala aimed at adding OTP to flashrom. This chain of patches are based on CB:59075, which in turn depend on patches that introduce write-protect support. Change-Id: Ic33e2c1de8b0ca02df9118218a663ce63826f339 Signed-off-by: Hatim Kanchwala <hatim at hatimak.me> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M chipdrivers.h M flash.h A otp.h M spi.h M spi25.c 5 files changed, 167 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/02/59402/1 diff --git a/chipdrivers.h b/chipdrivers.h index e1d6aa9..a5fbec9 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -59,6 +59,11 @@ int spi_enter_4ba(struct flashctx *flash); int spi_exit_4ba(struct flashctx *flash); int spi_set_extended_address(struct flashctx *, uint8_t addr_high); +int spi_otp_mode_enter(struct flashctx *flash); +int spi_otp_mode_exit(struct flashctx *flash); +int spi_sec_reg_read(struct flashctx *flash, uint8_t *buf, uint32_t start_addr, uint32_t len); +int spi_sec_reg_prog(struct flashctx *flash, uint8_t const *buf, uint32_t start_addr, uint32_t len); +int spi_sec_reg_erase(struct flashctx *flash, uint32_t addr); /* spi25_statusreg.c */ diff --git a/flash.h b/flash.h index 391a2d4..d4b364e 100644 --- a/flash.h +++ b/flash.h @@ -245,7 +245,7 @@ /* SPI specific options (TODO: Make it a union in case other bustypes get specific options.) */ uint8_t wrea_override; /**< override opcode for write extended address register */ - struct wp *wp; + struct otp *otp; }; typedef int (*chip_restore_fn_cb_t)(struct flashctx *flash, uint8_t status); diff --git a/otp.h b/otp.h new file mode 100644 index 0000000..635d6cb --- /dev/null +++ b/otp.h @@ -0,0 +1,52 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2016 Hatim Kanchwala <hatim at hatimak.me> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __OTP_H__ +#define __OTP_H__ 1 + +#include <stdint.h> + +#include "flash.h" + +struct flashctx; + +/* Bits for otp.feature_bits field */ +/* Need to enter special mode to work with OTP */ +#define OTP_KIND_MODE (1 << 0) +/* Need to use special opcodes to interact with OTP */ +#define OTP_KIND_REGS (1 << 1) +/* Block protect bits must be cleared before entering OTP mode */ +#define OTP_MODE_CLEAR_BP (1 << 2) +/* OTP lock must be set while in OTP mode */ +#define OTP_MODE_LOCK_WHILE_IN (1 << 3) +/* OTP registers are read as one (FIXME: not implemented) */ +#define OTP_REGS_FUSED_READ (1 << 4) +/* OTP registers are erased as one (FIXME: not implemented) */ +#define OTP_REGS_FUSED_ERASE (1 << 5) + +struct otp { + int feature_bits; /* must contain either OTP_KIND_MODE or OTP_KIND_REGS */ + + /* These opcodes are different for different manufacturers. */ + uint8_t otp_enter_opcode; + uint8_t otp_exit_opcode; +}; + +#endif /* !__OTP_H__ */ diff --git a/spi.h b/spi.h index 09da579..203ef19 100644 --- a/spi.h +++ b/spi.h @@ -178,6 +178,26 @@ #define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x03 #define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00 +/* Enter OTP mode (supported by most Eon chips) */ +#define JEDEC_ENTER_OTP 0x3A +#define JEDEC_ENTER_OTP_OUTSIZE 0x01 +#define JEDEC_ENTER_OTP_INSIZE 0x00 + +/* Read Security Register(s) (supported by most GigaDevice chips) */ +#define JEDEC_READ_SEC_REG 0x48 +#define JEDEC_READ_SEC_REG_OUTSIZE 0x05 +/* JEDEC_READ_SEC_REG_INSIZE any length */ + +/* Program Security Register(s) (supported by most GigaDevice chips) */ +#define JEDEC_PROG_BYTE_SEC_REG 0x42 +#define JEDEC_PROG_BYTE_SEC_REG_OUTSIZE 0x05 +#define JEDEC_PROG_BYTE_SEC_REG_INSIZE 0x00 + +/* Erase Security Register(s) (supported by most GigaDevice chips) */ +#define JEDEC_ERASE_SEC_REG 0x44 +#define JEDEC_ERASE_SEC_REG_OUTSIZE 0x04 +#define JEDEC_ERASE_SEC_REG_INSIZE 0x00 + /* Read the memory with 4-byte address From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ #define JEDEC_READ_4BA 0x13 diff --git a/spi25.c b/spi25.c index 213273f..629e239 100644 --- a/spi25.c +++ b/spi25.c @@ -26,6 +26,7 @@ #include "chipdrivers.h" #include "programmer.h" #include "spi.h" +#include "otp.h" enum id_type { RDID, @@ -839,3 +840,91 @@ { return spi_enter_exit_4ba(flash, false); } + +/* This function maps the additional OTP sector to the top or bottom sector + * (depending on the chip). The mapped sector behaves like just another normal + * sector. */ +int spi_otp_mode_enter(struct flashctx *flash) +{ + if (!flash->chip->otp || !flash->chip->otp->otp_enter_opcode) + return 1; + + const unsigned char cmd[1] = { + flash->chip->otp->otp_enter_opcode + }; + return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); +} + +int spi_otp_mode_exit(struct flashctx *flash) +{ + if (!flash->chip->otp || !flash->chip->otp->otp_exit_opcode) + return 1; + + const unsigned char cmd[1] = { + flash->chip->otp->otp_exit_opcode + }; + return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); +} + +int spi_sec_reg_read(struct flashctx *flash, uint8_t *buf, uint32_t start_addr, uint32_t len) +{ + /* We assume that start_addr and len are correct and proceed without any error checking. */ + uint8_t cmd[JEDEC_READ_SEC_REG_OUTSIZE] = { + JEDEC_READ_SEC_REG, + (start_addr >> 16), + (start_addr >> 8), + start_addr, + 0x00, /* dummy data */ + }; + + int result = spi_send_command(flash, sizeof(cmd), len, cmd, buf); + if (result) + msg_cerr("%s failed.\n", __func__); + return result; +} + +int spi_sec_reg_prog(struct flashctx *flash, uint8_t const *buf, uint32_t start_addr, uint32_t len) +{ + /* We assume that start_addr and len are correct, the security register is unlocked + * and proceed without any error checking. */ + int ret = spi_write_enable(flash); + if (ret) { + msg_cerr("%s failed\n", __func__); + return ret; + } + + uint8_t cmd[JEDEC_PROG_BYTE_SEC_REG_OUTSIZE - 1 + len]; + cmd[0] = JEDEC_PROG_BYTE_SEC_REG; + cmd[1] = (start_addr >> 16); + cmd[2] = (start_addr >> 8); + cmd[3] = start_addr; + memcpy(&cmd[4], buf, len); + + ret = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); + if (ret || spi_poll_wip(flash, 10)) + msg_cerr("%s\n", __func__); + + return ret; +} + +int spi_sec_reg_erase(struct flashctx *flash, uint32_t addr) +{ + /* We assume that addr is correct and proceed without any error checking. */ + int ret = spi_write_enable(flash); + if (ret) { + msg_cerr("%s failed\n", __func__); + return ret; + } + + uint8_t cmd[JEDEC_ERASE_SEC_REG_OUTSIZE] = { + JEDEC_ERASE_SEC_REG, + (addr >> 16), + (addr >> 8), + addr, + }; + + ret = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); + if (ret || spi_poll_wip(flash, 10)) + msg_cerr("%s\n", __func__); + return ret; +} -- To view, visit https://review.coreboot.org/c/flashrom/+/59402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic33e2c1de8b0ca02df9118218a663ce63826f339 Gerrit-Change-Number: 59402 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] tests: test write protection
by Sergii Dmytruk (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Nico Huber, Angel Pons, Anastasia Klimchuk. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59075 ) Change subject: [RFC] tests: test write protection ...................................................................... Patch Set 5: (13 comments) Patchset: PS5: > Thank you for working on tests!! I did more detailed code review. […] Previous patches in the chain make tests possible. I've seen your name in `git blame` for dummyflasher, so I'd appreciate if you could take a look at those changes. File tests/meson.build: https://review.coreboot.org/c/flashrom/+/59075/comment/7dfb619c_32c0d6d1 PS5, Line 26: write_protect > I know I asked you to rename the file, but now I did more detailed review and I think the better nam […] Done File tests/tests.h: https://review.coreboot.org/c/flashrom/+/59075/comment/ede9ed34_950fdc89 PS5, Line 67: write_protection.c > chip_wp. […] Done File tests/tests.c: https://review.coreboot.org/c/flashrom/+/59075/comment/4f5eee49_5f821cc8 PS5, Line 357: write_protection > chip_wp Done https://review.coreboot.org/c/flashrom/+/59075/comment/24266dfa_3509c179 PS5, Line 364: write_protection.c > chip_wp. […] Done File tests/write_protect.c: https://review.coreboot.org/c/flashrom/+/59075/comment/a6c445d8_380d6f57 PS5, Line 27: No mocking. Using WP emulation in dummy programmer. > Maybe a complete phrase is better, like "Tests in this file do not use any mocking, because using wr […] Done https://review.coreboot.org/c/flashrom/+/59075/comment/bb68168c_c391d9c6 PS5, Line 101: invalid_setup > We can be more specific in test name, since it covers invalid range (not just any invalid setup). […] Done https://review.coreboot.org/c/flashrom/+/59075/comment/0208bba5_1a451d3f PS5, Line 117: struct flashrom_wp_chip_config cfg; > Lets move this declaration in the beginning , together with flash, layout, mock_chip. […] Done https://review.coreboot.org/c/flashrom/+/59075/comment/0379418b_bef99b4f PS5, Line 120: /* Invalid range. */ : range.start = 0x1000; : range.len = 0x1000; > why chip_len is initialised at creation time, but start/len initialised separately, few lines later? […] There used to me more checks, but changes to WP patches cased their removal. Done. https://review.coreboot.org/c/flashrom/+/59075/comment/00f10e2d_61ba7747 PS5, Line 143: wp=no > I haven't looked at the rest of your chain (tell me if I should), but this looks confusing: param sa […] Here "wp" means WP pin of the flash chip. Could rename it to "wppin" or "hwp" (hardware write-protection). The latter might be better because actual pin is negated and I wanted param to set state of hardware protection rather than state of a pin. https://review.coreboot.org/c/flashrom/+/59075/comment/3548f97f_d7ceb39a PS5, Line 152: /* Use first 4 KiB for a range. */ : range.len = 0x1000; : assert_int_equal(0, flashrom_wp_set_range(&cfg, &range)); : : /* Change range to last 4 KiB. */ : range.start = 0x00fff000; : assert_int_equal(0, flashrom_wp_set_range(&cfg, &range)); > This code looks like as if test is testing two scenarios? If there are indeed two different scenario […] Broke it into set_wp_range_dummyflasher_test_success and set_wp_mode_dummyflasher_test_success. https://review.coreboot.org/c/flashrom/+/59075/comment/949de99f_3a491bcb PS5, Line 164: /* Switch modes in configuration only. */ : assert_int_equal(0, flashrom_wp_set_mode(&cfg, WP_MODE_HARDWARE)); : assert_int_equal(0, flashrom_wp_set_mode(&cfg, WP_MODE_DISABLED)); : assert_int_equal(0, flashrom_wp_set_mode(&cfg, WP_MODE_POWER_CYCLE)); : assert_int_equal(0, flashrom_wp_set_mode(&cfg, WP_MODE_PERMANENT)); > Do all these need flash context, chip, layout? If not, extract into separate small tests that only d […] Done https://review.coreboot.org/c/flashrom/+/59075/comment/3b0d090f_ab8e3ccd PS5, Line 170: /* Switch modes in dummyflasher. */ : assert_int_equal(0, flashrom_wp_write_chip_config(&flash, &cfg)); : assert_int_equal(0, flashrom_wp_set_mode(&cfg, WP_MODE_POWER_CYCLE)); : assert_int_equal(0, flashrom_wp_write_chip_config(&flash, &cfg)); : : /* Check final mode. */ : assert_int_equal(0, flashrom_wp_read_chip_config(&flash, &cfg)); : assert_int_equal(0, flashrom_wp_get_mode(&cfg, &mode)); : assert_int_equal(WP_MODE_PERMANENT, mode); > Which ones of these need layout, if any? […] Reduced checks performed by the two tests. Layout isn't needed, but dummyflasher is needed to test how WP code behaves on saving state. -- To view, visit https://review.coreboot.org/c/flashrom/+/59075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I49af7f6d173eb4c56c22d80b01a473b8c499c0f8 Gerrit-Change-Number: 59075 Gerrit-PatchSet: 5 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Wed, 17 Nov 2021 16:42:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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