March 2020 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: lspcon_i2c_spi.c: Add support for the i2c-controlled SPI master in PS...
by Shiyu Sun (Code Review) 01 Apr '20

01 Apr '20

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39687 ) Change subject: lspcon_i2c_spi.c: Add support for the i2c-controlled SPI master in PS175/176. ...................................................................... lspcon_i2c_spi.c: Add support for the i2c-controlled SPI master in PS175/176. Usage is as follows: flashrom -p lspcon_i2c_spi:bus=X where X is the bus number. Tested with following commands, read/write/erase works good. flashrom -p lspcon_i2c_spi:bus=7 -r /tmp/foo; flashrom -p lspcon_i2c_spi:bus=7 -E; flashrom -p lspcon_i2c_spi:bus=7 -w /tmp/foo; Change-Id: I039e683252cfaf1ffef8694a3e8081b1b6b944f7 Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> --- M Makefile M flashrom.c A lspcon_i2c_spi.c M meson.build M meson_options.txt M programmer.h 6 files changed, 548 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/87/39687/1 diff --git a/Makefile b/Makefile index aa77a64..298890e 100644 --- a/Makefile +++ b/Makefile @@ -195,6 +195,11 @@ else override CONFIG_STLINKV3_SPI = no endif +ifeq ($(CONFIG_LSPCON_I2C_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_LSPCON_I2C_SPI=yes +else +override CONFIG_LSPCON_I2C_SPI = no +endif # libjaylink is also not available for DOS ifeq ($(CONFIG_JLINK_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_JLINK_SPI=yes @@ -306,6 +311,11 @@ else override CONFIG_SATAMV = no endif +ifeq ($(CONFIG_LSPCON_I2C_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_LSPCON_I2C_SPI=yes +else +override CONFIG_LSPCON_I2C_SPI = no +endif endif ifneq ($(TARGET_OS), MinGW) @@ -381,6 +391,11 @@ else override CONFIG_STLINKV3_SPI = no endif +ifeq ($(CONFIG_LSPCON_I2C_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_LSPCON_I2C_SPI=yes +else +override CONFIG_LSPCON_I2C_SPI = no +endif ifeq ($(CONFIG_CH341A_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_CH341A_SPI=yes else @@ -656,6 +671,9 @@ # Always enable STLink V3 CONFIG_STLINKV3_SPI ?= yes +# Always enable I2C SPI +CONFIG_LSPCON_I2C_SPI ?= yes + # Always enable dummy tracing for now. CONFIG_DUMMY ?= yes @@ -735,6 +753,7 @@ override CONFIG_DEVELOPERBOX_SPI = no override CONFIG_PICKIT2_SPI = no override CONFIG_STLINKV3_SPI = no +override CONFIG_LSPCON_I2C_SPI = no endif ifeq ($(CONFIG_ENABLE_LIBPCI_PROGRAMMERS), no) override CONFIG_INTERNAL = no @@ -913,6 +932,12 @@ NEED_LIBUSB1 += CONFIG_STLINKV3_SPI endif +ifeq ($(CONFIG_LSPCON_I2C_SPI), yes) +FEATURE_CFLAGS += -D'CONFIG_LSPCON_I2C_SPI=1' +PROGRAMMER_OBJS += lspcon_i2c_spi.o +NEED_LIBUSB1 += CONFIG_LSPCON_I2C_SPI +endif + ifneq ($(NEED_LIBFTDI), ) FTDILIBS := $(call debug_shell,[ -n "$(PKG_CONFIG_LIBDIR)" ] && export PKG_CONFIG_LIBDIR="$(PKG_CONFIG_LIBDIR)" ; $(PKG_CONFIG) --libs libftdi1 || $(PKG_CONFIG) --libs libftdi || printf "%s" "-lftdi -lusb") FEATURE_CFLAGS += $(call debug_shell,grep -q "FT232H := yes" .features && printf "%s" "-D'HAVE_FT232H=1'") diff --git a/flashrom.c b/flashrom.c index e541b68..3fc705a 100644 --- a/flashrom.c +++ b/flashrom.c @@ -389,6 +389,18 @@ }, #endif +#if CONFIG_LSPCON_I2C_SPI == 1 + { + .name = "lspcon_i2c_spi", + .type = OTHER, + .devs.note = "Device files /dev/i2c-*.\n", + .init = lspcon_i2c_spi_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_USBBLASTER_SPI == 1 { .name = "usbblaster_spi", diff --git a/lspcon_i2c_spi.c b/lspcon_i2c_spi.c new file mode 100644 index 0000000..d56da92 --- /dev/null +++ b/lspcon_i2c_spi.c @@ -0,0 +1,499 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2020 The Chromium OS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <stdint.h> +#include <stdio.h> +#include <string.h> +#include <time.h> +#include <errno.h> + +#include "programmer.h" +#include "spi.h" +#include "i2c_helper.h" + +#define REGISTER_ADDRESS (0x94 >> 1) +#define PAGE_ADDRESS (0x9e >> 1) +#define PAGE_SIZE 256 +#define READ_SIZE 32 +#define MAX_SPI_WAIT_RETRIES 1000 +#define FUNCTION_ERR -1 + +#define CLT2_SPI 0x82 +#define SPIEDID_BASE_ADDR2 0x8d +#define ROMADDR_BYTE1 0x8e +#define ROMADDR_BYTE2 0x8f +#define SWSPI_WDATA 0x90 + #define SWSPI_WDATA_CLEAR_STATUS 0x00 + #define SWSPI_WDATA_WRITE_REGISTER 0x01 + #define SWSPI_WDATA_READ_REGISTER 0x05 + #define SWSPI_WDATA_ENABLE_REGISTER 0x06 + #define SWSPI_WDATA_SECTOR_ERASE 0x20 + #define SWSPI_WDATA_PROTECT_BP 0x8c +#define SWSPI_RDATA 0x91 +#define SWSPI_LEN 0x92 +#define SWSPICTL 0x93 + #define SWSPICTL_ACCESS_TRIGGER 1 + #define SWSPICTL_CLEAR_PTR (1 << 1) + #define SWSPICTL_NO_READ (1 << 2) + #define SWSPICTL_ENABLE_READBACK (1 << 3) + #define SWSPICTL_MOT (1 << 4) +#define SPISTATUS 0x9e + #define SPISTATUS_BYTE_PROGRAM_FINISHED 0 + #define SPISTATUS_BYTE_PROGRAM_IN_IF 1 + #define SPISTATUS_BYTE_PROGRAM_SEND_DONE (1 << 1) + #define SPISTATUS_SECTOR_ERASE_FINISHED 0 + #define SPISTATUS_SECTOR_ERASE_IN_IF (1 << 2) + #define SPISTATUS_SECTOR_ERASE_SEND_DONE (1 << 3) + #define SPISTATUS_CHIP_ERASE_FINISHED 0 + #define SPISTATUS_CHIP_ERASE_IN_IF (1 << 4) + #define SPISTATUS_CHIP_ERASE_SEND_DONE (1 << 5) + #define SPISTATUS_FW_UPDATE_ENABLE (1 << 6) +#define WRITE_PROTECTION 0xb3 + #define WRITE_PROTECTION_ON 0 + #define WRITE_PROTECTION_OFF 0x10 +#define MPU 0xbc +#define PAGE_HW_WRITE 0xda + #define PAGE_HW_WRITE_DISABLE 0 + #define PAGE_HW_COFIG_REGISTER 0xaa + #define PAGE_HW_WRITE_ENABLE 0x55 + +struct lspcon_i2c_spi_data { + int fd; +}; + +typedef struct { + uint8_t command; + uint8_t data_size; + const uint8_t *data; + uint8_t control; +} packet_t; + +static int lspcon_i2c_spi_write_data(int fd, uint16_t addr, void *buf, uint16_t len) +{ + i2c_buffer_t data; + if (i2c_buffer_t_fill(&data, buf, len)) + return FUNCTION_ERR; + + return i2c_write(fd, addr, &data) == len ? 0 : FUNCTION_ERR; +} + +static int lspcon_i2c_spi_read_data(int fd, uint16_t addr, void *buf, uint16_t len) +{ + i2c_buffer_t data; + if (i2c_buffer_t_fill(&data, buf, len)) + return FUNCTION_ERR; + + return i2c_read(fd, addr, &data) == len ? 0 : FUNCTION_ERR; +} + +static int get_fd_from_context(struct flashctx *flash) +{ + if (!flash || !flash->mst || !flash->mst->spi.data) { + msg_perr("Unable to extract fd from flash context.\n"); + return FUNCTION_ERR; + } + + return ((const struct lspcon_i2c_spi_data *)flash->mst->spi.data)->fd; +} + +static int lspcon_i2c_spi_write_register(int fd, uint8_t i2c_register, uint8_t value) +{ + uint8_t command[] = { i2c_register, value }; + return lspcon_i2c_spi_write_data(fd, REGISTER_ADDRESS, command, 2); +} + +static int lspcon_i2c_spi_read_register(int fd, uint8_t i2c_register, uint8_t *value) +{ + uint8_t command[] = { i2c_register }; + int ret = lspcon_i2c_spi_write_data(fd, REGISTER_ADDRESS, command, 1); + ret |= lspcon_i2c_spi_read_data(fd, REGISTER_ADDRESS, value, 1); + + return ret ? FUNCTION_ERR : 0; +} + +static int lspcon_i2c_spi_register_control(int fd, packet_t *packet) +{ + int i; + int ret = lspcon_i2c_spi_write_register(fd, SWSPI_WDATA, packet->command); + if (ret) + return ret; + + /* Higher 4 bits are read size. */ + int write_size = packet->data_size & 0x0f; + for (i = 0; i < write_size; ++i) { + ret |= lspcon_i2c_spi_write_register(fd, SWSPI_WDATA, packet->data[i]); + } + + ret |= lspcon_i2c_spi_write_register(fd, SWSPI_LEN, packet->data_size); + ret |= lspcon_i2c_spi_write_register(fd, SWSPICTL, packet->control); + + return ret; +} + +static int lspcon_i2c_spi_wait_command_done(int fd, unsigned int offset, int mask) +{ + uint8_t val; + int tried = 0; + int ret = 0; + do { + ret |= lspcon_i2c_spi_read_register(fd, offset, &val); + } while(!ret && (val & mask) && ++tried < MAX_SPI_WAIT_RETRIES); + + if (tried == MAX_SPI_WAIT_RETRIES) { + msg_perr("Error: Time out on sending command.\n"); + return -MAX_SPI_WAIT_RETRIES; + } + + return (val & mask) ? FUNCTION_ERR : ret; +} + +static int lspcon_i2c_spi_wait_rom_free(int fd) +{ + uint8_t val; + int tried = 0; + int ret = 0; + ret |= lspcon_i2c_spi_wait_command_done(fd, SPISTATUS, + SPISTATUS_SECTOR_ERASE_IN_IF | SPISTATUS_SECTOR_ERASE_SEND_DONE); + if (ret) + return ret; + + do { + packet_t packet = { SWSPI_WDATA_READ_REGISTER, 0, NULL, SWSPICTL_ACCESS_TRIGGER }; + ret |= lspcon_i2c_spi_register_control(fd, &packet); + ret |= lspcon_i2c_spi_wait_command_done(fd, SWSPICTL, SWSPICTL_ACCESS_TRIGGER); + ret |= lspcon_i2c_spi_read_register(fd, SWSPI_RDATA, &val); + } while (!ret && (val & SWSPICTL_ACCESS_TRIGGER) && ++tried < MAX_SPI_WAIT_RETRIES); + + if (tried == MAX_SPI_WAIT_RETRIES) { + msg_perr("Error: Time out on waiting ROM free.\n"); + return -MAX_SPI_WAIT_RETRIES; + } + + return (val & SWSPICTL_ACCESS_TRIGGER) ? FUNCTION_ERR : ret; +} + +static int lspcon_i2c_spi_toggle_register_protection(int fd, int toggle) +{ + return lspcon_i2c_spi_write_register(fd, WRITE_PROTECTION, + toggle ? WRITE_PROTECTION_OFF : WRITE_PROTECTION_ON); +} + +static int lspcon_i2c_spi_enable_write_status_register(int fd) +{ + int ret = lspcon_i2c_spi_toggle_register_protection(fd, 1); + packet_t packet = { + SWSPI_WDATA_ENABLE_REGISTER, 0, NULL, SWSPICTL_ACCESS_TRIGGER | SWSPICTL_NO_READ }; + ret |= lspcon_i2c_spi_register_control(fd, &packet); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0); + + return ret; +} + +static int lspcon_i2c_spi_enable_write_status_register_protection(int fd) +{ + int ret = lspcon_i2c_spi_toggle_register_protection(fd, 1); + uint8_t data[] = { SWSPI_WDATA_PROTECT_BP }; + packet_t packet = { + SWSPI_WDATA_WRITE_REGISTER, 1, data, SWSPICTL_ACCESS_TRIGGER | SWSPICTL_NO_READ }; + ret |= lspcon_i2c_spi_register_control(fd, &packet); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0); + + return ret; +} + +static int lspcon_i2c_spi_disable_protection(int fd) +{ + int ret = lspcon_i2c_spi_toggle_register_protection(fd, 1); + uint8_t data[] = { SWSPI_WDATA_CLEAR_STATUS }; + packet_t packet = { + SWSPI_WDATA_WRITE_REGISTER, 1, &data[0], SWSPICTL_ACCESS_TRIGGER | SWSPICTL_NO_READ }; + ret |= lspcon_i2c_spi_register_control(fd, &packet); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0); + + return ret; +} + +static int lspcon_i2c_spi_disable_hw_write(int fd) +{ + return lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, PAGE_HW_WRITE_DISABLE); +} + +static int lspcon_i2c_spi_enable_write_protection(int fd) +{ + int ret = lspcon_i2c_spi_enable_write_status_register(fd); + ret |= lspcon_i2c_spi_enable_write_status_register_protection(fd); + ret |= lspcon_i2c_spi_wait_rom_free(fd); + ret |= lspcon_i2c_spi_disable_hw_write(fd); + + return ret; +} + +static int lspcon_i2c_spi_disable_all_protection(int fd) +{ + int ret = lspcon_i2c_spi_enable_write_status_register(fd); + ret |= lspcon_i2c_spi_disable_protection(fd); + ret |= lspcon_i2c_spi_wait_rom_free(fd); + + return ret; +} + +static int lspcon_i2c_spi_send_command(struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + unsigned int i; + if (writecnt > 16 || readcnt > 16 || writecnt == 0) { + msg_perr("Error: Invalid read/write count for send command.\n"); + return FUNCTION_ERR; + } + + int fd = get_fd_from_context(flash); + if (fd < 0) + return FUNCTION_ERR; + + int ret = lspcon_i2c_spi_disable_all_protection(fd); + ret |= lspcon_i2c_spi_enable_write_status_register(fd); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 1); + + /* First bit of writearr shuld be the command value, followed by the value to write. + Read length occupies 4 bit and represents 16 level, thus if read 1 bit, + read length should be set 0. */ + packet_t packet = { + writearr[0], (writecnt - 1) | ((readcnt - 1) << 4), &writearr[1], + SWSPICTL_ACCESS_TRIGGER | (readcnt ? 0 : SWSPICTL_NO_READ), + }; + + ret |= lspcon_i2c_spi_register_control(fd, &packet); + ret |= lspcon_i2c_spi_wait_command_done(fd, SWSPICTL, SWSPICTL_ACCESS_TRIGGER); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0); + if (ret) + return ret; + + for (i = 0; i < readcnt; ++i) { + ret |= lspcon_i2c_spi_read_register(fd, SWSPI_RDATA, &readarr[i]); + } + + ret |= lspcon_i2c_spi_wait_rom_free(fd); + + return ret; +} + +static int lspcon_i2c_spi_enable_hw_write(int fd) +{ + int ret = 0; + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, PAGE_HW_COFIG_REGISTER); + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, PAGE_HW_WRITE_ENABLE); + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, 0x50); + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, 0x41); + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, 0x52); + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, 0x44); + + return ret; +} + +static int lspcon_i2c_clt2_spi_reset(int fd) +{ + int ret = 0; + ret |= lspcon_i2c_spi_write_register(fd, CLT2_SPI, 0x20); + struct timespec wait_100_ms = { 0, 100000000 }; + nanosleep(&wait_100_ms, NULL); + ret |= lspcon_i2c_spi_write_register(fd, CLT2_SPI, 0x00); + + return ret; +} + +static int lspcon_i2c_spi_reset_mpu_stop(int fd) +{ + int ret = 0; + ret |= lspcon_i2c_spi_write_register(fd, MPU, 0xc0); // cmd mode + ret |= lspcon_i2c_spi_write_register(fd, MPU, 0x40); // stop mcu + + return ret; +} + +static int lspcon_i2c_spi_map_page(int fd, unsigned int offset) +{ + /* Page number byte, need to / PAGE_SIZE. */ + uint8_t command_byte1[] = { ROMADDR_BYTE1, (offset >> 8) & 0xff }; + uint8_t command_byte2[] = { ROMADDR_BYTE2, (offset >> 16) }; + int ret = 0; + ret |= lspcon_i2c_spi_write_data(fd, REGISTER_ADDRESS, command_byte1, 2); + ret |= lspcon_i2c_spi_write_data(fd, REGISTER_ADDRESS, command_byte2, 2); + + return ret ? FUNCTION_ERR : 0; +} + +static int lspcon_i2c_spi_read(struct flashctx *flash, uint8_t *buf, + unsigned int start, unsigned int len) +{ + unsigned int i; + int ret = 0; + if (start & 0xff) + return default_spi_read(flash, buf, start, len); + + int fd = get_fd_from_context(flash); + if (fd < 0) + return FUNCTION_ERR; + + for (i = 0; i < len; i += PAGE_SIZE) { + ret |= lspcon_i2c_spi_map_page(fd, start + i); + ret |= lspcon_i2c_spi_read_data(fd, PAGE_ADDRESS, buf + i, min(len - i, PAGE_SIZE)); + } + + return ret; +} + +static int lspcon_i2c_spi_write_page(int fd, const uint8_t *buf, unsigned int len) +{ + uint8_t write_buffer[len + 1]; + write_buffer[0] = 0; + memcpy(write_buffer + 1, buf, len); + + return lspcon_i2c_spi_write_data(fd, PAGE_ADDRESS, write_buffer, len + 1); +} + +static int lspcon_i2c_spi_write_256(struct flashctx *flash, const uint8_t *buf, + unsigned int start, unsigned int len) +{ + int ret = 0; + if (start & 0xff) + return default_spi_write_256(flash, buf, start, len); + + int fd = get_fd_from_context(flash); + if (fd < 0) + return FUNCTION_ERR; + + ret |= lspcon_i2c_spi_disable_all_protection(fd); + /* Enable hardware write and reset clt2SPI interface. */ + ret |= lspcon_i2c_spi_enable_hw_write(fd); + ret |= lspcon_i2c_clt2_spi_reset(fd); + + for (unsigned int i = 0; i < len; i += PAGE_SIZE) { + ret |= lspcon_i2c_spi_map_page(fd, start + i); + ret |= lspcon_i2c_spi_write_page(fd, buf + i, min(len - i, PAGE_SIZE)); + } + + ret |= lspcon_i2c_spi_enable_write_protection(fd); + ret |= lspcon_i2c_spi_disable_hw_write(fd); + + return ret; +} + +static int lspcon_i2c_spi_write_aai(struct flashctx *flash, const uint8_t *buf, + unsigned int start, unsigned int len) +{ + msg_perr("Error: AAI write function is not supported.\n"); + return FUNCTION_ERR; +} + +static const struct spi_master spi_master_i2c_lspcon = { + .max_data_read = 256, + .max_data_write = 256, + .command = lspcon_i2c_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = lspcon_i2c_spi_read, + .write_256 = lspcon_i2c_spi_write_256, + .write_aai = lspcon_i2c_spi_write_aai, +}; + +/* TODO: MPU still stop at this point, probably need to reset it. */ +static int lspcon_i2c_spi_shutdown(void *data) +{ + int ret = 0; + int fd = ((struct lspcon_i2c_spi_data *)data)->fd; + ret |= lspcon_i2c_spi_enable_write_protection(fd); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0); + i2c_close(fd); + free(data); + + return ret; +} + +/* TODO: remove this out of the specific spi master implementation. */ +static int get_bus() +{ + char *bus_str = extract_programmer_param("bus"); + int ret = FUNCTION_ERR; + if (bus_str) { + char *bus_suffix; + errno = 0; + int bus = (int)strtol(bus_str, &bus_suffix, 10); + if (errno != 0 || bus_str == bus_suffix) { + msg_perr("Error: Could not convert 'bus'.\n"); + goto get_bus_done; + } + + if (bus < 0 || bus > 255) { + msg_perr("Error: Value for 'bus' is out of range(0-255).\n"); + goto get_bus_done; + } + + if (strlen(bus_suffix) > 0) { + msg_perr("Error: Garbage following 'bus' value.\n"); + goto get_bus_done; + } + + msg_pinfo("Using i2c bus %i.\n", bus); + ret = bus; + goto get_bus_done; + } else { + msg_perr("Error: Bus number not specified.\n"); + } +get_bus_done: + if (bus_str) + free(bus_str); + + return ret; +} + +static int register_lspcon_i2c_spi_master(void *ptr) +{ + struct spi_master mst = spi_master_i2c_lspcon; + mst.data = ptr; + + return register_spi_master(&mst); +} + +int lspcon_i2c_spi_init(void) +{ + int lspcon_i2c_spi_bus = get_bus(); + if (lspcon_i2c_spi_bus < 0) + return FUNCTION_ERR; + + int ret = 0; + int fd = i2c_open(lspcon_i2c_spi_bus, REGISTER_ADDRESS, 0); + if (fd < 0) + return fd; + + ret |= lspcon_i2c_spi_reset_mpu_stop(fd); + if (ret) + return ret; + + struct lspcon_i2c_spi_data data = { fd }; + void *data_ptr = calloc(1, sizeof(data)); + if (!data_ptr) { + msg_perr("Unable to allocate space for extra spi master data.\n"); + return FUNCTION_ERR; + } + + memcpy(data_ptr, &data, sizeof(data)); + ret |= register_shutdown(lspcon_i2c_spi_shutdown, data_ptr); + ret |= register_lspcon_i2c_spi_master(data_ptr); + + return ret; +} diff --git a/meson.build b/meson.build index b586d9a..7494c51 100644 --- a/meson.build +++ b/meson.build @@ -63,6 +63,7 @@ config_serprog = get_option('config_serprog') config_usbblaster_spi = get_option('config_usbblaster_spi') config_stlinkv3_spi = get_option('config_stlinkv3_spi') +config_lspcon_i2c_spi = get_option('config_lspcon_i2c_spi') config_linux_i2c_helper = get_option('config_linux_i2c_helper') cargs = [] @@ -284,6 +285,10 @@ srcs += 'stlinkv3_spi.c' cargs += '-DCONFIG_STLINKV3_SPI=1' endif +if config_lspcon_i2c_spi + srcs += 'lspcon_i2c_spi.c' + cargs += '-DCONFIG_LSPCON_I2C_SPI=1' +endif # bitbanging SPI infrastructure if config_bitbang_spi diff --git a/meson_options.txt b/meson_options.txt index ff4a786..e4b4fa9 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -35,4 +35,5 @@ option('config_serprog', type : 'boolean', value : true, description : 'serprog') option('config_usbblaster_spi', type : 'boolean', value : true, description : 'Altera USB-Blaster dongles') option('config_stlinkv3_spi', type : 'boolean', value : true, description : 'STMicroelectronics STLINK-V3') +option('config_lspcon_i2c_spi', type : 'boolean', value : true, description : 'SPI control from I2C bus') option('config_linux_i2c_helper', type: 'boolean', value : true, description : 'Linux I2C control') diff --git a/programmer.h b/programmer.h index 08500c6..d47caf3 100644 --- a/programmer.h +++ b/programmer.h @@ -130,6 +130,9 @@ #if CONFIG_STLINKV3_SPI == 1 PROGRAMMER_STLINKV3_SPI, #endif +#if CONFIG_LSPCON_I2C_SPI == 1 + PROGRAMMER_LSPCON_I2C_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -810,4 +813,7 @@ struct libusb_device_handle *usb_dev_get_by_vid_pid_number( struct libusb_context *usb_ctx, uint16_t vid, uint16_t pid, unsigned int num); +/* lspcon_i2c_spi.c */ +int lspcon_i2c_spi_init(void); + #endif /* !__PROGRAMMER_H__ */ -- To view, visit https://review.coreboot.org/c/flashrom/+/39687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I039e683252cfaf1ffef8694a3e8081b1b6b944f7 Gerrit-Change-Number: 39687 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

5 27

Change in flashrom[master]: i2c_helper: Add support for the Linux I2C subsystem
by Shiyu Sun (Code Review) 01 Apr '20

01 Apr '20

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39686 ) Change subject: i2c_helper: Add support for the Linux I2C subsystem ...................................................................... i2c_helper: Add support for the Linux I2C subsystem See https://www.kernel.org/doc/Documentation/i2c/ for details. This creates common interface for I2C access functions, and adds implementation for linux I2C functions. Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> Change-Id: Ie0487824dfb71970bede17f617dbbb30ddf78c12 --- M Makefile A i2c_helper.h A i2c_helper_linux.c M meson.build M meson_options.txt 5 files changed, 241 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/86/39686/1 diff --git a/Makefile b/Makefile index 28ceab6..aa77a64 100644 --- a/Makefile +++ b/Makefile @@ -418,6 +418,10 @@ endif endif +ifeq ($(TARGET_OS), Linux) +CONFIG_LINUX_I2C_HELPER = yes +endif + ############################################################################### # General architecture-specific settings. # Like above for the OS, below we verify user-supplied options depending on the target architecture. @@ -1047,6 +1051,11 @@ PROGRAMMER_OBJS += ni845x_spi.o endif +ifeq ($(CONFIG_LINUX_I2C_HELPER), yes) +LIB_OBJS += i2c_helper_linux.o +FEATURE_CFLAGS += -D'CONFIG_LINUX_I2C_HELPER=1' +endif + ifneq ($(NEED_SERIAL), ) LIB_OBJS += serial.o custom_baud.o endif diff --git a/i2c_helper.h b/i2c_helper.h new file mode 100644 index 0000000..80dc836 --- /dev/null +++ b/i2c_helper.h @@ -0,0 +1,112 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2020 The Chromium OS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef I2C_HELPER_H +#define I2C_HELPER_H + +#include <inttypes.h> + +/** + * An convinent structure that contains the buffer size and the buffer + * pointer. Used to wrap buffer details while doing the I2C data + * transfer on both input and output. It is the client's responsibility + * to use i2c_buffer_t_fill to initialize this struct instead of + * trying to construct it directly. + */ +typedef struct { + void *buf; + uint16_t len; +} i2c_buffer_t; + +/** + * i2c_buffer_t_fill - fills in the i2c_buffer_t + * + * @i2c_buf: pointer to the be constructed. + * @buf: buffer contains data to be included in i2c_buffer_t. + * @len: length of buffer to be included in i2c_buffer_t. + * + * This function takes in a pointer to an initialized i2c_buffer_t + * object with related information, and fill in the i2c_buffer_t with + * some validation applied. The function does allow initialization with + * NULL buffer but will make sure len == 0 in such case. + * + * returns 0 on success, <0 to indicate failure + */ +static inline int i2c_buffer_t_fill(i2c_buffer_t *i2c_buf, void *buf, uint16_t len) +{ + if (!i2c_buf || (!buf && len)) + return -1; + + i2c_buf -> buf = buf; + i2c_buf -> len = len; + + return 0; +} + +/** + * i2c_open - opens the target I2C device and set the I2C slave address + * + * @bus: I2C bus number of the target device. + * @addr: I2C slave address. + * @force: whether to force set the I2C slave address. + * + * This function returns a file descriptor for the target device. It is + * the client's responsibility to pass the return value to i2c_close to + * clean up. + * + * returns fd of target device on success, <0 to indicate failure + */ +int i2c_open(int bus, uint16_t addr, int force); + +/** + * i2c_close - closes the file descriptor returned by i2c_open + * + * @fd: file descriptor to be closed. + * + * It is the client's responsibility to set fd = -1 when it is + * done with it. + * + * returns 0 on success, <0 to indicate failure + */ +int i2c_close(int fd); + +/** + * i2c_read - reads data from the I2C device + * + * @fd: file descriptor of the target device. + * @addr: I2C slave address of the target device. + * @buf_read: data struct includes reading buffer and size. + * + * This function does accept empty read and do nothing on such case. + * + * returns read length on success, <0 to indicate failure + */ +int i2c_read(int fd, uint16_t addr, i2c_buffer_t *buf_read); + +/** + * i2c_write - writes command/data into the I2C device + * + * @fd: file descriptor of the target device. + * @addr: I2C slave address of the target device. + * @buf_write: data struct includes writting buffer and size. + * + * This function does accept empty write and do nothing on such case. + * + * returns wrote length on success, <0 to indicate failure. + */ +int i2c_write(int fd, uint16_t addr, const i2c_buffer_t *buf_write); + +#endif /* !I2C_HELPER_H */ diff --git a/i2c_helper_linux.c b/i2c_helper_linux.c new file mode 100644 index 0000000..0703518 --- /dev/null +++ b/i2c_helper_linux.c @@ -0,0 +1,113 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2020 The Chromium OS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <errno.h> +#include <stdio.h> +#include <string.h> +#include <sys/fcntl.h> +#include <sys/ioctl.h> +#include <unistd.h> + +#include <stdlib.h> +#include <linux/i2c.h> +#include <linux/i2c-dev.h> + +#include "flash.h" +#include "i2c_helper.h" + +#define I2C_DEV_PREFIX "/dev/i2c-" +#define I2C_MAX_BUS 255 + +int i2c_close(int fd) +{ + return fd == -1 ? 0 : close(fd); +} + +int i2c_open(int bus, uint16_t addr, int force) +{ + int ret = -1; + int fd = -1; + + /* Maximum i2c bus number is 255(3 char), +1 for null terminated string. */ + int path_len = strlen(I2C_DEV_PREFIX) + 4; + int request = force ? I2C_SLAVE_FORCE : I2C_SLAVE; + + if (bus < 0 || bus > I2C_MAX_BUS) { + msg_perr("Invalid I2C bus %d.\n", bus); + return ret; + } + + char *dev = calloc(1, path_len); + if (!dev) { + msg_perr("Unable to allocate space for device name of len %d: %s.\n", + path_len, strerror(errno)); + goto linux_i2c_open_err; + } + + ret = snprintf(dev, path_len, "%s%d", I2C_DEV_PREFIX, bus); + if (ret < 0) { + msg_perr("Unable to join bus number to device name: %s.\n", strerror(errno)); + goto linux_i2c_open_err; + } + + fd = open(dev, O_RDWR); + if (fd < 0) { + msg_perr("Unable to open I2C device %s: %s.\n", dev, strerror(errno)); + ret = fd; + goto linux_i2c_open_err; + } + + ret = ioctl(fd, request, addr); + if (ret < 0) { + msg_perr("Unable to set I2C slave address to 0x%02x: %s.\n", addr, strerror(errno)); + i2c_close(fd); + goto linux_i2c_open_err; + } + +linux_i2c_open_err: + if (dev) + free(dev); + + return ret ? ret : fd; +} + +int i2c_read(int fd, uint16_t addr, i2c_buffer_t *buf) +{ + if (buf->len == 0) + return 0; + + int ret = ioctl(fd, I2C_SLAVE, addr); + if (ret < 0) { + msg_perr("Unable to set I2C slave address to 0x%02x: %s.\n", addr, strerror(errno)); + return ret; + } + + return read(fd, buf->buf, buf->len); +} + +int i2c_write(int fd, uint16_t addr, const i2c_buffer_t *buf) +{ + if (buf->len == 0) + return 0; + + int ret = ioctl(fd, I2C_SLAVE, addr); + if (ret < 0) { + msg_perr("Unable to set I2C slave address to 0x%02x: %s.\n", addr, strerror(errno)); + return ret; + } + + return write(fd, buf->buf, buf->len); +} diff --git a/meson.build b/meson.build index 8bb3e65..b586d9a 100644 --- a/meson.build +++ b/meson.build @@ -63,6 +63,7 @@ config_serprog = get_option('config_serprog') config_usbblaster_spi = get_option('config_usbblaster_spi') config_stlinkv3_spi = get_option('config_stlinkv3_spi') +config_linux_i2c_helper = get_option('config_linux_i2c_helper') cargs = [] deps = [] @@ -290,6 +291,11 @@ cargs += '-DCONFIG_BITBANG_SPI=1' endif +if config_linux_i2c_helper + srcs += 'i2c_helper_linux.c' + cargs += '-DCONFIG_LINUX_I2C_HELPER=1' +endif + # raw memory, MSR or PCI port I/O access if need_raw_access srcs += 'hwaccess.c' diff --git a/meson_options.txt b/meson_options.txt index 2831271..ff4a786 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -35,3 +35,4 @@ option('config_serprog', type : 'boolean', value : true, description : 'serprog') option('config_usbblaster_spi', type : 'boolean', value : true, description : 'Altera USB-Blaster dongles') option('config_stlinkv3_spi', type : 'boolean', value : true, description : 'STMicroelectronics STLINK-V3') +option('config_linux_i2c_helper', type: 'boolean', value : true, description : 'Linux I2C control') -- To view, visit https://review.coreboot.org/c/flashrom/+/39686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie0487824dfb71970bede17f617dbbb30ddf78c12 Gerrit-Change-Number: 39686 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

3 12

Change in flashrom[master]: Makefile: Fix 'CONFIG_ENABLE_LIBUSB1_PROGRAMMERS=no'
by Edward O'Callaghan (Code Review) 28 Mar '20

28 Mar '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39896 ) Change subject: Makefile: Fix 'CONFIG_ENABLE_LIBUSB1_PROGRAMMERS=no' ...................................................................... Makefile: Fix 'CONFIG_ENABLE_LIBUSB1_PROGRAMMERS=no' Turns out CONFIG_RAIDEN was missing in the LIBUSB1 as no overrides. Credit to HAOUAS Elyes for spotting this. Change-Id: I7dd26665a0133175949c11717837e9de68a1bf71 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/39896/1 diff --git a/Makefile b/Makefile index 28ceab6..4c6c4cc 100644 --- a/Makefile +++ b/Makefile @@ -730,6 +730,7 @@ override CONFIG_DIGILENT_SPI = no override CONFIG_DEVELOPERBOX_SPI = no override CONFIG_PICKIT2_SPI = no +override CONFIG_RAIDEN = no override CONFIG_STLINKV3_SPI = no endif ifeq ($(CONFIG_ENABLE_LIBPCI_PROGRAMMERS), no) -- To view, visit https://review.coreboot.org/c/flashrom/+/39896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7dd26665a0133175949c11717837e9de68a1bf71 Gerrit-Change-Number: 39896 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 8

Change in flashrom[master]: chipset_enable.c: Add more Lewisburg PCH IDs
by Angel Pons (Code Review) 27 Mar '20

27 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39780 ) Change subject: chipset_enable.c: Add more Lewisburg PCH IDs ...................................................................... chipset_enable.c: Add more Lewisburg PCH IDs Change-Id: I7ba768abfa6f19f23379e5f47a6bc099fc01d3da Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M chipset_enable.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/80/39780/1 diff --git a/chipset_enable.c b/chipset_enable.c index ae8269a..501e245 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2015,6 +2015,7 @@ {0x8086, 0xa153, B_S, NT, "Intel", "QM175", enable_flash_pch100}, {0x8086, 0xa154, B_S, NT, "Intel", "CM238", enable_flash_pch100}, {0x8086, 0xa155, B_S, NT, "Intel", "QMU185", enable_flash_pch100}, + {0x8086, 0xa1c0, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c1, B_S, NT, "Intel", "C621 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c2, B_S, NT, "Intel", "C622 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c3, B_S, NT, "Intel", "C624 Series Chipset (QS/PRQ)", enable_flash_c620}, @@ -2022,12 +2023,19 @@ {0x8086, 0xa1c5, B_S, NT, "Intel", "C626 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c6, B_S, NT, "Intel", "C627 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c7, B_S, NT, "Intel", "C628 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1c9, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1c8, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1ca, B_S, NT, "Intel", "C629 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa240, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, + {0x8086, 0xa241, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa242, B_S, NT, "Intel", "C624 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa243, B_S, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa244, B_S, NT, "Intel", "C621 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa245, B_S, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa246, B_S, NT, "Intel", "C628 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa247, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, + {0x8086, 0xa248, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, + {0x8086, 0xa249, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa2c4, B_S, NT, "Intel", "H270", enable_flash_pch100}, {0x8086, 0xa2c5, B_S, NT, "Intel", "Z270", enable_flash_pch100}, {0x8086, 0xa2c6, B_S, NT, "Intel", "Q270", enable_flash_pch100}, -- To view, visit https://review.coreboot.org/c/flashrom/+/39780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7ba768abfa6f19f23379e5f47a6bc099fc01d3da Gerrit-Change-Number: 39780 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in flashrom[master]: [RFC] udelay: Relax clock_gettime() resolution expectations
by Nico Huber (Code Review) 26 Mar '20

26 Mar '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39864 ) Change subject: [RFC] udelay: Relax clock_gettime() resolution expectations ...................................................................... [RFC] udelay: Relax clock_gettime() resolution expectations Only few programmers actually want to delay by a single microsecond. So we can relax the expected mininum resolution by default and let indivi- dual programmers override as needed. UNTESTED Change-Id: Ia24f5c8440b7cb8abcc5a1509443d0c41fd2c559 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M bitbang_spi.c M cli_classic.c M nicintel_eeprom.c M udelay.c 4 files changed, 15 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/39864/1 diff --git a/bitbang_spi.c b/bitbang_spi.c index 7c183c3..8e5b8f2 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -104,6 +104,8 @@ mst.data = master; register_spi_master(&mst); + myusec_calibrate_delay(100); + /* Only mess with the bus if we're sure nobody else uses it. */ bitbang_spi_request_bus(master); bitbang_spi_set_cs(master, 1); diff --git a/cli_classic.c b/cli_classic.c index 73cc417..2436351 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -454,7 +454,7 @@ } /* FIXME: Delay calibration should happen in programmer code. */ - myusec_calibrate_delay(); + myusec_calibrate_delay(1000); if (programmer_init(prog, pparam)) { msg_perr("Error: Programmer initialization failed.\n"); diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index 4d45f79..06284d4 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -449,6 +449,8 @@ int nicintel_ee_init(void) { + myusec_calibrate_delay(100); + if (rget_io_perms()) return 1; diff --git a/udelay.c b/udelay.c index 6c0efc4..3f0b6d1 100644 --- a/udelay.c +++ b/udelay.c @@ -52,11 +52,11 @@ } while (now.tv_sec < end.tv_sec || (now.tv_sec == end.tv_sec && now.tv_nsec < end.tv_nsec)); } -static int clock_check_res(void) +static int clock_check_res(const unsigned int resolution_ns) { struct timespec res; if (!clock_getres(clock_id, &res)) { - if (res.tv_sec == 0 && res.tv_nsec <= 100) { + if (res.tv_sec == 0 && res.tv_nsec <= resolution_ns) { msg_pinfo("Using clock_gettime for delay loops (clk_id: %d, resolution: %ldns).\n", (int)clock_id, res.tv_nsec); use_clock_gettime = true; @@ -65,7 +65,7 @@ } else if (clock_id != CLOCK_REALTIME && errno == EINVAL) { /* Try again with CLOCK_REALTIME. */ clock_id = CLOCK_REALTIME; - return clock_check_res(); + return clock_check_res(resolution_ns); } return 0; } @@ -77,7 +77,7 @@ #endif /* HAVE_CLOCK_GETTIME == 1 */ /* loops per microsecond */ -static unsigned long micro = 1; +static unsigned long micro; __attribute__ ((noinline)) void myusec_delay(unsigned int usecs) { @@ -133,15 +133,19 @@ return timeusec; } -void myusec_calibrate_delay(void) +void myusec_calibrate_delay(const unsigned int resolution_ns) { - if (clock_check_res()) + if (clock_check_res(resolution_ns)) return; + if (micro) + return; /* already calibrated */ + unsigned long count = 1000; unsigned long timeusec, resolution; int i, tries = 0; + micro = 1; msg_pinfo("Calibrating delay loop... "); resolution = measure_os_delay_resolution(); if (resolution) { -- To view, visit https://review.coreboot.org/c/flashrom/+/39864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia24f5c8440b7cb8abcc5a1509443d0c41fd2c559 Gerrit-Change-Number: 39864 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

1 2

Change in flashrom[master]: print.c: Fix alignment in print_supported_boards_helper()
by David Hendricks (Code Review) 26 Mar '20

26 Mar '20

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/37407 ) Change subject: print.c: Fix alignment in print_supported_boards_helper() ...................................................................... print.c: Fix alignment in print_supported_boards_helper() Commit 61e16e5 eliminated some duplicate logic for printing test status, but in doing so introduced a regression where some entries in `flashrom -L` output became unaligned. Up until then, it was assumed that the status field will always be 8-wide, including space for padding. This patch fixes alignment when using test_state_to_text() by making the padding consistent with other fields where a for-loop is used to pad the field up to a maximum width. Change-Id: Ie0a0b45c6466d14447aca443c2697e2048c6ef14 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M flash.h M print.c 2 files changed, 29 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/07/37407/1 diff --git a/flash.h b/flash.h index 1a9bd9f..e7b1c89 100644 --- a/flash.h +++ b/flash.h @@ -145,10 +145,11 @@ enum test_state { OK = 0, - NT = 1, /* Not tested */ - BAD, /* Known to not work */ - DEP, /* Support depends on configuration (e.g. Intel flash descriptor) */ - NA, /* Not applicable (e.g. write support on ROM chips) */ + NT = 1, /* Not tested */ + BAD, /* Known to not work */ + DEP, /* Support depends on configuration (e.g. Intel flash descriptor) */ + NA, /* Not applicable (e.g. write support on ROM chips) */ + TEST_STATE_END, /* Not a test state, just an indicator of how many are defined. */ }; #define TEST_UNTESTED (struct tested){ .probe = NT, .read = NT, .erase = NT, .write = NT } diff --git a/print.c b/print.c index 6a7ff5d..e5be6b6 100644 --- a/print.c +++ b/print.c @@ -35,6 +35,20 @@ } } +static size_t max_test_state_len(void) +{ + int i; + size_t max_len; + + for (i = max_len = 0; i < TEST_STATE_END; i++) { + size_t len = strlen(test_state_to_text(i)); + if (len > max_len) + max_len = len; + } + + return max_len; +} + static int print_supported_chips(void) { const char *delim = "/"; @@ -388,8 +402,12 @@ for (i = strlen("Board"); i < maxboardlen; i++) msg_ginfo(" "); - msg_ginfo("Status Required value for\n"); - for (i = 0; i < maxvendorlen + maxboardlen + strlen("Status "); i++) + msg_ginfo("Status"); + for (i = strlen("Status"); i < max_test_state_len(); i++) + msg_ginfo(" "); + + msg_ginfo("Required value for\n"); + for (i = 0; i < maxvendorlen + maxboardlen + max_test_state_len(); i++) msg_ginfo(" "); msg_ginfo("-p internal:mainboard=\n"); @@ -401,14 +419,10 @@ for (i = 0; i < maxboardlen - strlen(b->name); i++) msg_ginfo(" "); - switch (b->working) { - case OK: msg_ginfo("OK "); break; - case NT: msg_ginfo("NT "); break; - case DEP: msg_ginfo("DEP "); break; - case NA: msg_ginfo("N/A "); break; - case BAD: - default: msg_ginfo("BAD "); break; - } + const char *test_state = test_state_to_text(b->working); + msg_ginfo("%s", test_state); + for (i = 0; i < max_test_state_len() - strlen(test_state); i++) + msg_ginfo(" "); for (e = board_matches; e->vendor_name != NULL; e++) { if (strcmp(e->vendor_name, b->vendor) -- To view, visit https://review.coreboot.org/c/flashrom/+/37407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie0a0b45c6466d14447aca443c2697e2048c6ef14 Gerrit-Change-Number: 37407 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in flashrom[refs/meta/config]: Copy Verified label from coreboot
by David Hendricks (Code Review) 26 Mar '20

26 Mar '20

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/39640 ) Change subject: Copy Verified label from coreboot ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/39640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: refs/meta/config Gerrit-Change-Id: Ie77d5b461992c166c54d01ecda6fb509ad0a4407 Gerrit-Change-Number: 39640 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Thu, 26 Mar 2020 04:29:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in flashrom[master]: Fix segfault when running `flashrom -L`
by Angel Pons (Code Review) 26 Mar '20

26 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39826 ) Change subject: Fix segfault when running `flashrom -L` ...................................................................... Fix segfault when running `flashrom -L` The raiden_debug programmer is of type USB. However, it does not set the field `devs.dev`, which will result in a segfault when trying to print the devices of the non-existing table. FIx that by replacing `devs.note` with `devs.dev` and adding an empty device table. Since Device IDs are not used to match programmers, nothing could be added to the table. TEST=Running `flashrom -L` no longer segfaults and returns normally. Change-Id: Ie4171a11384c34abb102d1aadf86aa1b8829fc04 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M flashrom.c M programmer.h M raiden_debug_spi.c 3 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/26/39826/1 diff --git a/flashrom.c b/flashrom.c index e541b68..081b705 100644 --- a/flashrom.c +++ b/flashrom.c @@ -137,7 +137,7 @@ { .name = "raiden_debug", .type = USB, - .devs.note = "All programmer devices speaking the raiden protocol\n", + .devs.dev = devs_raiden, .init = raiden_debug_spi_init, .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, diff --git a/programmer.h b/programmer.h index 08500c6..9a41be1 100644 --- a/programmer.h +++ b/programmer.h @@ -407,6 +407,7 @@ /* raiden_debug_spi.c */ #if CONFIG_RAIDEN == 1 int raiden_debug_spi_init(void); +extern const struct dev_entry devs_raiden[]; #endif /* drkaiser.c */ diff --git a/raiden_debug_spi.c b/raiden_debug_spi.c index 6914455..173e355 100644 --- a/raiden_debug_spi.c +++ b/raiden_debug_spi.c @@ -116,6 +116,11 @@ #include <string.h> #include <unistd.h> +/* FIXME: Add some programmer IDs here */ +const struct dev_entry devs_raiden[] = { + {0}, +}; + #define GOOGLE_VID (0x18D1) #define GOOGLE_RAIDEN_SPI_SUBCLASS (0x51) #define GOOGLE_RAIDEN_SPI_PROTOCOL (0x01) -- To view, visit https://review.coreboot.org/c/flashrom/+/39826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie4171a11384c34abb102d1aadf86aa1b8829fc04 Gerrit-Change-Number: 39826 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[refs/meta/config]: Copy Verified label from coreboot
by Nico Huber (Code Review) 25 Mar '20

25 Mar '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/39640 ) Change subject: Copy Verified label from coreboot ...................................................................... Patch Set 3: Code-Review+1 Seems safe as Jenkins is re-triggered on rebase. -- To view, visit https://review.coreboot.org/c/flashrom/+/39640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: refs/meta/config Gerrit-Change-Id: Ie77d5b461992c166c54d01ecda6fb509ad0a4407 Gerrit-Change-Number: 39640 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Wed, 25 Mar 2020 23:30:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: flashchips: add support for GigaDevice GD25WQ80E
by Dino Li (Code Review) 25 Mar '20

25 Mar '20

Dino Li has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39820 ) Change subject: flashchips: add support for GigaDevice GD25WQ80E ...................................................................... flashchips: add support for GigaDevice GD25WQ80E Support GD25WQ80E, which is the internal flash of IT81202. TEST=Building flashrom and flashing FW image into IT81202 successfully. Change-Id: Ib5feaa6ecc7b11b2218e5f02c087b4331388bef8 Signed-off-by: Dino Li <Dino.Li(a)ite.com.tw> --- M flashchips.c M flashchips.h 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/20/39820/1 diff --git a/flashchips.c b/flashchips.c index 942cbc2..648fed4 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6787,6 +6787,44 @@ }, { + .vendor = "GigaDevice", + .name = "GD25WQ80E", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25WQ80E, + .total_size = 1024, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp4_srwd, + .unlock = spi_disable_blockprotect_bp4_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 3600}, + }, + + { .vendor = "Hyundai", .name = "HY29F002B", .bustype = BUS_PARALLEL, diff --git a/flashchips.h b/flashchips.h index 36990e2..dc04a5a 100644 --- a/flashchips.h +++ b/flashchips.h @@ -384,6 +384,7 @@ #define GIGADEVICE_GD25LQ32 0x6016 #define GIGADEVICE_GD25LQ64 0x6017 /* Same as GD25LQ64B (which is faster) */ #define GIGADEVICE_GD25LQ128CD 0x6018 +#define GIGADEVICE_GD25WQ80E 0x6514 #define GIGADEVICE_GD29GL064CAB 0x7E0601 #define HYUNDAI_ID 0xAD /* Hyundai */ -- To view, visit https://review.coreboot.org/c/flashrom/+/39820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib5feaa6ecc7b11b2218e5f02c087b4331388bef8 Gerrit-Change-Number: 39820 Gerrit-PatchSet: 1 Gerrit-Owner: Dino Li <Dino.Li(a)ite.com.tw> Gerrit-MessageType: newchange

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flashrom-gerrit March 2020