March 2020 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: 82802ab.c: Remove duplicated check
by Angel Pons (Code Review) 13 May '20

13 May '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38661 ) Change subject: 82802ab.c: Remove duplicated check ...................................................................... 82802ab.c: Remove duplicated check Change-Id: I5d511d7ec254bdbd9926e6d8efc308fb2339cb81 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M 82802ab.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/61/38661/1 diff --git a/82802ab.c b/82802ab.c index a44a66e..a13a4a0 100644 --- a/82802ab.c +++ b/82802ab.c @@ -89,9 +89,9 @@ chipaddr bios = flash->virtual_memory; chip_writeb(flash, 0x70, bios); - if ((chip_readb(flash, bios) & 0x80) == 0) { /* it's busy */ - while ((chip_readb(flash, bios) & 0x80) == 0) ; - } + + while ((chip_readb(flash, bios) & 0x80) == 0) /* it's busy */ + ; status = chip_readb(flash, bios); -- To view, visit https://review.coreboot.org/c/flashrom/+/38661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5d511d7ec254bdbd9926e6d8efc308fb2339cb81 Gerrit-Change-Number: 38661 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: libflashrom.map: Add missing symbols
by Edward O'Callaghan (Code Review) 05 May '20

05 May '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38993 ) Change subject: libflashrom.map: Add missing symbols ...................................................................... libflashrom.map: Add missing symbols The following symbols were missing at link-time from libflashrom: supported_flash_chips; supported_boards; supported_chipsets; Change-Id: I299928d62788c0abfe7f6cdd3e8ad8be0c49e45e Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M libflashrom.map 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/38993/1 diff --git a/libflashrom.map b/libflashrom.map index d6dd24d..9430775 100644 --- a/libflashrom.map +++ b/libflashrom.map @@ -25,6 +25,9 @@ flashrom_set_log_callback; flashrom_shutdown; flashrom_supported_programmers; + flashrom_supported_flash_chips; + flashrom_supported_boards; + flashrom_supported_chipsets; flashrom_system_info; flashrom_version_info; local: *; -- To view, visit https://review.coreboot.org/c/flashrom/+/38993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I299928d62788c0abfe7f6cdd3e8ad8be0c49e45e Gerrit-Change-Number: 38993 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in flashrom[master]: libflashrom.c: Use correct type for sizeof
by Angel Pons (Code Review) 03 May '20

03 May '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39973 ) Change subject: libflashrom.c: Use correct type for sizeof ...................................................................... libflashrom.c: Use correct type for sizeof As we want to allocate an array of `flashrom_board_info` structs, use that type in sizeof. This did not cause problems as `board_info` was at least as big as `flashrom_board_info`, but nothing guarantees it. Change-Id: I66e875d54c9a7cc59898b072b052282b0b5cbb2f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M libflashrom.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/39973/1 diff --git a/libflashrom.c b/libflashrom.c index 0dec22e..ab7e364 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -182,7 +182,7 @@ ++boards_known_size; struct flashrom_board_info *supported_boards = - malloc(boards_known_size * sizeof(*binfo)); + malloc(boards_known_size * sizeof(struct flashrom_board_info)); if (supported_boards != NULL) { for (; i < boards_known_size; ++i) { -- To view, visit https://review.coreboot.org/c/flashrom/+/39973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I66e875d54c9a7cc59898b072b052282b0b5cbb2f Gerrit-Change-Number: 39973 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: port S25FS(128S) chip from chromiumos
by Samir Ibradžić (Code Review) 28 Apr '20

28 Apr '20

Samir Ibradžić has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39822 ) Change subject: flashchips: port S25FS(128S) chip from chromiumos ...................................................................... flashchips: port S25FS(128S) chip from chromiumos This may seem too big just to support yet another flash chip, but in reality it brings support for whole new family of S25FS Spansion/Cypress flash chips. These chips require handling of some special status registers for erasing or writing, with very specific timing checks in place. For example, WIP status bit will remain being set to 1 if erase or programming errors occur, and in that case chip 'software reset' has to be performed otherwise the chip will remain unresponsive to all further commands. Also, special CR3NV register (Configuration Register 3 Nonvolatile) status bits needs to be read and set by using RDAR (ReaD Any Register) and WRAR (WRite Any Register) OP commands, and these states are needed to determine whether which type of reset feature is enabled at the time (legacy or SF25FS type) in the first place, determine whether Uniform or Hybrid sector architecture is used at the time, or programming buffer address wrap point (256 or 512 bytes). Furthermore, S25FS chip status register has to be restored to its original state (hence that ugly CHIP_RESTORE_CALLBACK) following erasing or writing, failing to do so may result in host being unable to access data on the chip at all. Finally, although this brings support for the whole family of chips, I only have one such chip to do actual testing, S25FS128S (Small Sectors), which I fully tested on ch341a and FT4232H programmers, with confirmed working probe, read, erase and write. The full summary of changes are here: flashchips: add new flashchip sctructure property: .reset add chip definitions: S25FS128S Large Sectors S25FS128S Small Sectors flash: add macro (chip_restore_func_data call-back): CHIP_RESTORE_CALLBACK flashrom: add struct: chip_restore_func_data add call-back function: register_chip_restore spi: add OP codes: CMD_RDAR, CMD_WRAR, CMD_WRAR_LEN, CMD_RSTEN, CMD_RST add register bit function definitions: CR3NV_ADDR, CR3NV_20H_NV add timers: T_W, T_RPH, T_SE spi25: refactor (based on chromiumos implementation) function: spi_poll_wip port these functions from chromiumos: probe_spi_big_spansion s25fs_software_reset s25f_legacy_software_reset s25fs_block_erase_d8 spi25_statusreg: port these functions from chromiumos: spi_restore_status s25fs_read_cr s25fs_write_cr s25fs_restore_cr3nv Change-Id: If659290874a4b9db6e71256bdef382d31b288e72 Signed-off-by: Samir Ibradzic <sibradzic(a)gmail.com> --- M chipdrivers.h M flash.h M flashchips.c M flashchips.h M flashrom.c M spi.h M spi25.c M spi25_statusreg.c 8 files changed, 415 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/22/39822/1 diff --git a/chipdrivers.h b/chipdrivers.h index cb1e877..aa24085 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -35,6 +35,9 @@ int probe_spi_res2(struct flashctx *flash); int probe_spi_res3(struct flashctx *flash); int probe_spi_at25f(struct flashctx *flash); +int probe_spi_big_spansion(struct flashctx *flash); +int s25fs_software_reset(struct flashctx *flash); +int spi_poll_wip(struct flashctx *const flash, const unsigned int poll_delay); int spi_write_enable(struct flashctx *flash); int spi_write_disable(struct flashctx *flash); int spi_block_erase_20(struct flashctx *flash, unsigned int addr, unsigned int blocklen); @@ -49,6 +52,7 @@ int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int s25fs_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_dc(struct flashctx *flash, unsigned int addr, unsigned int blocklen); erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode); @@ -60,10 +64,12 @@ int spi_exit_4ba(struct flashctx *flash); int spi_set_extended_address(struct flashctx *, uint8_t addr_high); - /* spi25_statusreg.c */ uint8_t spi_read_status_register(struct flashctx *flash); int spi_write_status_register(struct flashctx *flash, int status); +int s25fs_read_cr(struct flashctx *const flash, uint32_t addr); +int s25fs_write_cr(struct flashctx *const flash, uint32_t addr, uint8_t data); +int s25fs_restore_cr3nv(struct flashctx *const flash, uint8_t cfg); void spi_prettyprint_status_register_bit(uint8_t status, int bit); int spi_prettyprint_status_register_plain(struct flashctx *flash); int spi_prettyprint_status_register_default_welwip(struct flashctx *flash); diff --git a/flash.h b/flash.h index 1a9bd9f..1ee0f0f 100644 --- a/flash.h +++ b/flash.h @@ -54,6 +54,8 @@ #define PRIxPTR_WIDTH ((int)(sizeof(uintptr_t)*2)) int register_shutdown(int (*function) (void *data), void *data); +#define CHIP_RESTORE_CALLBACK int (*func) (struct flashrom_flashctx *flash, uint8_t status) +int register_chip_restore(CHIP_RESTORE_CALLBACK, struct flashrom_flashctx *flash, uint8_t status); int shutdown_free(void *data); void *programmer_map_flash_region(const char *descr, uintptr_t phys_addr, size_t len); void programmer_unmap_flash_region(void *virt_addr, size_t len); @@ -207,6 +209,7 @@ SPI_EDI = 1, } spi_cmd_set; + int (*reset) (struct flashctx *flash); int (*probe) (struct flashctx *flash); /* Delay after "enter/exit ID mode" commands in microseconds. diff --git a/flashchips.c b/flashchips.c index 942cbc2..8881804 100644 --- a/flashchips.c +++ b/flashchips.c @@ -49,6 +49,7 @@ * .eraseblocks[] = Array of { blocksize, blockcount } * .block_erase = Block erase function * } + * .reset = Reset Chip * .printlock = Chip lock status function * .unlock = Chip unlock function * .write = Chip write function @@ -15787,6 +15788,69 @@ { .vendor = "Spansion", + .name = "S25FS128S Large Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FS128S_L, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = s25fs_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", + .name = "S25FS128S Small Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FS128S_S, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = s25fs_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .reset = s25fs_software_reset, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", .name = "S25FL129P......1", /* uniform 256 kB sectors */ .bustype = BUS_SPI, .manufacture_id = SPANSION_ID, diff --git a/flashchips.h b/flashchips.h index 36990e2..fb2ec53 100644 --- a/flashchips.h +++ b/flashchips.h @@ -641,6 +641,8 @@ #define SPANSION_S25FL032A 0x0215 /* Same as S25FL032P, but the latter supports EDI and CFI */ #define SPANSION_S25FL064A 0x0216 /* Same as S25FL064P, but the latter supports EDI and CFI */ #define SPANSION_S25FL128 0x2018 /* Same ID for various S25FL127S, S25FL128P, S25FL128S and S25FL129P (including dual-die S70FL256P) variants (EDI supported) */ +#define SPANSION_S25FS128S_L 0x20180081 /* Large sectors. */ +#define SPANSION_S25FS128S_S 0x20180181 /* Small sectors. */ #define SPANSION_S25FL256 0x0219 #define SPANSION_S25FL512 0x0220 #define SPANSION_S25FL204 0x4013 diff --git a/flashrom.c b/flashrom.c index e541b68..178c7b6 100644 --- a/flashrom.c +++ b/flashrom.c @@ -488,6 +488,14 @@ {0}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; +#define CHIP_RESTORE_MAXFN 4 +static int chip_restore_fn_count = 0; +static struct chip_restore_func_data { + CHIP_RESTORE_CALLBACK; + struct flashctx *flash; + uint8_t status; +} chip_restore_fn[CHIP_RESTORE_MAXFN]; + #define SHUTDOWN_MAXFN 32 static int shutdown_fn_count = 0; /** @private */ @@ -538,6 +546,23 @@ return 0; } +//int register_chip_restore(int (*function) (void *data), void *data) +int register_chip_restore(CHIP_RESTORE_CALLBACK, + struct flashctx *flash, uint8_t status) +{ + if (chip_restore_fn_count >= CHIP_RESTORE_MAXFN) { + msg_perr("Tried to register more than %i chip restore" + " functions.\n", CHIP_RESTORE_MAXFN); + return 1; + } + chip_restore_fn[chip_restore_fn_count].func = func; /* from macro */ + chip_restore_fn[chip_restore_fn_count].flash = flash; + chip_restore_fn[chip_restore_fn_count].status = status; + chip_restore_fn_count++; + + return 0; +} + int programmer_init(enum programmer prog, const char *param) { int ret; diff --git a/spi.h b/spi.h index 3f45038..12063d7 100644 --- a/spi.h +++ b/spi.h @@ -101,7 +101,7 @@ #define JEDEC_BE_C4_OUTSIZE 0x04 #define JEDEC_BE_C4_INSIZE 0x00 -/* Block Erase 0xd8 is supported by EON/Macronix chips. */ +/* Block Erase 0xd8 is supported by EON/Macronix/Spansion chips. */ #define JEDEC_BE_D8 0xd8 #define JEDEC_BE_D8_OUTSIZE 0x04 #define JEDEC_BE_D8_INSIZE 0x00 @@ -116,6 +116,18 @@ #define JEDEC_SE_OUTSIZE 0x04 #define JEDEC_SE_INSIZE 0x00 +/* RADR, WRAR, RSTEN, RST & CR3NV OPs and timers on Spansion S25FS chips */ +#define CMD_RDAR 0x65 +#define CMD_WRAR 0x71 +#define CMD_WRAR_LEN 5 +#define CMD_RSTEN 0x66 +#define CMD_RST 0x99 +#define CR3NV_ADDR 0x000004 +#define CR3NV_20H_NV (1 << 3) +#define T_W 145 * 1000 /* NV register write time */ +#define T_RPH 35 /* Reset pulse hold time */ +#define T_SE 145 * 1000 /* Sector Erase Time */ + /* Page Erase 0xDB */ #define JEDEC_PE 0xDB #define JEDEC_PE_OUTSIZE 0x04 @@ -129,6 +141,7 @@ /* Status Register Bits */ #define SPI_SR_WIP (0x01 << 0) #define SPI_SR_WEL (0x01 << 1) +#define SPI_SR_ERA_ERR (0x01 << 5) #define SPI_SR_AAI (0x01 << 6) /* Write Status Enable */ diff --git a/spi25.c b/spi25.c index 2a1d492..41fa3e2 100644 --- a/spi25.c +++ b/spi25.c @@ -25,6 +25,7 @@ #include "flashchips.h" #include "chipdrivers.h" #include "programmer.h" +#include "hwaccess.h" #include "spi.h" static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes) @@ -284,13 +285,155 @@ return 0; } -static int spi_poll_wip(struct flashctx *const flash, const unsigned int poll_delay) +/* Used for probing 'big' Spansion/Cypress S25FS chips */ +int probe_spi_big_spansion(struct flashctx *flash) { - /* FIXME: We can't tell if spi_read_status_register() failed. */ + static const unsigned char cmd = JEDEC_RDID; + int ret; + unsigned char dev_id[6]; /* We care only about 6 first bytes */ + + ret = spi_send_command(flash, sizeof(cmd), sizeof(dev_id), &cmd, dev_id); + + if (!ret) { + unsigned long i; + + for (i = 0; i < sizeof(dev_id); i++) + msg_gdbg(" 0x%02x", dev_id[i]); + msg_gdbg(".\n"); + + if (dev_id[0] == flash->chip->manufacture_id) { + union { + uint8_t array[4]; + uint32_t whole; + } model_id; + + /* + * The structure of the RDID output is as follows: + * + * offset value meaning + * 00h 01h Manufacturer ID for Spansion + * 01h 20h 128 Mb capacity + * 01h 02h 256 Mb capacity + * 02h 18h 128 Mb capacity + * 02h 19h 256 Mb capacity + * 03h 4Dh Full size of the RDID output (ignored) + * 04h 00h FS: 256-kB physical sectors + * 04h 01h FS: 64-kB physical sectors + * 04h 00h FL: 256-kB physical sectors + * 04h 01h FL: Mix of 64-kB and 4KB overlayed sectors + * 05h 80h FL family + * 05h 81h FS family + * + * Need to use bytes 1, 2, 4, and 5 to properly identify one of eight + * possible chips: + * + * 2 types * 2 possible sizes * 2 possible sector layouts + * + */ + memcpy(model_id.array, dev_id + 1, 2); + memcpy(model_id.array + 2, dev_id + 4, 2); + if (be_to_cpu32(model_id.whole) == flash->chip->model_id) + return 1; + } + } + + return 0; +} + +/* Used for Spansion/Cypress S25F chips */ +static int s25f_legacy_software_reset(struct flashctx *flash) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = 1, + .writearr = (const unsigned char[]){ CMD_RSTEN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 1, + .writearr = (const unsigned char[]){ 0xf0 }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + return result; + } + /* Reset takes 35us according to data-sheet, double that for safety */ + programmer_delay(T_RPH * 2); + + return 0; +} + +/* Only for Spansion S25F chips, where legacy reset is disabled by default */ +int s25fs_software_reset(struct flashctx *flash) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = 1, + .writearr = (const unsigned char[]){ CMD_RSTEN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 1, + .writearr = (const unsigned char[]){ CMD_RST }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_cdbg("Force resetting SPI chip.\n"); + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + return result; + } + + programmer_delay(T_RPH * 2); + + return 0; +} + +int spi_poll_wip(struct flashctx *const flash, const unsigned int poll_delay) +{ + uint8_t status_reg = spi_read_status_register(flash); + /* FIXME: We don't time out. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) + while (status_reg & SPI_SR_WIP) { + /* + * The WIP bit on S25F chips remains set to 1 if erase or + * programming errors occur, so we must check for those + * errors here. If an error is encountered, do a software + * reset to clear WIP and other volatile bits, otherwise + * the chip will be unresponsive to further commands. + */ + if (status_reg & SPI_SR_ERA_ERR) { + msg_cerr("Erase error occurred\n"); + s25f_legacy_software_reset(flash); + return -1; + } + if (status_reg & (1 << 6)) { + msg_cerr("Programming error occurred\n"); + s25f_legacy_software_reset(flash); + return -1; + } programmer_delay(poll_delay); - /* FIXME: Check the status register for errors. */ + status_reg = spi_read_status_register(flash); + } + return 0; } @@ -486,6 +629,73 @@ return spi_write_cmd(flash, 0xd8, false, addr, NULL, 0, 100 * 1000); } +/* Used on Spansion/Cypress S25FS chips */ +int s25fs_block_erase_d8(struct flashctx *flash, + unsigned int addr, unsigned int blocklen) +{ + unsigned char cfg; + int result; + static int cr3nv_checked = 0; + + struct spi_command erase_cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D8_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_D8, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + /* Check if hybrid sector architecture is in use and, if so, + * switch to uniform sectors. */ + if (!cr3nv_checked) { + cfg = s25fs_read_cr(flash, CR3NV_ADDR); + if (!(cfg & CR3NV_20H_NV)) { + s25fs_write_cr(flash, CR3NV_ADDR, cfg | CR3NV_20H_NV); + s25fs_software_reset(flash); + + cfg = s25fs_read_cr(flash, CR3NV_ADDR); + if (!(cfg & CR3NV_20H_NV)) { + msg_cerr("%s: Unable to enable uniform " + "block sizes.\n", __func__); + return 1; + } + + msg_cdbg("\n%s: CR3NV updated (0x%02x -> 0x%02x)\n", + __func__, cfg, + s25fs_read_cr(flash, CR3NV_ADDR)); + /* Restore CR3V when flashrom exits */ + register_chip_restore(s25fs_restore_cr3nv, flash, cfg); + } + + cr3nv_checked = 1; + } + + result = spi_send_multicommand(flash, erase_cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + + programmer_delay(T_SE); + return spi_poll_wip(flash, 1000 * 10); +} + /* Block size is usually * 4k for PMC */ diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 8cd5a28..aa574d5 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -108,6 +108,89 @@ return readarr[0]; } +static int spi_restore_status(struct flashctx *flash, uint8_t status) +{ + msg_cdbg("restoring chip status (0x%02x)\n", status); + return spi_write_status_register(flash, status); +} + +/* 'Read Any Register' used on Spansion/Cypress S25FS chips */ +int s25fs_read_cr(struct flashctx *const flash, uint32_t addr) +{ + int result; + uint8_t cfg; + /* By default, 8 dummy cycles are necessary for variable-latency + commands such as RDAR (see CR2NV[3:0]). */ + unsigned char read_cr_cmd[] = { + CMD_RDAR, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + }; + + result = spi_send_command(flash, sizeof(read_cr_cmd), 1, read_cr_cmd, &cfg); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return -1; + } + + return cfg; +} + +/* 'Write Any Register' used on Spansion/Cypress S25FS chips */ +int s25fs_write_cr(struct flashctx *const flash, + uint32_t addr, uint8_t data) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = CMD_WRAR_LEN, + .writearr = (const unsigned char[]){ + CMD_WRAR, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + data + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return -1; + } + + programmer_delay(T_W); + return spi_poll_wip(flash, 1000 * 10); +} + +/* Used on Spansion/Cypress S25FS chips */ +int s25fs_restore_cr3nv(struct flashctx *const flash, uint8_t cfg) +{ + int ret = 0; + + msg_cdbg("Restoring CR3NV value to 0x%02x\n", cfg); + ret |= s25fs_write_cr(flash, CR3NV_ADDR, cfg); + ret |= s25fs_software_reset(flash); + return ret; +} + /* A generic block protection disable. * Tests if a protection is enabled with the block protection mask (bp_mask) and returns success otherwise. * Tests if the register bits are locked with the lock_mask (lock_mask). @@ -139,6 +222,9 @@ return 0; } + /* restore status register content upon exit */ + register_chip_restore(spi_restore_status, flash, status); + msg_cdbg("Some block protection in effect, disabling... "); if ((status & lock_mask) != 0) { msg_cdbg("\n\tNeed to disable the register lock first... "); -- To view, visit https://review.coreboot.org/c/flashrom/+/39822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If659290874a4b9db6e71256bdef382d31b288e72 Gerrit-Change-Number: 39822 Gerrit-PatchSet: 1 Gerrit-Owner: Samir Ibradžić <sibradzic(a)gmail.com> Gerrit-MessageType: newchange

5 13

Change in flashrom[master]: ft2232_spi.c: Improve handling of static buffer
by Angel Pons (Code Review) 25 Apr '20

25 Apr '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39975 ) Change subject: ft2232_spi.c: Improve handling of static buffer ...................................................................... ft2232_spi.c: Improve handling of static buffer If `buf` became NULL because of an error, subsequent calls to the `ft2232_spi_send_command` function with a smaller buffer size will result in a null pointer dereference. Add an additional null check before using `buf` to prevent that. Moreover, use `size_t` for the `bufsize` and `oldbufsize` variables, as it's what `realloc` uses. Change-Id: Idc4237ddca94c42ce2a930e6d00fd2d14e4f125c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M ft2232_spi.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/75/39975/1 diff --git a/ft2232_spi.c b/ft2232_spi.c index 1a5b2fe..84aebb3 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -468,8 +468,8 @@ static unsigned char *buf = NULL; /* failed is special. We use bitwise ops, but it is essentially bool. */ int i = 0, ret = 0, failed = 0; - int bufsize; - static int oldbufsize = 0; + size_t bufsize; + static size_t oldbufsize = 0; if (writecnt > 65536 || readcnt > 65536) return SPI_INVALID_LENGTH; @@ -477,7 +477,7 @@ /* buf is not used for the response from the chip. */ bufsize = max(writecnt + 9, 260 + 9); /* Never shrink. realloc() calls are expensive. */ - if (bufsize > oldbufsize) { + if (!buf || bufsize > oldbufsize) { buf = realloc(buf, bufsize); if (!buf) { msg_perr("Out of memory!\n"); -- To view, visit https://review.coreboot.org/c/flashrom/+/39975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idc4237ddca94c42ce2a930e6d00fd2d14e4f125c Gerrit-Change-Number: 39975 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in flashrom[master]: spi25.c: Add a null check
by Angel Pons (Code Review) 25 Apr '20

25 Apr '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39974 ) Change subject: spi25.c: Add a null check ...................................................................... spi25.c: Add a null check Change-Id: I5fcc23d81b8404af90768afa2954509bf334ab2c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M spi25.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/74/39974/1 diff --git a/spi25.c b/spi25.c index 2a1d492..0a939e7 100644 --- a/spi25.c +++ b/spi25.c @@ -427,6 +427,8 @@ msg_cerr("%s called for too long a write\n", __func__); return 1; } + if (!out_bytes && out_len > 0) + return 1; memcpy(cmd + 1 + addr_len, out_bytes, out_len); cmds[1].writecnt = 1 + addr_len + out_len; -- To view, visit https://review.coreboot.org/c/flashrom/+/39974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5fcc23d81b8404af90768afa2954509bf334ab2c Gerrit-Change-Number: 39974 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in flashrom[master]: cli_classic.c: Prevent memory leak
by Angel Pons (Code Review) 15 Apr '20

15 Apr '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39972 ) Change subject: cli_classic.c: Prevent memory leak ...................................................................... cli_classic.c: Prevent memory leak If the `--flash-contents` switch is specified more than once, it will result in a memory leak. Therefore, allow this option only once. Change-Id: I530933c9a6431580fe4645396bb363939472a80a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M cli_classic.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/39972/1 diff --git a/cli_classic.c b/cli_classic.c index 73cc417..967ff50 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -273,6 +273,9 @@ } break; case OPTION_FLASH_CONTENTS: + if (referencefile) + cli_classic_abort_usage("Error: --flash-contents specified more than once." + "Aborting.\n"); referencefile = strdup(optarg); break; case OPTION_FLASH_NAME: -- To view, visit https://review.coreboot.org/c/flashrom/+/39972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I530933c9a6431580fe4645396bb363939472a80a Gerrit-Change-Number: 39972 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in flashrom[master]: flashchips: add W25M512JV
by Joel Stanley (Code Review) 08 Apr '20

08 Apr '20

Joel Stanley has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34595 ) Change subject: flashchips: add W25M512JV ...................................................................... flashchips: add W25M512JV https://www.winbond.com/resource-files/w25m512jv%20revd%2009052017.pdf Change-Id: I8d16f0918785795cc49500435a03641b87d706e9 Signed-off-by: Joel Stanley <joel(a)jms.id.au> --- M flashchips.c M flashchips.h 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/34595/1 diff --git a/flashchips.c b/flashchips.c index 166af6a..304ebe7 100644 --- a/flashchips.c +++ b/flashchips.c @@ -15902,6 +15902,25 @@ { .vendor = "Winbond", + .name = "W25Q512JV", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q512JV, + .total_size = 64 * 1024, + .page_size = 1024, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Winbond", .name = "W25Q256JV_M", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, diff --git a/flashchips.h b/flashchips.h index 006b95e..c606161 100644 --- a/flashchips.h +++ b/flashchips.h @@ -921,6 +921,7 @@ #define WINBOND_NEX_W25Q64_V 0x4017 /* W25Q64BV, W25Q64CV; W25Q64FV in SPI mode (default) */ #define WINBOND_NEX_W25Q128_V 0x4018 /* W25Q128BV; W25Q128FV in SPI mode (default) */ #define WINBOND_NEX_W25Q256_V 0x4019 /* W25Q256FV or W25Q256JV_Q (QE=1) */ +#define WINBOND_NEX_W25Q512JV 0x4020 /* W25Q512JV */ #define WINBOND_NEX_W25Q20_W 0x5012 /* W25Q20BW */ #define WINBOND_NEX_W25Q40BW 0x5013 /* W25Q40BW */ #define WINBOND_NEX_W25Q80BW 0x5014 /* W25Q80BW */ -- To view, visit https://review.coreboot.org/c/flashrom/+/34595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8d16f0918785795cc49500435a03641b87d706e9 Gerrit-Change-Number: 34595 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Stanley Gerrit-MessageType: newchange

4 10

Change in flashrom[master]: ft2232_spi.c - change the chunksize from 256 to 270 as this value mus...
by el-coder-sb (Code Review) 08 Apr '20

08 Apr '20

el-coder-sb has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39632 ) Change subject: ft2232_spi.c - change the chunksize from 256 to 270 as this value must contain the address and cmd bytes to really make use of 256 raw data page write. ...................................................................... ft2232_spi.c - change the chunksize from 256 to 270 as this value must contain the address and cmd bytes to really make use of 256 raw data page write. For details check: https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/message/W2H… Signed-off-by: Simon Buhrow <simon.buhrow(a)posteo.de> Change-Id: Iac067a23025e9df053ab9cd4e82a98de70046c18 --- M ft2232_spi.c 1 file changed, 417 insertions(+), 417 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/32/39632/1 diff --git a/ft2232_spi.c b/ft2232_spi.c index 1a5b2fe..62cfabe 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -29,60 +29,60 @@ /* This is not defined in libftdi.h <0.20 (c7e4c09e68cfa6f5e112334aa1b3bb23401c8dc7 to be exact). * Some tests indicate that his is the only change that it is needed to support the FT232H in flashrom. */ #if !defined(HAVE_FT232H) -#define TYPE_232H 6 +#define TYPE_232H 6 #endif /* Please keep sorted by vendor ID, then device ID. */ -#define FTDI_VID 0x0403 -#define FTDI_FT2232H_PID 0x6010 -#define FTDI_FT4232H_PID 0x6011 -#define FTDI_FT232H_PID 0x6014 -#define TIAO_TUMPA_PID 0x8a98 -#define TIAO_TUMPA_LITE_PID 0x8a99 -#define AMONTEC_JTAGKEY_PID 0xCFF8 +#define FTDI_VID 0x0403 +#define FTDI_FT2232H_PID 0x6010 +#define FTDI_FT4232H_PID 0x6011 +#define FTDI_FT232H_PID 0x6014 +#define TIAO_TUMPA_PID 0x8a98 +#define TIAO_TUMPA_LITE_PID 0x8a99 +#define AMONTEC_JTAGKEY_PID 0xCFF8 -#define GOEPEL_VID 0x096C -#define GOEPEL_PICOTAP_PID 0x1449 +#define GOEPEL_VID 0x096C +#define GOEPEL_PICOTAP_PID 0x1449 -#define FIC_VID 0x1457 -#define OPENMOKO_DBGBOARD_PID 0x5118 +#define FIC_VID 0x1457 +#define OPENMOKO_DBGBOARD_PID 0x5118 -#define OLIMEX_VID 0x15BA -#define OLIMEX_ARM_OCD_PID 0x0003 -#define OLIMEX_ARM_TINY_PID 0x0004 -#define OLIMEX_ARM_OCD_H_PID 0x002B -#define OLIMEX_ARM_TINY_H_PID 0x002A +#define OLIMEX_VID 0x15BA +#define OLIMEX_ARM_OCD_PID 0x0003 +#define OLIMEX_ARM_TINY_PID 0x0004 +#define OLIMEX_ARM_OCD_H_PID 0x002B +#define OLIMEX_ARM_TINY_H_PID 0x002A -#define GOOGLE_VID 0x18D1 -#define GOOGLE_SERVO_PID 0x5001 -#define GOOGLE_SERVO_V2_PID0 0x5002 -#define GOOGLE_SERVO_V2_PID1 0x5003 +#define GOOGLE_VID 0x18D1 +#define GOOGLE_SERVO_PID 0x5001 +#define GOOGLE_SERVO_V2_PID0 0x5002 +#define GOOGLE_SERVO_V2_PID1 0x5003 const struct dev_entry devs_ft2232spi[] = { - {FTDI_VID, FTDI_FT2232H_PID, OK, "FTDI", "FT2232H"}, - {FTDI_VID, FTDI_FT4232H_PID, OK, "FTDI", "FT4232H"}, - {FTDI_VID, FTDI_FT232H_PID, OK, "FTDI", "FT232H"}, - {FTDI_VID, TIAO_TUMPA_PID, OK, "TIAO", "USB Multi-Protocol Adapter"}, - {FTDI_VID, TIAO_TUMPA_LITE_PID, OK, "TIAO", "USB Multi-Protocol Adapter Lite"}, - {FTDI_VID, AMONTEC_JTAGKEY_PID, OK, "Amontec", "JTAGkey"}, - {GOEPEL_VID, GOEPEL_PICOTAP_PID, OK, "GOEPEL", "PicoTAP"}, - {GOOGLE_VID, GOOGLE_SERVO_PID, OK, "Google", "Servo"}, - {GOOGLE_VID, GOOGLE_SERVO_V2_PID0, OK, "Google", "Servo V2 Legacy"}, - {GOOGLE_VID, GOOGLE_SERVO_V2_PID1, OK, "Google", "Servo V2"}, - {FIC_VID, OPENMOKO_DBGBOARD_PID, OK, "FIC", "OpenMoko Neo1973 Debug board (V2+)"}, - {OLIMEX_VID, OLIMEX_ARM_OCD_PID, OK, "Olimex", "ARM-USB-OCD"}, - {OLIMEX_VID, OLIMEX_ARM_TINY_PID, OK, "Olimex", "ARM-USB-TINY"}, - {OLIMEX_VID, OLIMEX_ARM_OCD_H_PID, OK, "Olimex", "ARM-USB-OCD-H"}, - {OLIMEX_VID, OLIMEX_ARM_TINY_H_PID, OK, "Olimex", "ARM-USB-TINY-H"}, + {FTDI_VID, FTDI_FT2232H_PID, OK, "FTDI", "FT2232H"}, + {FTDI_VID, FTDI_FT4232H_PID, OK, "FTDI", "FT4232H"}, + {FTDI_VID, FTDI_FT232H_PID, OK, "FTDI", "FT232H"}, + {FTDI_VID, TIAO_TUMPA_PID, OK, "TIAO", "USB Multi-Protocol Adapter"}, + {FTDI_VID, TIAO_TUMPA_LITE_PID, OK, "TIAO", "USB Multi-Protocol Adapter Lite"}, + {FTDI_VID, AMONTEC_JTAGKEY_PID, OK, "Amontec", "JTAGkey"}, + {GOEPEL_VID, GOEPEL_PICOTAP_PID, OK, "GOEPEL", "PicoTAP"}, + {GOOGLE_VID, GOOGLE_SERVO_PID, OK, "Google", "Servo"}, + {GOOGLE_VID, GOOGLE_SERVO_V2_PID0, OK, "Google", "Servo V2 Legacy"}, + {GOOGLE_VID, GOOGLE_SERVO_V2_PID1, OK, "Google", "Servo V2"}, + {FIC_VID, OPENMOKO_DBGBOARD_PID, OK, "FIC", "OpenMoko Neo1973 Debug board (V2+)"}, + {OLIMEX_VID, OLIMEX_ARM_OCD_PID, OK, "Olimex", "ARM-USB-OCD"}, + {OLIMEX_VID, OLIMEX_ARM_TINY_PID, OK, "Olimex", "ARM-USB-TINY"}, + {OLIMEX_VID, OLIMEX_ARM_OCD_H_PID, OK, "Olimex", "ARM-USB-OCD-H"}, + {OLIMEX_VID, OLIMEX_ARM_TINY_H_PID, OK, "Olimex", "ARM-USB-TINY-H"}, - {0}, + {0}, }; #define DEFAULT_DIVISOR 2 -#define BITMODE_BITBANG_NORMAL 1 -#define BITMODE_BITBANG_SPI 2 +#define BITMODE_BITBANG_NORMAL 1 +#define BITMODE_BITBANG_SPI 2 /* The variables cs_bits and pindir store the values for the "set data bits low byte" MPSSE command that * sets the initial state and the direction of the I/O pins. The pin offsets are as follows: @@ -108,442 +108,442 @@ static const char *get_ft2232_devicename(int ft2232_vid, int ft2232_type) { - int i; - for (i = 0; devs_ft2232spi[i].vendor_name != NULL; i++) { - if ((devs_ft2232spi[i].device_id == ft2232_type) && (devs_ft2232spi[i].vendor_id == ft2232_vid)) - return devs_ft2232spi[i].device_name; - } - return "unknown device"; + int i; + for (i = 0; devs_ft2232spi[i].vendor_name != NULL; i++) { + if ((devs_ft2232spi[i].device_id == ft2232_type) && (devs_ft2232spi[i].vendor_id == ft2232_vid)) + return devs_ft2232spi[i].device_name; + } + return "unknown device"; } static const char *get_ft2232_vendorname(int ft2232_vid, int ft2232_type) { - int i; - for (i = 0; devs_ft2232spi[i].vendor_name != NULL; i++) { - if ((devs_ft2232spi[i].device_id == ft2232_type) && (devs_ft2232spi[i].vendor_id == ft2232_vid)) - return devs_ft2232spi[i].vendor_name; - } - return "unknown vendor"; + int i; + for (i = 0; devs_ft2232spi[i].vendor_name != NULL; i++) { + if ((devs_ft2232spi[i].device_id == ft2232_type) && (devs_ft2232spi[i].vendor_id == ft2232_vid)) + return devs_ft2232spi[i].vendor_name; + } + return "unknown vendor"; } static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, - int size) + int size) { - int r; - r = ftdi_write_data(ftdic, (unsigned char *) buf, size); - if (r < 0) { - msg_perr("ftdi_write_data: %d, %s\n", r, ftdi_get_error_string(ftdic)); - return 1; - } - return 0; + int r; + r = ftdi_write_data(ftdic, (unsigned char *) buf, size); + if (r < 0) { + msg_perr("ftdi_write_data: %d, %s\n", r, ftdi_get_error_string(ftdic)); + return 1; + } + return 0; } static int get_buf(struct ftdi_context *ftdic, const unsigned char *buf, - int size) + int size) { - int r; + int r; - while (size > 0) { - r = ftdi_read_data(ftdic, (unsigned char *) buf, size); - if (r < 0) { - msg_perr("ftdi_read_data: %d, %s\n", r, ftdi_get_error_string(ftdic)); - return 1; - } - buf += r; - size -= r; - } - return 0; + while (size > 0) { + r = ftdi_read_data(ftdic, (unsigned char *) buf, size); + if (r < 0) { + msg_perr("ftdi_read_data: %d, %s\n", r, ftdi_get_error_string(ftdic)); + return 1; + } + buf += r; + size -= r; + } + return 0; } static int ft2232_spi_send_command(struct flashctx *flash, - unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, - unsigned char *readarr); + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr); static const struct spi_master spi_master_ft2232 = { - .features = SPI_MASTER_4BA, - .max_data_read = 64 * 1024, - .max_data_write = 256, - .command = ft2232_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, + .features = SPI_MASTER_4BA, + .max_data_read = 64 * 1024, + .max_data_write = 256, + .command = ft2232_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, }; /* Returns 0 upon success, a negative number upon errors. */ int ft2232_spi_init(void) { - int ret = 0; - struct ftdi_context *ftdic = &ftdic_context; - unsigned char buf[512]; - int ft2232_vid = FTDI_VID; - int ft2232_type = FTDI_FT4232H_PID; - int channel_count = 4; /* Stores the number of channels of the device. */ - enum ftdi_interface ft2232_interface = INTERFACE_A; - /* - * The 'H' chips can run with an internal clock of either 12 MHz or 60 MHz, - * but the non-H chips can only run at 12 MHz. We enable the divide-by-5 - * prescaler on the former to run on the same speed. - */ - uint8_t clock_5x = 1; - /* In addition to the prescaler mentioned above there is also another - * configurable one on all versions of the chips. Its divisor div can be - * set by a 16 bit value x according to the following formula: - * div = (1 + x) * 2 <-> x = div / 2 - 1 - * Hence the expressible divisors are all even numbers between 2 and - * 2^17 (=131072) resulting in SCK frequencies of 6 MHz down to about - * 92 Hz for 12 MHz inputs. - */ - uint32_t divisor = DEFAULT_DIVISOR; - int f; - char *arg; - double mpsse_clk; + int ret = 0; + struct ftdi_context *ftdic = &ftdic_context; + unsigned char buf[512]; + int ft2232_vid = FTDI_VID; + int ft2232_type = FTDI_FT4232H_PID; + int channel_count = 4; /* Stores the number of channels of the device. */ + enum ftdi_interface ft2232_interface = INTERFACE_A; + /* + * The 'H' chips can run with an internal clock of either 12 MHz or 60 MHz, + * but the non-H chips can only run at 12 MHz. We enable the divide-by-5 + * prescaler on the former to run on the same speed. + */ + uint8_t clock_5x = 1; + /* In addition to the prescaler mentioned above there is also another + * configurable one on all versions of the chips. Its divisor div can be + * set by a 16 bit value x according to the following formula: + * div = (1 + x) * 2 <-> x = div / 2 - 1 + * Hence the expressible divisors are all even numbers between 2 and + * 2^17 (=131072) resulting in SCK frequencies of 6 MHz down to about + * 92 Hz for 12 MHz inputs. + */ + uint32_t divisor = DEFAULT_DIVISOR; + int f; + char *arg; + double mpsse_clk; - arg = extract_programmer_param("type"); - if (arg) { - if (!strcasecmp(arg, "2232H")) { - ft2232_type = FTDI_FT2232H_PID; - channel_count = 2; - } else if (!strcasecmp(arg, "4232H")) { - ft2232_type = FTDI_FT4232H_PID; - channel_count = 4; - } else if (!strcasecmp(arg, "232H")) { - ft2232_type = FTDI_FT232H_PID; - channel_count = 1; - } else if (!strcasecmp(arg, "jtagkey")) { - ft2232_type = AMONTEC_JTAGKEY_PID; - channel_count = 2; - /* JTAGkey(2) needs to enable its output via Bit4 / GPIOL0 - * value: 0x18 OE=high, CS=high, DI=low, DO=low, SK=low - * dir: 0x1b OE=output, CS=output, DI=input, DO=output, SK=output */ - cs_bits = 0x18; - pindir = 0x1b; - } else if (!strcasecmp(arg, "picotap")) { - ft2232_vid = GOEPEL_VID; - ft2232_type = GOEPEL_PICOTAP_PID; - channel_count = 2; - } else if (!strcasecmp(arg, "tumpa")) { - /* Interface A is SPI1, B is SPI2. */ - ft2232_type = TIAO_TUMPA_PID; - channel_count = 2; - } else if (!strcasecmp(arg, "tumpalite")) { - /* Only one channel is used on lite edition */ - ft2232_type = TIAO_TUMPA_LITE_PID; - channel_count = 1; - } else if (!strcasecmp(arg, "busblaster")) { - /* In its default configuration it is a jtagkey clone */ - ft2232_type = FTDI_FT2232H_PID; - channel_count = 2; - cs_bits = 0x18; - pindir = 0x1b; - } else if (!strcasecmp(arg, "openmoko")) { - ft2232_vid = FIC_VID; - ft2232_type = OPENMOKO_DBGBOARD_PID; - channel_count = 2; - } else if (!strcasecmp(arg, "arm-usb-ocd")) { - ft2232_vid = OLIMEX_VID; - ft2232_type = OLIMEX_ARM_OCD_PID; - channel_count = 2; - /* arm-usb-ocd(-h) has an output buffer that needs to be enabled by pulling ADBUS4 low. - * value: 0x08 #OE=low, CS=high, DI=low, DO=low, SK=low - * dir: 0x1b #OE=output, CS=output, DI=input, DO=output, SK=output */ - cs_bits = 0x08; - pindir = 0x1b; - } else if (!strcasecmp(arg, "arm-usb-tiny")) { - ft2232_vid = OLIMEX_VID; - ft2232_type = OLIMEX_ARM_TINY_PID; - channel_count = 2; - } else if (!strcasecmp(arg, "arm-usb-ocd-h")) { - ft2232_vid = OLIMEX_VID; - ft2232_type = OLIMEX_ARM_OCD_H_PID; - channel_count = 2; - /* See arm-usb-ocd */ - cs_bits = 0x08; - pindir = 0x1b; - } else if (!strcasecmp(arg, "arm-usb-tiny-h")) { - ft2232_vid = OLIMEX_VID; - ft2232_type = OLIMEX_ARM_TINY_H_PID; - channel_count = 2; - } else if (!strcasecmp(arg, "google-servo")) { - ft2232_vid = GOOGLE_VID; - ft2232_type = GOOGLE_SERVO_PID; - } else if (!strcasecmp(arg, "google-servo-v2")) { - ft2232_vid = GOOGLE_VID; - ft2232_type = GOOGLE_SERVO_V2_PID1; - /* Default divisor is too fast, and chip ID fails */ - divisor = 6; - } else if (!strcasecmp(arg, "google-servo-v2-legacy")) { - ft2232_vid = GOOGLE_VID; - ft2232_type = GOOGLE_SERVO_V2_PID0; - } else if (!strcasecmp(arg, "flyswatter")) { - ft2232_type = FTDI_FT2232H_PID; - channel_count = 2; - /* Flyswatter and Flyswatter-2 require GPIO bits 0x80 - * and 0x40 to be driven low to enable output buffers */ - pindir = 0xcb; - } else { - msg_perr("Error: Invalid device type specified.\n"); - free(arg); - return -1; - } - } - free(arg); + arg = extract_programmer_param("type"); + if (arg) { + if (!strcasecmp(arg, "2232H")) { + ft2232_type = FTDI_FT2232H_PID; + channel_count = 2; + } else if (!strcasecmp(arg, "4232H")) { + ft2232_type = FTDI_FT4232H_PID; + channel_count = 4; + } else if (!strcasecmp(arg, "232H")) { + ft2232_type = FTDI_FT232H_PID; + channel_count = 1; + } else if (!strcasecmp(arg, "jtagkey")) { + ft2232_type = AMONTEC_JTAGKEY_PID; + channel_count = 2; + /* JTAGkey(2) needs to enable its output via Bit4 / GPIOL0 + * value: 0x18 OE=high, CS=high, DI=low, DO=low, SK=low + * dir: 0x1b OE=output, CS=output, DI=input, DO=output, SK=output */ + cs_bits = 0x18; + pindir = 0x1b; + } else if (!strcasecmp(arg, "picotap")) { + ft2232_vid = GOEPEL_VID; + ft2232_type = GOEPEL_PICOTAP_PID; + channel_count = 2; + } else if (!strcasecmp(arg, "tumpa")) { + /* Interface A is SPI1, B is SPI2. */ + ft2232_type = TIAO_TUMPA_PID; + channel_count = 2; + } else if (!strcasecmp(arg, "tumpalite")) { + /* Only one channel is used on lite edition */ + ft2232_type = TIAO_TUMPA_LITE_PID; + channel_count = 1; + } else if (!strcasecmp(arg, "busblaster")) { + /* In its default configuration it is a jtagkey clone */ + ft2232_type = FTDI_FT2232H_PID; + channel_count = 2; + cs_bits = 0x18; + pindir = 0x1b; + } else if (!strcasecmp(arg, "openmoko")) { + ft2232_vid = FIC_VID; + ft2232_type = OPENMOKO_DBGBOARD_PID; + channel_count = 2; + } else if (!strcasecmp(arg, "arm-usb-ocd")) { + ft2232_vid = OLIMEX_VID; + ft2232_type = OLIMEX_ARM_OCD_PID; + channel_count = 2; + /* arm-usb-ocd(-h) has an output buffer that needs to be enabled by pulling ADBUS4 low. + * value: 0x08 #OE=low, CS=high, DI=low, DO=low, SK=low + * dir: 0x1b #OE=output, CS=output, DI=input, DO=output, SK=output */ + cs_bits = 0x08; + pindir = 0x1b; + } else if (!strcasecmp(arg, "arm-usb-tiny")) { + ft2232_vid = OLIMEX_VID; + ft2232_type = OLIMEX_ARM_TINY_PID; + channel_count = 2; + } else if (!strcasecmp(arg, "arm-usb-ocd-h")) { + ft2232_vid = OLIMEX_VID; + ft2232_type = OLIMEX_ARM_OCD_H_PID; + channel_count = 2; + /* See arm-usb-ocd */ + cs_bits = 0x08; + pindir = 0x1b; + } else if (!strcasecmp(arg, "arm-usb-tiny-h")) { + ft2232_vid = OLIMEX_VID; + ft2232_type = OLIMEX_ARM_TINY_H_PID; + channel_count = 2; + } else if (!strcasecmp(arg, "google-servo")) { + ft2232_vid = GOOGLE_VID; + ft2232_type = GOOGLE_SERVO_PID; + } else if (!strcasecmp(arg, "google-servo-v2")) { + ft2232_vid = GOOGLE_VID; + ft2232_type = GOOGLE_SERVO_V2_PID1; + /* Default divisor is too fast, and chip ID fails */ + divisor = 6; + } else if (!strcasecmp(arg, "google-servo-v2-legacy")) { + ft2232_vid = GOOGLE_VID; + ft2232_type = GOOGLE_SERVO_V2_PID0; + } else if (!strcasecmp(arg, "flyswatter")) { + ft2232_type = FTDI_FT2232H_PID; + channel_count = 2; + /* Flyswatter and Flyswatter-2 require GPIO bits 0x80 + * and 0x40 to be driven low to enable output buffers */ + pindir = 0xcb; + } else { + msg_perr("Error: Invalid device type specified.\n"); + free(arg); + return -1; + } + } + free(arg); - arg = extract_programmer_param("port"); - if (arg) { - switch (toupper((unsigned char)*arg)) { - case 'A': - ft2232_interface = INTERFACE_A; - break; - case 'B': - ft2232_interface = INTERFACE_B; - if (channel_count < 2) - channel_count = -1; - break; - case 'C': - ft2232_interface = INTERFACE_C; - if (channel_count < 3) - channel_count = -1; - break; - case 'D': - ft2232_interface = INTERFACE_D; - if (channel_count < 4) - channel_count = -1; - break; - default: - channel_count = -1; - break; - } - if (channel_count < 0 || strlen(arg) != 1) { - msg_perr("Error: Invalid channel/port/interface specified: \"%s\".\n", arg); - free(arg); - return -2; - } - } - free(arg); + arg = extract_programmer_param("port"); + if (arg) { + switch (toupper((unsigned char)*arg)) { + case 'A': + ft2232_interface = INTERFACE_A; + break; + case 'B': + ft2232_interface = INTERFACE_B; + if (channel_count < 2) + channel_count = -1; + break; + case 'C': + ft2232_interface = INTERFACE_C; + if (channel_count < 3) + channel_count = -1; + break; + case 'D': + ft2232_interface = INTERFACE_D; + if (channel_count < 4) + channel_count = -1; + break; + default: + channel_count = -1; + break; + } + if (channel_count < 0 || strlen(arg) != 1) { + msg_perr("Error: Invalid channel/port/interface specified: \"%s\".\n", arg); + free(arg); + return -2; + } + } + free(arg); - arg = extract_programmer_param("divisor"); - if (arg && strlen(arg)) { - unsigned int temp = 0; - char *endptr; - temp = strtoul(arg, &endptr, 10); - if (*endptr || temp < 2 || temp > 131072 || temp & 0x1) { - msg_perr("Error: Invalid SPI frequency divisor specified: \"%s\".\n" - "Valid are even values between 2 and 131072.\n", arg); - free(arg); - return -2; - } - divisor = (uint32_t)temp; - } - free(arg); + arg = extract_programmer_param("divisor"); + if (arg && strlen(arg)) { + unsigned int temp = 0; + char *endptr; + temp = strtoul(arg, &endptr, 10); + if (*endptr || temp < 2 || temp > 131072 || temp & 0x1) { + msg_perr("Error: Invalid SPI frequency divisor specified: \"%s\".\n" + "Valid are even values between 2 and 131072.\n", arg); + free(arg); + return -2; + } + divisor = (uint32_t)temp; + } + free(arg); - /* Allows setting multiple GPIOL states, for example: csgpiol=012 */ - arg = extract_programmer_param("csgpiol"); - if (arg) { - unsigned int ngpios = strlen(arg); - for (unsigned int i = 0; i <= ngpios; i++) { - int temp = arg[i] - '0'; - if (ngpios == 0 || (ngpios != i && (temp < 0 || temp > 3))) { - msg_perr("Error: Invalid GPIOLs specified: \"%s\".\n" - "Valid values are numbers between 0 and 3. " - "Multiple GPIOLs can be specified.\n", arg); - free(arg); - return -2; - } else { - unsigned int pin = temp + 4; - cs_bits |= 1 << pin; - pindir |= 1 << pin; - } - } - } - free(arg); + /* Allows setting multiple GPIOL states, for example: csgpiol=012 */ + arg = extract_programmer_param("csgpiol"); + if (arg) { + unsigned int ngpios = strlen(arg); + for (unsigned int i = 0; i <= ngpios; i++) { + int temp = arg[i] - '0'; + if (ngpios == 0 || (ngpios != i && (temp < 0 || temp > 3))) { + msg_perr("Error: Invalid GPIOLs specified: \"%s\".\n" + "Valid values are numbers between 0 and 3. " + "Multiple GPIOLs can be specified.\n", arg); + free(arg); + return -2; + } else { + unsigned int pin = temp + 4; + cs_bits |= 1 << pin; + pindir |= 1 << pin; + } + } + } + free(arg); - msg_pdbg("Using device type %s %s ", - get_ft2232_vendorname(ft2232_vid, ft2232_type), - get_ft2232_devicename(ft2232_vid, ft2232_type)); - msg_pdbg("channel %s.\n", - (ft2232_interface == INTERFACE_A) ? "A" : - (ft2232_interface == INTERFACE_B) ? "B" : - (ft2232_interface == INTERFACE_C) ? "C" : "D"); + msg_pdbg("Using device type %s %s ", + get_ft2232_vendorname(ft2232_vid, ft2232_type), + get_ft2232_devicename(ft2232_vid, ft2232_type)); + msg_pdbg("channel %s.\n", + (ft2232_interface == INTERFACE_A) ? "A" : + (ft2232_interface == INTERFACE_B) ? "B" : + (ft2232_interface == INTERFACE_C) ? "C" : "D"); - if (ftdi_init(ftdic) < 0) { - msg_perr("ftdi_init failed.\n"); - return -3; - } + if (ftdi_init(ftdic) < 0) { + msg_perr("ftdi_init failed.\n"); + return -3; + } - if (ftdi_set_interface(ftdic, ft2232_interface) < 0) { - msg_perr("Unable to select channel (%s).\n", ftdi_get_error_string(ftdic)); - } + if (ftdi_set_interface(ftdic, ft2232_interface) < 0) { + msg_perr("Unable to select channel (%s).\n", ftdi_get_error_string(ftdic)); + } - arg = extract_programmer_param("serial"); - f = ftdi_usb_open_desc(ftdic, ft2232_vid, ft2232_type, NULL, arg); - free(arg); + arg = extract_programmer_param("serial"); + f = ftdi_usb_open_desc(ftdic, ft2232_vid, ft2232_type, NULL, arg); + free(arg); - if (f < 0 && f != -5) { - msg_perr("Unable to open FTDI device: %d (%s).\n", f, ftdi_get_error_string(ftdic)); - return -4; - } + if (f < 0 && f != -5) { + msg_perr("Unable to open FTDI device: %d (%s).\n", f, ftdi_get_error_string(ftdic)); + return -4; + } - if (ftdic->type != TYPE_2232H && ftdic->type != TYPE_4232H && ftdic->type != TYPE_232H) { - msg_pdbg("FTDI chip type %d is not high-speed.\n", ftdic->type); - clock_5x = 0; - } + if (ftdic->type != TYPE_2232H && ftdic->type != TYPE_4232H && ftdic->type != TYPE_232H) { + msg_pdbg("FTDI chip type %d is not high-speed.\n", ftdic->type); + clock_5x = 0; + } - if (ftdi_usb_reset(ftdic) < 0) { - msg_perr("Unable to reset FTDI device (%s).\n", ftdi_get_error_string(ftdic)); - } + if (ftdi_usb_reset(ftdic) < 0) { + msg_perr("Unable to reset FTDI device (%s).\n", ftdi_get_error_string(ftdic)); + } - if (ftdi_set_latency_timer(ftdic, 2) < 0) { - msg_perr("Unable to set latency timer (%s).\n", ftdi_get_error_string(ftdic)); - } + if (ftdi_set_latency_timer(ftdic, 2) < 0) { + msg_perr("Unable to set latency timer (%s).\n", ftdi_get_error_string(ftdic)); + } - if (ftdi_write_data_set_chunksize(ftdic, 256)) { - msg_perr("Unable to set chunk size (%s).\n", ftdi_get_error_string(ftdic)); - } + if (ftdi_write_data_set_chunksize(ftdic, 270)) { + msg_perr("Unable to set chunk size (%s).\n", ftdi_get_error_string(ftdic)); + } - if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_SPI) < 0) { - msg_perr("Unable to set bitmode to SPI (%s).\n", ftdi_get_error_string(ftdic)); - } + if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_SPI) < 0) { + msg_perr("Unable to set bitmode to SPI (%s).\n", ftdi_get_error_string(ftdic)); + } - if (clock_5x) { - msg_pdbg("Disable divide-by-5 front stage\n"); - buf[0] = 0x8a; /* Disable divide-by-5. DIS_DIV_5 in newer libftdi */ - if (send_buf(ftdic, buf, 1)) { - ret = -5; - goto ftdi_err; - } - mpsse_clk = 60.0; - } else { - mpsse_clk = 12.0; - } + if (clock_5x) { + msg_pdbg("Disable divide-by-5 front stage\n"); + buf[0] = 0x8a; /* Disable divide-by-5. DIS_DIV_5 in newer libftdi */ + if (send_buf(ftdic, buf, 1)) { + ret = -5; + goto ftdi_err; + } + mpsse_clk = 60.0; + } else { + mpsse_clk = 12.0; + } - msg_pdbg("Set clock divisor\n"); - buf[0] = TCK_DIVISOR; - buf[1] = (divisor / 2 - 1) & 0xff; - buf[2] = ((divisor / 2 - 1) >> 8) & 0xff; - if (send_buf(ftdic, buf, 3)) { - ret = -6; - goto ftdi_err; - } + msg_pdbg("Set clock divisor\n"); + buf[0] = TCK_DIVISOR; + buf[1] = (divisor / 2 - 1) & 0xff; + buf[2] = ((divisor / 2 - 1) >> 8) & 0xff; + if (send_buf(ftdic, buf, 3)) { + ret = -6; + goto ftdi_err; + } - msg_pdbg("MPSSE clock: %f MHz, divisor: %u, SPI clock: %f MHz\n", - mpsse_clk, divisor, (double)(mpsse_clk / divisor)); + msg_pdbg("MPSSE clock: %f MHz, divisor: %u, SPI clock: %f MHz\n", + mpsse_clk, divisor, (double)(mpsse_clk / divisor)); - /* Disconnect TDI/DO to TDO/DI for loopback. */ - msg_pdbg("No loopback of TDI/DO TDO/DI\n"); - buf[0] = LOOPBACK_END; - if (send_buf(ftdic, buf, 1)) { - ret = -7; - goto ftdi_err; - } + /* Disconnect TDI/DO to TDO/DI for loopback. */ + msg_pdbg("No loopback of TDI/DO TDO/DI\n"); + buf[0] = LOOPBACK_END; + if (send_buf(ftdic, buf, 1)) { + ret = -7; + goto ftdi_err; + } - msg_pdbg("Set data bits\n"); - buf[0] = SET_BITS_LOW; - buf[1] = cs_bits; - buf[2] = pindir; - if (send_buf(ftdic, buf, 3)) { - ret = -8; - goto ftdi_err; - } + msg_pdbg("Set data bits\n"); + buf[0] = SET_BITS_LOW; + buf[1] = cs_bits; + buf[2] = pindir; + if (send_buf(ftdic, buf, 3)) { + ret = -8; + goto ftdi_err; + } - register_spi_master(&spi_master_ft2232); + register_spi_master(&spi_master_ft2232); - return 0; + return 0; ftdi_err: - if ((f = ftdi_usb_close(ftdic)) < 0) { - msg_perr("Unable to close FTDI device: %d (%s)\n", f, ftdi_get_error_string(ftdic)); - } - return ret; + if ((f = ftdi_usb_close(ftdic)) < 0) { + msg_perr("Unable to close FTDI device: %d (%s)\n", f, ftdi_get_error_string(ftdic)); + } + return ret; } /* Returns 0 upon success, a negative number upon errors. */ static int ft2232_spi_send_command(struct flashctx *flash, - unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, - unsigned char *readarr) + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) { - struct ftdi_context *ftdic = &ftdic_context; - static unsigned char *buf = NULL; - /* failed is special. We use bitwise ops, but it is essentially bool. */ - int i = 0, ret = 0, failed = 0; - int bufsize; - static int oldbufsize = 0; + struct ftdi_context *ftdic = &ftdic_context; + static unsigned char *buf = NULL; + /* failed is special. We use bitwise ops, but it is essentially bool. */ + int i = 0, ret = 0, failed = 0; + int bufsize; + static int oldbufsize = 0; - if (writecnt > 65536 || readcnt > 65536) - return SPI_INVALID_LENGTH; + if (writecnt > 65536 || readcnt > 65536) + return SPI_INVALID_LENGTH; - /* buf is not used for the response from the chip. */ - bufsize = max(writecnt + 9, 260 + 9); - /* Never shrink. realloc() calls are expensive. */ - if (bufsize > oldbufsize) { - buf = realloc(buf, bufsize); - if (!buf) { - msg_perr("Out of memory!\n"); - /* TODO: What to do with buf? */ - return SPI_GENERIC_ERROR; - } - oldbufsize = bufsize; - } + /* buf is not used for the response from the chip. */ + bufsize = max(writecnt + 9, 260 + 9); + /* Never shrink. realloc() calls are expensive. */ + if (bufsize > oldbufsize) { + buf = realloc(buf, bufsize); + if (!buf) { + msg_perr("Out of memory!\n"); + /* TODO: What to do with buf? */ + return SPI_GENERIC_ERROR; + } + oldbufsize = bufsize; + } - /* - * Minimize USB transfers by packing as many commands as possible - * together. If we're not expecting to read, we can assert CS#, write, - * and deassert CS# all in one shot. If reading, we do three separate - * operations. - */ - msg_pspew("Assert CS#\n"); - buf[i++] = SET_BITS_LOW; - buf[i++] = ~ 0x08 & cs_bits; /* assert CS (3rd) bit only */ - buf[i++] = pindir; + /* + * Minimize USB transfers by packing as many commands as possible + * together. If we're not expecting to read, we can assert CS#, write, + * and deassert CS# all in one shot. If reading, we do three separate + * operations. + */ + msg_pspew("Assert CS#\n"); + buf[i++] = SET_BITS_LOW; + buf[i++] = ~ 0x08 & cs_bits; /* assert CS (3rd) bit only */ + buf[i++] = pindir; - if (writecnt) { - buf[i++] = MPSSE_DO_WRITE | MPSSE_WRITE_NEG; - buf[i++] = (writecnt - 1) & 0xff; - buf[i++] = ((writecnt - 1) >> 8) & 0xff; - memcpy(buf + i, writearr, writecnt); - i += writecnt; - } + if (writecnt) { + buf[i++] = MPSSE_DO_WRITE | MPSSE_WRITE_NEG; + buf[i++] = (writecnt - 1) & 0xff; + buf[i++] = ((writecnt - 1) >> 8) & 0xff; + memcpy(buf + i, writearr, writecnt); + i += writecnt; + } - /* - * Optionally terminate this batch of commands with a - * read command, then do the fetch of the results. - */ - if (readcnt) { - buf[i++] = MPSSE_DO_READ; - buf[i++] = (readcnt - 1) & 0xff; - buf[i++] = ((readcnt - 1) >> 8) & 0xff; - ret = send_buf(ftdic, buf, i); - failed = ret; - /* We can't abort here, we still have to deassert CS#. */ - if (ret) - msg_perr("send_buf failed before read: %i\n", ret); - i = 0; - if (ret == 0) { - /* - * FIXME: This is unreliable. There's no guarantee that - * we read the response directly after sending the read - * command. We may be scheduled out etc. - */ - ret = get_buf(ftdic, readarr, readcnt); - failed |= ret; - /* We can't abort here either. */ - if (ret) - msg_perr("get_buf failed: %i\n", ret); - } - } + /* + * Optionally terminate this batch of commands with a + * read command, then do the fetch of the results. + */ + if (readcnt) { + buf[i++] = MPSSE_DO_READ; + buf[i++] = (readcnt - 1) & 0xff; + buf[i++] = ((readcnt - 1) >> 8) & 0xff; + ret = send_buf(ftdic, buf, i); + failed = ret; + /* We can't abort here, we still have to deassert CS#. */ + if (ret) + msg_perr("send_buf failed before read: %i\n", ret); + i = 0; + if (ret == 0) { + /* + * FIXME: This is unreliable. There's no guarantee that + * we read the response directly after sending the read + * command. We may be scheduled out etc. + */ + ret = get_buf(ftdic, readarr, readcnt); + failed |= ret; + /* We can't abort here either. */ + if (ret) + msg_perr("get_buf failed: %i\n", ret); + } + } - msg_pspew("De-assert CS#\n"); - buf[i++] = SET_BITS_LOW; - buf[i++] = cs_bits; - buf[i++] = pindir; - ret = send_buf(ftdic, buf, i); - failed |= ret; - if (ret) - msg_perr("send_buf failed at end: %i\n", ret); + msg_pspew("De-assert CS#\n"); + buf[i++] = SET_BITS_LOW; + buf[i++] = cs_bits; + buf[i++] = pindir; + ret = send_buf(ftdic, buf, i); + failed |= ret; + if (ret) + msg_perr("send_buf failed at end: %i\n", ret); - return failed ? -1 : 0; + return failed ? -1 : 0; } #endif -- To view, visit https://review.coreboot.org/c/flashrom/+/39632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iac067a23025e9df053ab9cd4e82a98de70046c18 Gerrit-Change-Number: 39632 Gerrit-PatchSet: 1 Gerrit-Owner: el-coder-sb Gerrit-MessageType: newchange

3 19

Change in flashrom[master]: lspcon_i2c_spi.c: Add support for the i2c-controlled SPI master in PS...
by Shiyu Sun (Code Review) 01 Apr '20

01 Apr '20

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39687 ) Change subject: lspcon_i2c_spi.c: Add support for the i2c-controlled SPI master in PS175/176. ...................................................................... lspcon_i2c_spi.c: Add support for the i2c-controlled SPI master in PS175/176. Usage is as follows: flashrom -p lspcon_i2c_spi:bus=X where X is the bus number. Tested with following commands, read/write/erase works good. flashrom -p lspcon_i2c_spi:bus=7 -r /tmp/foo; flashrom -p lspcon_i2c_spi:bus=7 -E; flashrom -p lspcon_i2c_spi:bus=7 -w /tmp/foo; Change-Id: I039e683252cfaf1ffef8694a3e8081b1b6b944f7 Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> --- M Makefile M flashrom.c A lspcon_i2c_spi.c M meson.build M meson_options.txt M programmer.h 6 files changed, 548 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/87/39687/1 diff --git a/Makefile b/Makefile index aa77a64..298890e 100644 --- a/Makefile +++ b/Makefile @@ -195,6 +195,11 @@ else override CONFIG_STLINKV3_SPI = no endif +ifeq ($(CONFIG_LSPCON_I2C_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_LSPCON_I2C_SPI=yes +else +override CONFIG_LSPCON_I2C_SPI = no +endif # libjaylink is also not available for DOS ifeq ($(CONFIG_JLINK_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_JLINK_SPI=yes @@ -306,6 +311,11 @@ else override CONFIG_SATAMV = no endif +ifeq ($(CONFIG_LSPCON_I2C_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_LSPCON_I2C_SPI=yes +else +override CONFIG_LSPCON_I2C_SPI = no +endif endif ifneq ($(TARGET_OS), MinGW) @@ -381,6 +391,11 @@ else override CONFIG_STLINKV3_SPI = no endif +ifeq ($(CONFIG_LSPCON_I2C_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_LSPCON_I2C_SPI=yes +else +override CONFIG_LSPCON_I2C_SPI = no +endif ifeq ($(CONFIG_CH341A_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_CH341A_SPI=yes else @@ -656,6 +671,9 @@ # Always enable STLink V3 CONFIG_STLINKV3_SPI ?= yes +# Always enable I2C SPI +CONFIG_LSPCON_I2C_SPI ?= yes + # Always enable dummy tracing for now. CONFIG_DUMMY ?= yes @@ -735,6 +753,7 @@ override CONFIG_DEVELOPERBOX_SPI = no override CONFIG_PICKIT2_SPI = no override CONFIG_STLINKV3_SPI = no +override CONFIG_LSPCON_I2C_SPI = no endif ifeq ($(CONFIG_ENABLE_LIBPCI_PROGRAMMERS), no) override CONFIG_INTERNAL = no @@ -913,6 +932,12 @@ NEED_LIBUSB1 += CONFIG_STLINKV3_SPI endif +ifeq ($(CONFIG_LSPCON_I2C_SPI), yes) +FEATURE_CFLAGS += -D'CONFIG_LSPCON_I2C_SPI=1' +PROGRAMMER_OBJS += lspcon_i2c_spi.o +NEED_LIBUSB1 += CONFIG_LSPCON_I2C_SPI +endif + ifneq ($(NEED_LIBFTDI), ) FTDILIBS := $(call debug_shell,[ -n "$(PKG_CONFIG_LIBDIR)" ] && export PKG_CONFIG_LIBDIR="$(PKG_CONFIG_LIBDIR)" ; $(PKG_CONFIG) --libs libftdi1 || $(PKG_CONFIG) --libs libftdi || printf "%s" "-lftdi -lusb") FEATURE_CFLAGS += $(call debug_shell,grep -q "FT232H := yes" .features && printf "%s" "-D'HAVE_FT232H=1'") diff --git a/flashrom.c b/flashrom.c index e541b68..3fc705a 100644 --- a/flashrom.c +++ b/flashrom.c @@ -389,6 +389,18 @@ }, #endif +#if CONFIG_LSPCON_I2C_SPI == 1 + { + .name = "lspcon_i2c_spi", + .type = OTHER, + .devs.note = "Device files /dev/i2c-*.\n", + .init = lspcon_i2c_spi_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_USBBLASTER_SPI == 1 { .name = "usbblaster_spi", diff --git a/lspcon_i2c_spi.c b/lspcon_i2c_spi.c new file mode 100644 index 0000000..d56da92 --- /dev/null +++ b/lspcon_i2c_spi.c @@ -0,0 +1,499 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2020 The Chromium OS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <stdint.h> +#include <stdio.h> +#include <string.h> +#include <time.h> +#include <errno.h> + +#include "programmer.h" +#include "spi.h" +#include "i2c_helper.h" + +#define REGISTER_ADDRESS (0x94 >> 1) +#define PAGE_ADDRESS (0x9e >> 1) +#define PAGE_SIZE 256 +#define READ_SIZE 32 +#define MAX_SPI_WAIT_RETRIES 1000 +#define FUNCTION_ERR -1 + +#define CLT2_SPI 0x82 +#define SPIEDID_BASE_ADDR2 0x8d +#define ROMADDR_BYTE1 0x8e +#define ROMADDR_BYTE2 0x8f +#define SWSPI_WDATA 0x90 + #define SWSPI_WDATA_CLEAR_STATUS 0x00 + #define SWSPI_WDATA_WRITE_REGISTER 0x01 + #define SWSPI_WDATA_READ_REGISTER 0x05 + #define SWSPI_WDATA_ENABLE_REGISTER 0x06 + #define SWSPI_WDATA_SECTOR_ERASE 0x20 + #define SWSPI_WDATA_PROTECT_BP 0x8c +#define SWSPI_RDATA 0x91 +#define SWSPI_LEN 0x92 +#define SWSPICTL 0x93 + #define SWSPICTL_ACCESS_TRIGGER 1 + #define SWSPICTL_CLEAR_PTR (1 << 1) + #define SWSPICTL_NO_READ (1 << 2) + #define SWSPICTL_ENABLE_READBACK (1 << 3) + #define SWSPICTL_MOT (1 << 4) +#define SPISTATUS 0x9e + #define SPISTATUS_BYTE_PROGRAM_FINISHED 0 + #define SPISTATUS_BYTE_PROGRAM_IN_IF 1 + #define SPISTATUS_BYTE_PROGRAM_SEND_DONE (1 << 1) + #define SPISTATUS_SECTOR_ERASE_FINISHED 0 + #define SPISTATUS_SECTOR_ERASE_IN_IF (1 << 2) + #define SPISTATUS_SECTOR_ERASE_SEND_DONE (1 << 3) + #define SPISTATUS_CHIP_ERASE_FINISHED 0 + #define SPISTATUS_CHIP_ERASE_IN_IF (1 << 4) + #define SPISTATUS_CHIP_ERASE_SEND_DONE (1 << 5) + #define SPISTATUS_FW_UPDATE_ENABLE (1 << 6) +#define WRITE_PROTECTION 0xb3 + #define WRITE_PROTECTION_ON 0 + #define WRITE_PROTECTION_OFF 0x10 +#define MPU 0xbc +#define PAGE_HW_WRITE 0xda + #define PAGE_HW_WRITE_DISABLE 0 + #define PAGE_HW_COFIG_REGISTER 0xaa + #define PAGE_HW_WRITE_ENABLE 0x55 + +struct lspcon_i2c_spi_data { + int fd; +}; + +typedef struct { + uint8_t command; + uint8_t data_size; + const uint8_t *data; + uint8_t control; +} packet_t; + +static int lspcon_i2c_spi_write_data(int fd, uint16_t addr, void *buf, uint16_t len) +{ + i2c_buffer_t data; + if (i2c_buffer_t_fill(&data, buf, len)) + return FUNCTION_ERR; + + return i2c_write(fd, addr, &data) == len ? 0 : FUNCTION_ERR; +} + +static int lspcon_i2c_spi_read_data(int fd, uint16_t addr, void *buf, uint16_t len) +{ + i2c_buffer_t data; + if (i2c_buffer_t_fill(&data, buf, len)) + return FUNCTION_ERR; + + return i2c_read(fd, addr, &data) == len ? 0 : FUNCTION_ERR; +} + +static int get_fd_from_context(struct flashctx *flash) +{ + if (!flash || !flash->mst || !flash->mst->spi.data) { + msg_perr("Unable to extract fd from flash context.\n"); + return FUNCTION_ERR; + } + + return ((const struct lspcon_i2c_spi_data *)flash->mst->spi.data)->fd; +} + +static int lspcon_i2c_spi_write_register(int fd, uint8_t i2c_register, uint8_t value) +{ + uint8_t command[] = { i2c_register, value }; + return lspcon_i2c_spi_write_data(fd, REGISTER_ADDRESS, command, 2); +} + +static int lspcon_i2c_spi_read_register(int fd, uint8_t i2c_register, uint8_t *value) +{ + uint8_t command[] = { i2c_register }; + int ret = lspcon_i2c_spi_write_data(fd, REGISTER_ADDRESS, command, 1); + ret |= lspcon_i2c_spi_read_data(fd, REGISTER_ADDRESS, value, 1); + + return ret ? FUNCTION_ERR : 0; +} + +static int lspcon_i2c_spi_register_control(int fd, packet_t *packet) +{ + int i; + int ret = lspcon_i2c_spi_write_register(fd, SWSPI_WDATA, packet->command); + if (ret) + return ret; + + /* Higher 4 bits are read size. */ + int write_size = packet->data_size & 0x0f; + for (i = 0; i < write_size; ++i) { + ret |= lspcon_i2c_spi_write_register(fd, SWSPI_WDATA, packet->data[i]); + } + + ret |= lspcon_i2c_spi_write_register(fd, SWSPI_LEN, packet->data_size); + ret |= lspcon_i2c_spi_write_register(fd, SWSPICTL, packet->control); + + return ret; +} + +static int lspcon_i2c_spi_wait_command_done(int fd, unsigned int offset, int mask) +{ + uint8_t val; + int tried = 0; + int ret = 0; + do { + ret |= lspcon_i2c_spi_read_register(fd, offset, &val); + } while(!ret && (val & mask) && ++tried < MAX_SPI_WAIT_RETRIES); + + if (tried == MAX_SPI_WAIT_RETRIES) { + msg_perr("Error: Time out on sending command.\n"); + return -MAX_SPI_WAIT_RETRIES; + } + + return (val & mask) ? FUNCTION_ERR : ret; +} + +static int lspcon_i2c_spi_wait_rom_free(int fd) +{ + uint8_t val; + int tried = 0; + int ret = 0; + ret |= lspcon_i2c_spi_wait_command_done(fd, SPISTATUS, + SPISTATUS_SECTOR_ERASE_IN_IF | SPISTATUS_SECTOR_ERASE_SEND_DONE); + if (ret) + return ret; + + do { + packet_t packet = { SWSPI_WDATA_READ_REGISTER, 0, NULL, SWSPICTL_ACCESS_TRIGGER }; + ret |= lspcon_i2c_spi_register_control(fd, &packet); + ret |= lspcon_i2c_spi_wait_command_done(fd, SWSPICTL, SWSPICTL_ACCESS_TRIGGER); + ret |= lspcon_i2c_spi_read_register(fd, SWSPI_RDATA, &val); + } while (!ret && (val & SWSPICTL_ACCESS_TRIGGER) && ++tried < MAX_SPI_WAIT_RETRIES); + + if (tried == MAX_SPI_WAIT_RETRIES) { + msg_perr("Error: Time out on waiting ROM free.\n"); + return -MAX_SPI_WAIT_RETRIES; + } + + return (val & SWSPICTL_ACCESS_TRIGGER) ? FUNCTION_ERR : ret; +} + +static int lspcon_i2c_spi_toggle_register_protection(int fd, int toggle) +{ + return lspcon_i2c_spi_write_register(fd, WRITE_PROTECTION, + toggle ? WRITE_PROTECTION_OFF : WRITE_PROTECTION_ON); +} + +static int lspcon_i2c_spi_enable_write_status_register(int fd) +{ + int ret = lspcon_i2c_spi_toggle_register_protection(fd, 1); + packet_t packet = { + SWSPI_WDATA_ENABLE_REGISTER, 0, NULL, SWSPICTL_ACCESS_TRIGGER | SWSPICTL_NO_READ }; + ret |= lspcon_i2c_spi_register_control(fd, &packet); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0); + + return ret; +} + +static int lspcon_i2c_spi_enable_write_status_register_protection(int fd) +{ + int ret = lspcon_i2c_spi_toggle_register_protection(fd, 1); + uint8_t data[] = { SWSPI_WDATA_PROTECT_BP }; + packet_t packet = { + SWSPI_WDATA_WRITE_REGISTER, 1, data, SWSPICTL_ACCESS_TRIGGER | SWSPICTL_NO_READ }; + ret |= lspcon_i2c_spi_register_control(fd, &packet); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0); + + return ret; +} + +static int lspcon_i2c_spi_disable_protection(int fd) +{ + int ret = lspcon_i2c_spi_toggle_register_protection(fd, 1); + uint8_t data[] = { SWSPI_WDATA_CLEAR_STATUS }; + packet_t packet = { + SWSPI_WDATA_WRITE_REGISTER, 1, &data[0], SWSPICTL_ACCESS_TRIGGER | SWSPICTL_NO_READ }; + ret |= lspcon_i2c_spi_register_control(fd, &packet); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0); + + return ret; +} + +static int lspcon_i2c_spi_disable_hw_write(int fd) +{ + return lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, PAGE_HW_WRITE_DISABLE); +} + +static int lspcon_i2c_spi_enable_write_protection(int fd) +{ + int ret = lspcon_i2c_spi_enable_write_status_register(fd); + ret |= lspcon_i2c_spi_enable_write_status_register_protection(fd); + ret |= lspcon_i2c_spi_wait_rom_free(fd); + ret |= lspcon_i2c_spi_disable_hw_write(fd); + + return ret; +} + +static int lspcon_i2c_spi_disable_all_protection(int fd) +{ + int ret = lspcon_i2c_spi_enable_write_status_register(fd); + ret |= lspcon_i2c_spi_disable_protection(fd); + ret |= lspcon_i2c_spi_wait_rom_free(fd); + + return ret; +} + +static int lspcon_i2c_spi_send_command(struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + unsigned int i; + if (writecnt > 16 || readcnt > 16 || writecnt == 0) { + msg_perr("Error: Invalid read/write count for send command.\n"); + return FUNCTION_ERR; + } + + int fd = get_fd_from_context(flash); + if (fd < 0) + return FUNCTION_ERR; + + int ret = lspcon_i2c_spi_disable_all_protection(fd); + ret |= lspcon_i2c_spi_enable_write_status_register(fd); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 1); + + /* First bit of writearr shuld be the command value, followed by the value to write. + Read length occupies 4 bit and represents 16 level, thus if read 1 bit, + read length should be set 0. */ + packet_t packet = { + writearr[0], (writecnt - 1) | ((readcnt - 1) << 4), &writearr[1], + SWSPICTL_ACCESS_TRIGGER | (readcnt ? 0 : SWSPICTL_NO_READ), + }; + + ret |= lspcon_i2c_spi_register_control(fd, &packet); + ret |= lspcon_i2c_spi_wait_command_done(fd, SWSPICTL, SWSPICTL_ACCESS_TRIGGER); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0); + if (ret) + return ret; + + for (i = 0; i < readcnt; ++i) { + ret |= lspcon_i2c_spi_read_register(fd, SWSPI_RDATA, &readarr[i]); + } + + ret |= lspcon_i2c_spi_wait_rom_free(fd); + + return ret; +} + +static int lspcon_i2c_spi_enable_hw_write(int fd) +{ + int ret = 0; + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, PAGE_HW_COFIG_REGISTER); + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, PAGE_HW_WRITE_ENABLE); + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, 0x50); + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, 0x41); + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, 0x52); + ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, 0x44); + + return ret; +} + +static int lspcon_i2c_clt2_spi_reset(int fd) +{ + int ret = 0; + ret |= lspcon_i2c_spi_write_register(fd, CLT2_SPI, 0x20); + struct timespec wait_100_ms = { 0, 100000000 }; + nanosleep(&wait_100_ms, NULL); + ret |= lspcon_i2c_spi_write_register(fd, CLT2_SPI, 0x00); + + return ret; +} + +static int lspcon_i2c_spi_reset_mpu_stop(int fd) +{ + int ret = 0; + ret |= lspcon_i2c_spi_write_register(fd, MPU, 0xc0); // cmd mode + ret |= lspcon_i2c_spi_write_register(fd, MPU, 0x40); // stop mcu + + return ret; +} + +static int lspcon_i2c_spi_map_page(int fd, unsigned int offset) +{ + /* Page number byte, need to / PAGE_SIZE. */ + uint8_t command_byte1[] = { ROMADDR_BYTE1, (offset >> 8) & 0xff }; + uint8_t command_byte2[] = { ROMADDR_BYTE2, (offset >> 16) }; + int ret = 0; + ret |= lspcon_i2c_spi_write_data(fd, REGISTER_ADDRESS, command_byte1, 2); + ret |= lspcon_i2c_spi_write_data(fd, REGISTER_ADDRESS, command_byte2, 2); + + return ret ? FUNCTION_ERR : 0; +} + +static int lspcon_i2c_spi_read(struct flashctx *flash, uint8_t *buf, + unsigned int start, unsigned int len) +{ + unsigned int i; + int ret = 0; + if (start & 0xff) + return default_spi_read(flash, buf, start, len); + + int fd = get_fd_from_context(flash); + if (fd < 0) + return FUNCTION_ERR; + + for (i = 0; i < len; i += PAGE_SIZE) { + ret |= lspcon_i2c_spi_map_page(fd, start + i); + ret |= lspcon_i2c_spi_read_data(fd, PAGE_ADDRESS, buf + i, min(len - i, PAGE_SIZE)); + } + + return ret; +} + +static int lspcon_i2c_spi_write_page(int fd, const uint8_t *buf, unsigned int len) +{ + uint8_t write_buffer[len + 1]; + write_buffer[0] = 0; + memcpy(write_buffer + 1, buf, len); + + return lspcon_i2c_spi_write_data(fd, PAGE_ADDRESS, write_buffer, len + 1); +} + +static int lspcon_i2c_spi_write_256(struct flashctx *flash, const uint8_t *buf, + unsigned int start, unsigned int len) +{ + int ret = 0; + if (start & 0xff) + return default_spi_write_256(flash, buf, start, len); + + int fd = get_fd_from_context(flash); + if (fd < 0) + return FUNCTION_ERR; + + ret |= lspcon_i2c_spi_disable_all_protection(fd); + /* Enable hardware write and reset clt2SPI interface. */ + ret |= lspcon_i2c_spi_enable_hw_write(fd); + ret |= lspcon_i2c_clt2_spi_reset(fd); + + for (unsigned int i = 0; i < len; i += PAGE_SIZE) { + ret |= lspcon_i2c_spi_map_page(fd, start + i); + ret |= lspcon_i2c_spi_write_page(fd, buf + i, min(len - i, PAGE_SIZE)); + } + + ret |= lspcon_i2c_spi_enable_write_protection(fd); + ret |= lspcon_i2c_spi_disable_hw_write(fd); + + return ret; +} + +static int lspcon_i2c_spi_write_aai(struct flashctx *flash, const uint8_t *buf, + unsigned int start, unsigned int len) +{ + msg_perr("Error: AAI write function is not supported.\n"); + return FUNCTION_ERR; +} + +static const struct spi_master spi_master_i2c_lspcon = { + .max_data_read = 256, + .max_data_write = 256, + .command = lspcon_i2c_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = lspcon_i2c_spi_read, + .write_256 = lspcon_i2c_spi_write_256, + .write_aai = lspcon_i2c_spi_write_aai, +}; + +/* TODO: MPU still stop at this point, probably need to reset it. */ +static int lspcon_i2c_spi_shutdown(void *data) +{ + int ret = 0; + int fd = ((struct lspcon_i2c_spi_data *)data)->fd; + ret |= lspcon_i2c_spi_enable_write_protection(fd); + ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0); + i2c_close(fd); + free(data); + + return ret; +} + +/* TODO: remove this out of the specific spi master implementation. */ +static int get_bus() +{ + char *bus_str = extract_programmer_param("bus"); + int ret = FUNCTION_ERR; + if (bus_str) { + char *bus_suffix; + errno = 0; + int bus = (int)strtol(bus_str, &bus_suffix, 10); + if (errno != 0 || bus_str == bus_suffix) { + msg_perr("Error: Could not convert 'bus'.\n"); + goto get_bus_done; + } + + if (bus < 0 || bus > 255) { + msg_perr("Error: Value for 'bus' is out of range(0-255).\n"); + goto get_bus_done; + } + + if (strlen(bus_suffix) > 0) { + msg_perr("Error: Garbage following 'bus' value.\n"); + goto get_bus_done; + } + + msg_pinfo("Using i2c bus %i.\n", bus); + ret = bus; + goto get_bus_done; + } else { + msg_perr("Error: Bus number not specified.\n"); + } +get_bus_done: + if (bus_str) + free(bus_str); + + return ret; +} + +static int register_lspcon_i2c_spi_master(void *ptr) +{ + struct spi_master mst = spi_master_i2c_lspcon; + mst.data = ptr; + + return register_spi_master(&mst); +} + +int lspcon_i2c_spi_init(void) +{ + int lspcon_i2c_spi_bus = get_bus(); + if (lspcon_i2c_spi_bus < 0) + return FUNCTION_ERR; + + int ret = 0; + int fd = i2c_open(lspcon_i2c_spi_bus, REGISTER_ADDRESS, 0); + if (fd < 0) + return fd; + + ret |= lspcon_i2c_spi_reset_mpu_stop(fd); + if (ret) + return ret; + + struct lspcon_i2c_spi_data data = { fd }; + void *data_ptr = calloc(1, sizeof(data)); + if (!data_ptr) { + msg_perr("Unable to allocate space for extra spi master data.\n"); + return FUNCTION_ERR; + } + + memcpy(data_ptr, &data, sizeof(data)); + ret |= register_shutdown(lspcon_i2c_spi_shutdown, data_ptr); + ret |= register_lspcon_i2c_spi_master(data_ptr); + + return ret; +} diff --git a/meson.build b/meson.build index b586d9a..7494c51 100644 --- a/meson.build +++ b/meson.build @@ -63,6 +63,7 @@ config_serprog = get_option('config_serprog') config_usbblaster_spi = get_option('config_usbblaster_spi') config_stlinkv3_spi = get_option('config_stlinkv3_spi') +config_lspcon_i2c_spi = get_option('config_lspcon_i2c_spi') config_linux_i2c_helper = get_option('config_linux_i2c_helper') cargs = [] @@ -284,6 +285,10 @@ srcs += 'stlinkv3_spi.c' cargs += '-DCONFIG_STLINKV3_SPI=1' endif +if config_lspcon_i2c_spi + srcs += 'lspcon_i2c_spi.c' + cargs += '-DCONFIG_LSPCON_I2C_SPI=1' +endif # bitbanging SPI infrastructure if config_bitbang_spi diff --git a/meson_options.txt b/meson_options.txt index ff4a786..e4b4fa9 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -35,4 +35,5 @@ option('config_serprog', type : 'boolean', value : true, description : 'serprog') option('config_usbblaster_spi', type : 'boolean', value : true, description : 'Altera USB-Blaster dongles') option('config_stlinkv3_spi', type : 'boolean', value : true, description : 'STMicroelectronics STLINK-V3') +option('config_lspcon_i2c_spi', type : 'boolean', value : true, description : 'SPI control from I2C bus') option('config_linux_i2c_helper', type: 'boolean', value : true, description : 'Linux I2C control') diff --git a/programmer.h b/programmer.h index 08500c6..d47caf3 100644 --- a/programmer.h +++ b/programmer.h @@ -130,6 +130,9 @@ #if CONFIG_STLINKV3_SPI == 1 PROGRAMMER_STLINKV3_SPI, #endif +#if CONFIG_LSPCON_I2C_SPI == 1 + PROGRAMMER_LSPCON_I2C_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -810,4 +813,7 @@ struct libusb_device_handle *usb_dev_get_by_vid_pid_number( struct libusb_context *usb_ctx, uint16_t vid, uint16_t pid, unsigned int num); +/* lspcon_i2c_spi.c */ +int lspcon_i2c_spi_init(void); + #endif /* !__PROGRAMMER_H__ */ -- To view, visit https://review.coreboot.org/c/flashrom/+/39687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I039e683252cfaf1ffef8694a3e8081b1b6b944f7 Gerrit-Change-Number: 39687 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

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flashrom-gerrit March 2020