September 2018 - flashrom-gerrit

Change in flashrom[master]: Remove unneeded whitespace
by Richard Spiegel (Code Review) 21 Sep '18

21 Sep '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28707 ) Change subject: Remove unneeded whitespace ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28707/1/board_enable.c File board_enable.c: https://review.coreboot.org/#/c/28707/1/board_enable.c@159 PS1, Line 159: the GPIO port */ > e.g. […] There's actually only 4 spaces after a tab... it's just how it looks that makes you think there are enough spaces after the tab... -- To view, visit https://review.coreboot.org/28707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0e72e3e3736a39685b7f166c5e6b06cc241b26be Gerrit-Change-Number: 28707 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Sep 2018 16:02:50 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in flashrom[master]: Remove unneeded whitespace
by Nico Huber (Code Review) 21 Sep '18

21 Sep '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/28707 ) Change subject: Remove unneeded whitespace ...................................................................... Patch Set 1: (1 comment) Many of the touched lines are after unnecessary line breaks. Flashrom has a 112 char line limit. If we touch lines for whitespace we should fix that too. https://review.coreboot.org/#/c/28707/1/board_enable.c File board_enable.c: https://review.coreboot.org/#/c/28707/1/board_enable.c@159 PS1, Line 159: the GPIO port */ e.g. here -- To view, visit https://review.coreboot.org/28707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0e72e3e3736a39685b7f166c5e6b06cc241b26be Gerrit-Change-Number: 28707 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Sep 2018 15:09:22 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in flashrom[master]: Remove unneeded whitespace
by Richard Spiegel (Code Review) 21 Sep '18

21 Sep '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28707 ) Change subject: Remove unneeded whitespace ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0e72e3e3736a39685b7f166c5e6b06cc241b26be Gerrit-Change-Number: 28707 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Sep 2018 14:38:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in flashrom[master]: Remove unneeded whitespace
by Elyes HAOUAS (Code Review) 21 Sep '18

21 Sep '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28707 Change subject: Remove unneeded whitespace ...................................................................... Remove unneeded whitespace Change-Id: I0e72e3e3736a39685b7f166c5e6b06cc241b26be Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M board_enable.c M cbtable.c M chipset_enable.c M drkaiser.c M flashchips.c M flashchips.h M flashrom.c M hwaccess.h M pickit2_spi.c 9 files changed, 186 insertions(+), 186 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/07/28707/1 diff --git a/board_enable.c b/board_enable.c index 9d45813..d1c9da5 100644 --- a/board_enable.c +++ b/board_enable.c @@ -156,7 +156,7 @@ const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */ uint8_t ldn; /* LDN this GPIO register is located in */ uint8_t enable_bit; /* bit in 0x30 of that LDN to enable - the GPIO port */ + the GPIO port */ uint8_t base; /* base register in that LDN for the port */ }; @@ -391,7 +391,7 @@ * soon as we have generic Super I/O detection code. */ static int winbond_gpio_set(uint16_t base, enum winbond_id chipid, - int pin, int raise) + int pin, int raise) { const struct winbond_chip *chip = NULL; const struct winbond_port *gpio; @@ -405,12 +405,12 @@ } if (chip->device_id != chipid) { msg_perr("\nERROR: Found Winbond chip with ID 0x%x, " - "expected %x\n", chip->device_id, chipid); + "expected %x\n", chip->device_id, chipid); return -1; } if (bit >= 8 || port == 0 || port > chip->gpio_port_count) { msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n", - pin); + pin); return -1; } @@ -418,7 +418,7 @@ if (gpio->ldn == 0) { msg_perr("\nERROR: GPIO%d is not supported yet on this" - " winbond chip\n", port); + " winbond chip\n", port); return -1; } @@ -433,7 +433,7 @@ /* Select GPIO function of that pin. */ if (gpio->mux && gpio->mux[bit].reg) sio_mask(base, gpio->mux[bit].reg, - gpio->mux[bit].data, gpio->mux[bit].mask); + gpio->mux[bit].data, gpio->mux[bit].mask); sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */ sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */ @@ -1036,7 +1036,7 @@ LPC bridge, but have the same SMBus bridge IDs */ if (dev->func != 0) { msg_perr("MCP LPC bridge at unexpected function" - " number %d\n", dev->func); + " number %d\n", dev->func); return -1; } @@ -1056,7 +1056,7 @@ devclass = pci_read_word(dev, PCI_CLASS_DEVICE); if (devclass != 0x0C05) { msg_perr("Unexpected device class %04x for SMBus" - " controller\n", devclass); + " controller\n", devclass); return -1; } break; @@ -1125,12 +1125,12 @@ * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55 * * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that - * board. We can't tell the SMBus logical devices apart, but we - * can tell the LPC bridge functions apart. - * We need to choose the SMBus bridge next to the LPC bridge with - * ID 0x364 and the "LPC bridge" class. - * b) #TBL is hardwired on that board to a pull-down. It can be - * overridden by connecting the two solder points next to F2. + * board. We can't tell the SMBus logical devices apart, but we + * can tell the LPC bridge functions apart. + * We need to choose the SMBus bridge next to the LPC bridge with + * ID 0x364 and the "LPC bridge" class. + * b) #TBL is hardwired on that board to a pull-down. It can be + * overridden by connecting the two solder points next to F2. */ static int nvidia_mcp_gpio5_raise(void) { @@ -1329,35 +1329,35 @@ static const struct {unsigned int reg, mask, value; } piix4_gpo[] = { {0}, - {0xB0, 0x0001, 0x0000}, /* GPO1... */ + {0xB0, 0x0001, 0x0000}, /* GPO1... */ {0xB0, 0x0001, 0x0000}, {0xB0, 0x0001, 0x0000}, {0xB0, 0x0001, 0x0000}, {0xB0, 0x0001, 0x0000}, {0xB0, 0x0001, 0x0000}, - {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */ + {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */ {0}, - {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */ - {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */ - {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */ - {0x4E, 0x0100, 0x0000}, /* GPO12... */ + {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */ + {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */ + {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */ + {0x4E, 0x0100, 0x0000}, /* GPO12... */ {0x4E, 0x0100, 0x0000}, - {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */ - {0xB2, 0x0002, 0x0002}, /* GPO15... */ - {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */ - {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */ - {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */ - {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */ - {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */ - {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */ - {0xB2, 0x1000, 0x1000}, /* GPO22... */ - {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */ - {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */ - {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */ - {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */ + {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */ + {0xB2, 0x0002, 0x0002}, /* GPO15... */ + {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */ + {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */ + {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */ + {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */ + {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */ + {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */ + {0xB2, 0x1000, 0x1000}, /* GPO22... */ + {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */ + {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */ + {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */ + {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */ {0}, {0}, - {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */ + {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */ {0} }; @@ -1994,7 +1994,7 @@ * Returns the base port of the runtime register block, or 0 on error. */ static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id, - uint8_t logical_device) + uint8_t logical_device) { uint16_t rt_port = 0; @@ -2009,7 +2009,7 @@ sio_write(sio_port, 0x07, logical_device); if (sio_read(sio_port, 0x30) & 1) { rt_port = (sio_read(sio_port, 0x60) << 8) - | sio_read(sio_port, 0x61); + | sio_read(sio_port, 0x61); } if (rt_port == 0) { @@ -2043,12 +2043,12 @@ /* Configure the GPIO pin. */ val = INB(rt_port + 0x33); /* GP30 config */ - val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */ + val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */ OUTB(val, rt_port + 0x33); /* Disable write protection. */ val = INB(rt_port + 0x4d); /* GP3 values */ - val |= 0x01; /* Set GP30 high. */ + val |= 0x01; /* Set GP30 high. */ OUTB(val, rt_port + 0x4d); return 0; @@ -2262,7 +2262,7 @@ * flashrom before their ROM chip can be accessed/written to. * * NOTE: Please add boards that _don't_ need such enables or don't work yet - * to the respective tables in print.c. Thanks! + * to the respective tables in print.c. Thanks! * * We use 2 sets of PCI IDs here, you're free to choose which is which. This * is to provide a very high degree of certainty when matching a board on diff --git a/cbtable.c b/cbtable.c index fe0c368..827bebe 100644 --- a/cbtable.c +++ b/cbtable.c @@ -203,10 +203,10 @@ rec = (struct lb_mainboard *)ptr; max_size = rec->size - sizeof(*rec); msg_pdbg("Vendor ID: %.*s, part ID: %.*s\n", - max_size - rec->vendor_idx, - rec->strings + rec->vendor_idx, - max_size - rec->part_number_idx, - rec->strings + rec->part_number_idx); + max_size - rec->vendor_idx, + rec->strings + rec->vendor_idx, + max_size - rec->part_number_idx, + rec->strings + rec->part_number_idx); snprintf(vendor, 255, "%.*s", max_size - rec->vendor_idx, rec->strings + rec->vendor_idx); snprintf(part, 255, "%.*s", max_size - rec->part_number_idx, rec->strings + rec->part_number_idx); diff --git a/chipset_enable.c b/chipset_enable.c index 566b1fb..fea4017 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -228,14 +228,14 @@ old = pci_read_word(dev, xbcs); /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to - * FFF00000-FFF7FFFF are forwarded to ISA). - * Note: This bit is reserved on PIIX/PIIX3/MPIIX. + * FFF00000-FFF7FFFF are forwarded to ISA). + * Note: This bit is reserved on PIIX/PIIX3/MPIIX. * Set bit 7: Extended BIOS Enable (PCI master accesses to - * FFF80000-FFFDFFFF are forwarded to ISA). + * FFF80000-FFFDFFFF are forwarded to ISA). * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to - * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top - * of 1 Mbyte, or the aliases at the top of 4 Gbyte - * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#. + * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top + * of 1 Mbyte, or the aliases at the top of 4 Gbyte + * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#. * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA. * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable). */ diff --git a/drkaiser.c b/drkaiser.c index ac49df3..2fe294c 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -24,7 +24,7 @@ #define PCI_MAGIC_DRKAISER_ADDR 0x50 #define PCI_MAGIC_DRKAISER_VALUE 0xa971 -#define DRKAISER_MEMMAP_SIZE (1024 * 128) +#define DRKAISER_MEMMAP_SIZE (1024 * 128) /* Mask to restrict flash accesses to the 128kB memory window. */ #define DRKAISER_MEMMAP_MASK ((1 << 17) - 1) diff --git a/flashchips.c b/flashchips.c index 2001d8c..b2d9611 100644 --- a/flashchips.c +++ b/flashchips.c @@ -15859,18 +15859,18 @@ }, { - .vendor = "Winbond", - .name = "W25P80", - .bustype = BUS_SPI, - .manufacture_id = WINBOND_NEX_ID, - .model_id = WINBOND_NEX_W25P80, - .total_size = 1024, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = + .vendor = "Winbond", + .name = "W25P80", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25P80, + .total_size = 1024, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { { .eraseblocks = { {64 * 1024, 16} }, @@ -15880,26 +15880,26 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B) supported */ - .voltage = {2700, 3600}, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, }, { - .vendor = "Winbond", - .name = "W25P16", - .bustype = BUS_SPI, - .manufacture_id = WINBOND_NEX_ID, - .model_id = WINBOND_NEX_W25P16, - .total_size = 2048, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = + .vendor = "Winbond", + .name = "W25P16", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25P16, + .total_size = 2048, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { { .eraseblocks = { {64 * 1024, 32} }, @@ -15909,26 +15909,26 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B) supported */ - .voltage = {2700, 3600}, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, }, { - .vendor = "Winbond", - .name = "W25P32", - .bustype = BUS_SPI, - .manufacture_id = WINBOND_NEX_ID, - .model_id = WINBOND_NEX_W25P32, - .total_size = 4096, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = + .vendor = "Winbond", + .name = "W25P32", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25P32, + .total_size = 4096, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { { .eraseblocks = { {64 * 1024, 64} }, @@ -15938,11 +15938,11 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B) supported */ - .voltage = {2700, 3600}, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, }, { .vendor = "Winbond", @@ -16760,18 +16760,18 @@ }, { - .vendor = "Zetta Device", - .name = "ZD25D20", - .bustype = BUS_SPI, - .manufacture_id = ZETTADEVICE_ID, - .model_id = ZETTADEVICE_ZD25D20, - .total_size = 256, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = + .vendor = "Zetta Device", + .name = "ZD25D20", + .bustype = BUS_SPI, + .manufacture_id = ZETTADEVICE_ID, + .model_id = ZETTADEVICE_ZD25D20, + .total_size = 256, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { { .eraseblocks = { {4 * 1024, 64} }, @@ -16790,26 +16790,26 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, }, { - .vendor = "Zetta Device", - .name = "ZD25D40", - .bustype = BUS_SPI, - .manufacture_id = ZETTADEVICE_ID, - .model_id = ZETTADEVICE_ZD25D40, - .total_size = 512, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = + .vendor = "Zetta Device", + .name = "ZD25D40", + .bustype = BUS_SPI, + .manufacture_id = ZETTADEVICE_ID, + .model_id = ZETTADEVICE_ZD25D40, + .total_size = 512, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { { .eraseblocks = { {4 * 1024, 128} }, @@ -16828,11 +16828,11 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, }, { diff --git a/flashchips.h b/flashchips.h index ecd8d7a..aff6915 100644 --- a/flashchips.h +++ b/flashchips.h @@ -964,8 +964,8 @@ #define WINBOND_W49V002A 0xB0 #define WINBOND_W49V002FA 0x32 -#define ZETTADEVICE_ID 0xBA /* Zetta Device */ -#define ZETTADEVICE_ZD25D20 0x2012 -#define ZETTADEVICE_ZD25D40 0x2013 +#define ZETTADEVICE_ID 0xBA /* Zetta Device */ +#define ZETTADEVICE_ZD25D20 0x2012 +#define ZETTADEVICE_ZD25D40 0x2013 #endif /* !FLASHCHIPS_H */ diff --git a/flashrom.c b/flashrom.c index 094630c..921e556 100644 --- a/flashrom.c +++ b/flashrom.c @@ -792,7 +792,7 @@ /* Helper function for need_erase() that focuses on granularities of gran bytes. */ static int need_erase_gran_bytes(const uint8_t *have, const uint8_t *want, unsigned int len, - unsigned int gran, const uint8_t erased_value) + unsigned int gran, const uint8_t erased_value) { unsigned int i, j, limit; for (j = 0; j < len / gran; j++) { @@ -816,14 +816,14 @@ * Warning: This function assumes that @have and @want point to naturally * aligned regions. * - * @have buffer with current content - * @want buffer with desired content + * @have buffer with current content + * @want buffer with desired content * @len length of the checked area * @gran write granularity (enum, not count) * @return 0 if no erase is needed, 1 otherwise */ int need_erase(const uint8_t *have, const uint8_t *want, unsigned int len, - enum write_granularity gran, const uint8_t erased_value) + enum write_granularity gran, const uint8_t erased_value) { int result = 0; unsigned int i; @@ -2323,8 +2323,8 @@ * @param buffer Target buffer to write image to. * @param buffer_len Size of target buffer in bytes. * @return 0 on success, - * 2 if buffer_len is too short for the flash chip's contents, - * or 1 on any other failure. + * 2 if buffer_len is too short for the flash chip's contents, + * or 1 on any other failure. */ int flashrom_image_read(struct flashctx *const flashctx, void *const buffer, const size_t buffer_len) { @@ -2380,13 +2380,13 @@ * @param buffer_len Size of source buffer in bytes. * @param refbuffer If given, assume flash chip contains same data as `refbuffer`. * @return 0 on success, - * 4 if buffer_len doesn't match the size of the flash chip, - * 3 if write was tried but nothing has changed, - * 2 if write failed and flash contents changed, - * or 1 on any other failure. + * 4 if buffer_len doesn't match the size of the flash chip, + * 3 if write was tried but nothing has changed, + * 2 if write failed and flash contents changed, + * or 1 on any other failure. */ int flashrom_image_write(struct flashctx *const flashctx, void *const buffer, const size_t buffer_len, - const void *const refbuffer) + const void *const refbuffer) { const size_t flash_size = flashctx->chip->total_size * 1024; const bool verify_all = flashctx->flags.verify_whole_chip; @@ -2521,9 +2521,9 @@ * @param buffer Source buffer to verify with. * @param buffer_len Size of source buffer in bytes. * @return 0 on success, - * 3 if the chip's contents don't match, - * 2 if buffer_len doesn't match the size of the flash chip, - * or 1 on any other failure. + * 3 if the chip's contents don't match, + * 2 if buffer_len doesn't match the size of the flash chip, + * or 1 on any other failure. */ int flashrom_image_verify(struct flashctx *const flashctx, const void *const buffer, const size_t buffer_len) { diff --git a/hwaccess.h b/hwaccess.h index af7054b..fb468b7 100644 --- a/hwaccess.h +++ b/hwaccess.h @@ -199,15 +199,15 @@ #include <machine/sysarch.h> #if defined(__NetBSD__) #if defined(__i386__) - #define iopl i386_iopl + #define iopl i386_iopl #elif defined(__x86_64__) - #define iopl x86_64_iopl + #define iopl x86_64_iopl #endif #elif defined (__OpenBSD__) #if defined(__i386__) - #define iopl i386_iopl + #define iopl i386_iopl #elif defined(__amd64__) - #define iopl amd64_iopl + #define iopl amd64_iopl #endif #endif diff --git a/pickit2_spi.c b/pickit2_spi.c index a7c90a5..97741c8 100644 --- a/pickit2_spi.c +++ b/pickit2_spi.c @@ -60,39 +60,39 @@ static usb_dev_handle *pickit2_handle; /* Default USB transaction timeout in ms */ -#define DFLT_TIMEOUT 10000 +#define DFLT_TIMEOUT 10000 -#define CMD_LENGTH 64 -#define ENDPOINT_OUT 0x01 -#define ENDPOINT_IN 0x81 +#define CMD_LENGTH 64 +#define ENDPOINT_OUT 0x01 +#define ENDPOINT_IN 0x81 -#define CMD_GET_VERSION 0x76 -#define CMD_SET_VDD 0xA0 -#define CMD_SET_VPP 0xA1 -#define CMD_READ_VDD_VPP 0xA3 -#define CMD_EXEC_SCRIPT 0xA6 -#define CMD_CLR_DLOAD_BUFF 0xA7 -#define CMD_DOWNLOAD_DATA 0xA8 -#define CMD_CLR_ULOAD_BUFF 0xA9 -#define CMD_UPLOAD_DATA 0xAA -#define CMD_END_OF_BUFFER 0xAD +#define CMD_GET_VERSION 0x76 +#define CMD_SET_VDD 0xA0 +#define CMD_SET_VPP 0xA1 +#define CMD_READ_VDD_VPP 0xA3 +#define CMD_EXEC_SCRIPT 0xA6 +#define CMD_CLR_DLOAD_BUFF 0xA7 +#define CMD_DOWNLOAD_DATA 0xA8 +#define CMD_CLR_ULOAD_BUFF 0xA9 +#define CMD_UPLOAD_DATA 0xAA +#define CMD_END_OF_BUFFER 0xAD -#define SCR_SPI_READ_BUF 0xC5 -#define SCR_SPI_WRITE_BUF 0xC6 -#define SCR_SET_AUX 0xCF -#define SCR_LOOP 0xE9 -#define SCR_SET_ICSP_CLK_PERIOD 0xEA -#define SCR_SET_PINS 0xF3 -#define SCR_BUSY_LED_OFF 0xF4 -#define SCR_BUSY_LED_ON 0xF5 -#define SCR_MCLR_GND_OFF 0xF6 -#define SCR_MCLR_GND_ON 0xF7 -#define SCR_VPP_PWM_OFF 0xF8 -#define SCR_VPP_PWM_ON 0xF9 -#define SCR_VPP_OFF 0xFA -#define SCR_VPP_ON 0xFB -#define SCR_VDD_OFF 0xFE -#define SCR_VDD_ON 0xFF +#define SCR_SPI_READ_BUF 0xC5 +#define SCR_SPI_WRITE_BUF 0xC6 +#define SCR_SET_AUX 0xCF +#define SCR_LOOP 0xE9 +#define SCR_SET_ICSP_CLK_PERIOD 0xEA +#define SCR_SET_PINS 0xF3 +#define SCR_BUSY_LED_OFF 0xF4 +#define SCR_BUSY_LED_ON 0xF5 +#define SCR_MCLR_GND_OFF 0xF6 +#define SCR_MCLR_GND_ON 0xF7 +#define SCR_VPP_PWM_OFF 0xF8 +#define SCR_VPP_PWM_ON 0xF9 +#define SCR_VPP_OFF 0xFA +#define SCR_VPP_ON 0xFB +#define SCR_VDD_OFF 0xFE +#define SCR_VDD_ON 0xFF /* Might be useful for other USB devices as well. static for now. * device parameter allows user to specify one device of multiple installed */ -- To view, visit https://review.coreboot.org/28707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0e72e3e3736a39685b7f166c5e6b06cc241b26be Gerrit-Change-Number: 28707 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in flashrom[master]: Add CLI option to include a numeric range
by David Hendricks (Code Review) 19 Sep '18

19 Sep '18

David Hendricks has posted comments on this change. ( https://review.coreboot.org/28685 ) Change subject: Add CLI option to include a numeric range ...................................................................... Patch Set 1: Code-Review-1 Implementing a feature request from a user at OSFC. Adding -1 since at the very least it needs a man page entry, but hopefully the rest looks decent. Suggestions for a better option name and/or single-character option are welcome. -- To view, visit https://review.coreboot.org/28685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie2691051984bdeac128354c09bbe72aa05ef7401 Gerrit-Change-Number: 28685 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 19 Sep 2018 15:38:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in flashrom[master]: Add CLI option to include a numeric range
by David Hendricks (Code Review) 19 Sep '18

19 Sep '18

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/28685 Change subject: Add CLI option to include a numeric range ...................................................................... Add CLI option to include a numeric range This adds an option, --range, which allows the user to specify a numeric range directly on the command-line. Change-Id: Ie2691051984bdeac128354c09bbe72aa05ef7401 Signed-off-by: David Hendricks <dhendricks(a)fb.com> --- M cli_classic.c M flash.h M layout.c 3 files changed, 49 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/85/28685/1 diff --git a/cli_classic.c b/cli_classic.c index 119c6f8..b98be48 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -55,6 +55,7 @@ " -l | --layout <layoutfile> read ROM layout from <layoutfile>\n" " --ifd read layout from an Intel Firmware Descriptor\n" " -i | --image <name> only flash image <name> from flash layout\n" + " --range <start:end> include numeric range\n" " -o | --output <logfile> log output to <logfile>\n" " --flash-contents <ref-file> assume flash contents to be <ref-file>\n" " -L | --list-supported print supported devices\n" @@ -97,7 +98,7 @@ struct flashctx *fill_flash; const char *name; int namelen, opt, i, j; - int startchip = -1, chipcount = 0, option_index = 0, force = 0, ifd = 0; + int startchip = -1, chipcount = 0, option_index = 0, force = 0, ifd = 0, include_range = 0; #if CONFIG_PRINT_WIKI == 1 int list_supported_wiki = 0; #endif @@ -108,6 +109,7 @@ enum { OPTION_IFD = 0x0100, OPTION_FLASH_CONTENTS, + OPTION_INCLUDE_RANGE, }; int ret = 0; @@ -125,6 +127,7 @@ {"layout", 1, NULL, 'l'}, {"ifd", 0, NULL, OPTION_IFD}, {"image", 1, NULL, 'i'}, + {"range", 1, NULL, OPTION_INCLUDE_RANGE}, {"flash-contents", 1, NULL, OPTION_FLASH_CONTENTS}, {"list-supported", 0, NULL, 'L'}, {"list-supported-wiki", 0, NULL, 'z'}, @@ -239,6 +242,14 @@ } ifd = 1; break; + case OPTION_INCLUDE_RANGE: + tempstr = strdup(optarg); + if (include_numeric_range(get_global_layout(), tempstr)) { + free(tempstr); + cli_classic_abort_usage(); + } + include_range = 1; + break; case 'i': tempstr = strdup(optarg); if (register_include_arg(tempstr)) { @@ -552,7 +563,7 @@ goto out_shutdown; } - if (layoutfile) { + if (layoutfile || include_range) { layout = get_global_layout(); } else if (ifd && (flashrom_layout_read_from_ifd(&layout, fill_flash, NULL, 0) || process_include_args(layout))) { diff --git a/flash.h b/flash.h index 01ff5cd..735cd21 100644 --- a/flash.h +++ b/flash.h @@ -388,6 +388,7 @@ /* layout.c */ int register_include_arg(char *name); int read_romlayout(const char *name); +int include_numeric_range(struct flashrom_layout *const l, const char *str); int normalize_romentries(const struct flashctx *flash); void layout_cleanup(void); diff --git a/layout.c b/layout.c index fa66238..49dcba0 100644 --- a/layout.c +++ b/layout.c @@ -101,6 +101,41 @@ } #endif +int include_numeric_range(struct flashrom_layout *const l, const char *str) +{ + char *tstr1, *tstr2; + char *orig = strdup(str); + int ret = 1; + + if (num_include_args >= MAX_ROMLAYOUT) { + msg_gerr("Maximum number of ROM images (%i) in layout " + "file reached.\n", MAX_ROMLAYOUT); + goto free_ret; + } + + tstr1 = strtok((char *)str, ":"); + tstr2 = strtok(NULL, ":"); + if (!tstr1 || !tstr2) { + msg_gerr("Error parsing included range argument: \"%s\"\n", str); + goto free_ret; + } + + l->entries[l->num_entries].start = strtol(tstr1, (char **)NULL, 16); + l->entries[l->num_entries].end = strtol(tstr2, (char **)NULL, 16); + l->entries[l->num_entries].included = 1; + + memset(l->entries[l->num_entries].name, 0, sizeof(l->entries[l->num_entries].name)); + strncpy(l->entries[l->num_entries].name, orig, sizeof(l->entries[l->num_entries].name)); + msg_gdbg("romlayout %08x - %08x named %s\n", l->entries[l->num_entries].start, + l->entries[l->num_entries].end, l->entries[l->num_entries].name); + + l->num_entries++; + ret = 0; +free_ret: + free(orig); + return ret; +} + /* returns the index of the entry (or a negative value if it is not found) */ static int find_include_arg(const char *const name) { -- To view, visit https://review.coreboot.org/28685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie2691051984bdeac128354c09bbe72aa05ef7401 Gerrit-Change-Number: 28685 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com>

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Change in flashrom[master]: Add support to get layout from fmap (e.g. coreboot rom)
by David Hendricks (Code Review) 17 Sep '18

17 Sep '18

David Hendricks has posted comments on this change. ( https://review.coreboot.org/23203 ) Change subject: Add support to get layout from fmap (e.g. coreboot rom) ...................................................................... Patch Set 24: (17 comments) I had some time to hack on this some more and test using a Chromebook using --fmap-file (linear search), --fmap with the fmap offset at a weird location (try bsearch and fall back to linear search), and --fmap with the fmap at a bsearchable offset. I'm not sure what to do about the man page... The line break seems weird. https://review.coreboot.org/#/c/23203/22/cli_classic.c File cli_classic.c: https://review.coreboot.org/#/c/23203/22/cli_classic.c@619 PS22, Line 619: out > out_shutdown Done https://review.coreboot.org/#/c/23203/22/cli_classic.c@642 PS22, Line 642: && (flashrom_ > I stared at this for a moment, now I'm sure the `!fmapfile` is […] OK. I think it helps with readability since it flows nicely with the above `fmap && fmapfile`, but I don't have a strong preference. https://review.coreboot.org/#/c/23203/22/flashrom.8.tmpl File flashrom.8.tmpl: https://review.coreboot.org/#/c/23203/22/flashrom.8.tmpl@52 PS22, Line 52: \-\-fmap\fR|\fB\-\-fmap-file\fR <file>) \ > This line is unnecessarily long now. Please break before the […] Yeah, it's not the longest line but it is quite long. I don't understand why you want to break before the `-n` though. The spacing doesn't make much sense to me, is there a standard or some general guidelines? I just took a guess. https://review.coreboot.org/#/c/23203/22/flashrom.8.tmpl@202 PS22, Line 202: hrom suppo > par*ti*tioning Done https://review.coreboot.org/#/c/23203/22/flashrom.8.tmpl@217 PS22, Line 217: hrom suppo > partitioning Done https://review.coreboot.org/#/c/23203/22/flashrom.8.tmpl@219 PS22, Line 219: used to generate the layout. > leftover oops, done. https://review.coreboot.org/#/c/23203/22/fmap.h File fmap.h: https://review.coreboot.org/#/c/23203/22/fmap.h@3 PS22, Line 3: -present > I know it has been discussed already. But this is incredibly […] Nah, I kinda like it actually. It just says explicitly what we already assume, and prevents issues with people updating copyright notices needlessly to match the present year whenever they touch a file. In any case our non-lawyer opinions are irrelevant, so no point in arguing. https://review.coreboot.org/#/c/23203/22/fmap.h@45 PS22, Line 45: #define FMAP_VER_MINOR 1 /* this header's FMAP minor version */ > Didn't check earlier versions, but now this is unused? shouldn't […] Sure. FWIW, the only difference IIRC between 1.0 and 1.1 was that 1.1 required alignment to a 64-byte boundary so that bsearch wouldn't be too expensive on the hardware we had available at the time. We fallback to doing brute-force linear search on all bytes anyway so it doesn't matter too much, it was intended more as a guideline for implementation. https://review.coreboot.org/#/c/23203/22/fmap.h@67 PS22, Line 67: int fmap_read_from_buffer(struct fmap **fmap_out, const uint8_t *buf, size_t len); > nit, could be static now Done https://review.coreboot.org/#/c/23203/22/fmap.c File fmap.c: https://review.coreboot.org/#/c/23203/22/fmap.c@1 PS22, Line 1: > nit, missing initial line break Done https://review.coreboot.org/#/c/23203/22/fmap.c@153 PS22, Line 153: int ret = -1; : uint8_t *b > Redundant, probably leftover? Done https://review.coreboot.org/#/c/23203/22/fmap.c@203 PS22, Line 203: } > leaking `fmap` moved above malloc https://review.coreboot.org/#/c/23203/22/fmap.c@260 PS22, Line 260: if (fmap_found) : break; : } : : if (!fmap_found) : goto _free_ret; : : fmap_len = fmap_size(fmap); : struct fmap *tmp = fmap; : fmap = realloc(fmap, fmap_len); : if (!fmap) { : msg_gerr("Failed to realloc.\n"); : free(tmp); : goto _free_ret; : } : : if (flashctx->chip->read(flashctx, (uint8_t *)fmap + sizeof(*fmap), : offset + sizeof(*fmap), fmap_len - sizeof(*fmap))) { : msg_cerr("Cannot read %zu bytes at offset %06zx\n", : fmap_len - sizeof(*fmap), offset + sizeof(*fmap)); : /* Treat read failure to be fatal since this : * should be a valid, usable fmap. */ : goto _free_ret; : } : > This path is flawed a little. At least it's missing an unconditional […] The break seems to have been lost during refactoring :-/ Sigh. I like the idea of doing more stuff outside of the inner loop. I don't think we should ever hit the realloc() a second time, and it should be fine to treat those error paths as fatal. I suppose one could make an argument that if we see a valid fmap header but can't read the whole thing then we should continue trying to find another fmap. But I think in practice that is indicative of a hardware failure or error in the way the firmware ROM is laid out and it's useful to treat it as fatal. Maybe we should return a different code to the caller to indicate this and avoid doing the linear search. https://review.coreboot.org/#/c/23203/22/fmap.c@292 PS22, Line 292: ret = 0; > This would still be set after a read failure, for instance. So it's […] agreed https://review.coreboot.org/#/c/23203/22/fmap.c@321 PS22, Line 321: an fma > How do you pronounce it? Is it `*a* fmap` or `*an* eff-map`? I say "an" in my head. Usually 'a' is used before a noun beginning with a consonant, but that sounds awkward to me in this case so I've updated the comment. https://review.coreboot.org/#/c/23203/22/libflashrom.c File libflashrom.c: https://review.coreboot.org/#/c/23203/22/libflashrom.c@433 PS22, Line 433: struct flashctx *const flashctx, off_t offset, size_t len) > Ugly, but as we were too lazy for proper deserialization again, […] done https://review.coreboot.org/#/c/23203/22/libflashrom.c@468 PS22, Line 468: * 3 if fmap parsing isn't implemented for the host, > Same guard here. Done -- To view, visit https://review.coreboot.org/23203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0e7fad38ed79a84d41358e1f175c36d255786c12 Gerrit-Change-Number: 23203 Gerrit-PatchSet: 24 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 17 Sep 2018 14:39:42 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in flashrom[master]: Add support to get layout from fmap (e.g. coreboot rom)
by David Hendricks (Code Review) 17 Sep '18

17 Sep '18

David Hendricks has uploaded a new patch set (#24) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/23203 ) Change subject: Add support to get layout from fmap (e.g. coreboot rom) ...................................................................... Add support to get layout from fmap (e.g. coreboot rom) Flashmap, or simply fmap, is a binary data format for describing region offsets, sizes, and certain attributes and is widely used by coreboot. This patch adds support for the fmap data format version 1.1 and adds --fmap and --fmap-file arguments. Using --fmap will make flashrom to search the ROM content for fmap data. Using --fmap-file will make flashrom search a supplied file for fmap data. An example of how to update the COREBOOT region of a ROM: flashrom -p programmer --fmap -w coreboot.rom -i COREBOOT flashrom -p programmer --fmap-file coreboot.rom -w coreboot.rom -i COREBOOT The fmap functions are mostly copied from cbfstool. Currently it is made mutually exclusive with other layout options until we are more clever about this input. Change-Id: I0e7fad38ed79a84d41358e1f175c36d255786c12 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: David Hendricks <dhendricks(a)fb.com> --- M Makefile M cli_classic.c M flashrom.8.tmpl A fmap.c A fmap.h M libflashrom.c M libflashrom.h 7 files changed, 651 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/03/23203/24 -- To view, visit https://review.coreboot.org/23203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0e7fad38ed79a84d41358e1f175c36d255786c12 Gerrit-Change-Number: 23203 Gerrit-PatchSet: 24 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com>

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Change in flashrom[master]: Add support to get layout from fmap (e.g. coreboot rom)
by David Hendricks (Code Review) 17 Sep '18

17 Sep '18

David Hendricks has uploaded a new patch set (#23) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/23203 ) Change subject: Add support to get layout from fmap (e.g. coreboot rom) ...................................................................... Add support to get layout from fmap (e.g. coreboot rom) Flashmap, or simply fmap, is a binary data format for describing region offsets, sizes, and certain attributes and is widely used by coreboot. This patch adds support for the fmap data format version 1.1 and adds --fmap and --fmap-file arguments. Using --fmap will make flashrom to search the ROM content for fmap data. Using --fmap-file will make flashrom search a supplied file for fmap data. An example of how to update the COREBOOT region of a ROM: flashrom -p programmer --fmap -w coreboot.rom -i COREBOOT flashrom -p programmer --fmap-file coreboot.rom -w coreboot.rom -i COREBOOT The fmap functions are mostly copied from cbfstool. Currently it is made mutually exclusive with other layout options until we are more clever about this input. Change-Id: I0e7fad38ed79a84d41358e1f175c36d255786c12 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: David Hendricks <dhendricks(a)fb.com> --- M Makefile M cli_classic.c M flashrom.8.tmpl A fmap.c A fmap.h M libflashrom.c M libflashrom.h 7 files changed, 652 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/03/23203/23 -- To view, visit https://review.coreboot.org/23203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0e7fad38ed79a84d41358e1f175c36d255786c12 Gerrit-Change-Number: 23203 Gerrit-PatchSet: 23 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com>

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Change in flashrom[master]: Add initial support for Dediprog SF200.
by Nico Huber (Code Review) 11 Sep '18

11 Sep '18

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/28272 ) Change subject: Add initial support for Dediprog SF200. ...................................................................... Add initial support for Dediprog SF200. Change-Id: I025d1533e249f6a75b6d9015a18a6abf350456b6 Signed-off-by: Jay Thompson <thompson.jay.thomas(a)gmail.com> Signed-off-by: David Hendricks <dhendricks(a)fb.com> Reviewed-on: https://review.coreboot.org/28272 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M dediprog.c 1 file changed, 14 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved Nico Huber: Looks good to me, approved diff --git a/dediprog.c b/dediprog.c index 1a469a7..58f1d43 100644 --- a/dediprog.c +++ b/dediprog.c @@ -51,6 +51,7 @@ enum dediprog_devtype { DEV_UNKNOWN = 0, DEV_SF100 = 100, + DEV_SF200 = 200, DEV_SF600 = 600, }; @@ -152,7 +153,7 @@ }; const struct dev_entry devs_dediprog[] = { - {0x0483, 0xDADA, OK, "Dediprog", "SF100/SF600"}, + {0x0483, 0xDADA, OK, "Dediprog", "SF100/SF200/SF600"}, {0}, }; @@ -181,6 +182,7 @@ /* Firmware version < 5.0.0 is handled explicitly in some cases. */ switch (dediprog_devicetype) { case DEV_SF100: + case DEV_SF200: if (dediprog_firmwareversion < FIRMWARE_VERSION(5, 5, 0)) return PROTOCOL_V1; else @@ -756,10 +758,12 @@ msg_pdbg("Found a %s\n", buf); if (memcmp(buf, "SF100", 0x5) == 0) dediprog_devicetype = DEV_SF100; + else if (memcmp(buf, "SF200", 0x5) == 0) + dediprog_devicetype = DEV_SF200; else if (memcmp(buf, "SF600", 0x5) == 0) dediprog_devicetype = DEV_SF600; else { - msg_perr("Device not a SF100 or SF600!\n"); + msg_perr("Device not a SF100, SF200, or SF600!\n"); return 1; } @@ -1091,12 +1095,17 @@ return 1; } - /* SF100 only has 1 endpoint for in/out, SF600 uses two separate endpoints instead. */ + /* SF100/SF200 uses one in/out endpoint, SF600 uses separate in/out endpoints */ dediprog_in_endpoint = 2; - if (dediprog_devicetype == DEV_SF100) + switch (dediprog_devicetype) { + case DEV_SF100: + case DEV_SF200: dediprog_out_endpoint = 2; - else + break; + default: dediprog_out_endpoint = 1; + break; + } /* Set all possible LEDs as soon as possible to indicate activity. * Because knowing the firmware version is required to set the LEDs correctly we need to this after -- To view, visit https://review.coreboot.org/28272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I025d1533e249f6a75b6d9015a18a6abf350456b6 Gerrit-Change-Number: 28272 Gerrit-PatchSet: 4 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com>

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flashrom-gerrit September 2018