Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28817
Change subject: chipset_enable.c: Mark Broadwell U Premium as DEP
......................................................................
chipset_enable.c: Mark Broadwell U Premium as DEP
As per Laurent Grimaud on the mailing list. I also have said chipset.
Since all ME-enable chipsets are marked as DEP instead of OK, this
one shall follow suit as well.
Change-Id: Ie195e8ec9ea1a2393e31bebdaede4fd3c3301a17
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M chipset_enable.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/17/28817/1
diff --git a/chipset_enable.c b/chipset_enable.c
index 566b1fb..4b28924 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1896,7 +1896,7 @@
{0x8086, 0x9c47, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp},
{0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp},
{0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp},
- {0x8086, 0x9cc3, NT, "Intel", "Broadwell U Premium", enable_flash_pch9_lp},
+ {0x8086, 0x9cc3, DEP, "Intel", "Broadwell U Premium", enable_flash_pch9_lp},
{0x8086, 0x9cc5, NT, "Intel", "Broadwell U Base", enable_flash_pch9_lp},
{0x8086, 0x9cc6, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp},
{0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp},
--
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie195e8ec9ea1a2393e31bebdaede4fd3c3301a17
Gerrit-Change-Number: 28817
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28812
Change subject: flashchips: Mark Macronix MX25U12835F as tested
......................................................................
flashchips: Mark Macronix MX25U12835F as tested
As reported by David Martinka on the mailing list.
Erase has not been tested, but since writes are reported as working, it
is very likely erase works as well.
Change-Id: I172453fe902ccface2a3a85817d775d45dd7cf80
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M flashchips.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/12/28812/1
diff --git a/flashchips.c b/flashchips.c
index 07c8949..f7a94e1 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -8572,7 +8572,7 @@
.page_size = 256,
/* OTP: 512B total; enter 0xB1, exit 0xC1 */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
- .tested = TEST_UNTESTED,
+ .tested = TEST_OK_PREW,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,
.block_erasers =
--
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/27106 )
Change subject: [WIP]layout.c: Use a linked lists for layout
......................................................................
Patch Set 3:
I tested this patch on an Asus P8H61-M PRO using the internal programmer.
I found issues when writing to the flash chip.
When writing, various operations (both with and without --ifd) would report "Chip content is identical to the requested image.", even though the image was different.
--
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Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
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Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
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Gerrit-Comment-Date: Sun, 30 Sep 2018 11:56:30 +0000
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