Hello Stefan Tauner, Youness Alaoui, David Hendricks, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18962
to look at the new patch set (#8).
Change subject: ichspi: Add support for Intel Skylake
......................................................................
ichspi: Add support for Intel Skylake
The Sunrise Point PCH, paired with Skylake, has some minor changes
in the HW sequencing interface:
* Support for more flash regions moved PR* registers
* Only 4KiB erase blocks are supported by the primary erase command
* A second erase command for 64KiB pages was added
* More commands were added for status register access etc.
* A "Dedicated Lock Bits" register was added
No support for the new commands was added.
The SW sequencing interface seems to have moved register location and
is not supported any more officially. It's also untested.
Changes are loosely based on the Skylake support commit in Chromium OS
by Ramya Vijaykumar:
commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1
Author: Ramya Vijaykumar <ramya.vijaykumar(a)intel.com>
flashrom: Add Skylake platform support
Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M ich_descriptors.c
M ich_descriptors.h
M ichspi.c
3 files changed, 227 insertions(+), 87 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/18962/8
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Gerrit-Project: flashrom
Gerrit-Branch: staging
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee
Gerrit-Change-Number: 18962
Gerrit-PatchSet: 8
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at>
Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Nico Huber has posted comments on this change. ( https://review.coreboot.org/18962 )
Change subject: ichspi: Add support for Intel Skylake
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/18962/7/ichspi.c
File ichspi.c:
https://review.coreboot.org/#/c/18962/7/ichspi.c@49
PS7, Line 49: HSFC_WET_OFF 5
> Should be bit 21?
You are off by 16 in both cases ;) the current datasheets treat
HSF STS and CTL as one 32-bit register, where we treat them
separately as HSFS (lower 16 bit) and HSFC (upper 16 bit).
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Gerrit-Comment-Date: Thu, 13 Jul 2017 16:04:52 +0000
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David Hendricks has posted comments on this change. ( https://review.coreboot.org/18962 )
Change subject: ichspi: Add support for Intel Skylake
......................................................................
Patch Set 7: Code-Review-1
(2 comments)
Looks good overall. I am just a bit puzzled with a couple of offsets.
There's also a tiny merge conflict in ich_descriptors.c that is preventing rebasing.
https://review.coreboot.org/#/c/18962/7/ichspi.c
File ichspi.c:
https://review.coreboot.org/#/c/18962/7/ichspi.c@46
PS7, Line 46: PCH100_HSFC_FCYCLE_OFF 1
Which datasheet did you see this in?
I think FCYCLE is bits 20:17 for 100-series and Skylake, but perhaps I'm looking in the wrong places...
https://review.coreboot.org/#/c/18962/7/ichspi.c@49
PS7, Line 49: HSFC_WET_OFF 5
Should be bit 21?
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Gerrit-Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee
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Gerrit-Comment-Date: Thu, 13 Jul 2017 00:52:15 +0000
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