July 2017 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[staging]: chipset_enable: Add support for Intel Skylake / Kabylake
by Youness Alaoui (Code Review) July 13, 2017

July 13, 2017

Youness Alaoui has posted comments on this change. ( https://review.coreboot.org/18925 ) Change subject: chipset_enable: Add support for Intel Skylake / Kabylake ...................................................................... Patch Set 8: > Actually it was correct in the earlier patch versions. I just > forgot about > the rpci_* when restructuring it. Should be fixed now, haven't > retested yet. Actually it wasn't correct in earlier patches. While I apparently commented on patchset 5, looking at my tree, I had actually tested patchset 1, so I already had the cleanup done in a shutdown handler. Anyways, I tested the latest code and I still get the crash. I also moved the register for shutdown to the end of the function to make sure the handler gets registered *after* the rcpi_* handler gets registered, hoping it would mean the pci_access wouldn't get cleaned up until after the rcpi callback is called, but it didn't help. Like I said before, the issue is that the accessor is set to -1 for some reason... ... and I just figured out why.. the machine I'm testing on is using pciutils 3.5.2, but the machine I'm building on is using pciutils 3.3.0. The structure changed (abi change but not api change?) and since the accessor is a 'used internally' its position in the structure changed.. when i print its value, it's actually printing the "numa_mode" field which is set to -1. Anyways, the problem here is that all the libpci APIs take/return a pci_dev pointer, so whichever version of the library you use, the allocations and field accesses from within the library are safe, and the 'non-internal' fields are also safe to use. The issue here is that flashrom/pcidev.c does a copy of the structure as is, but not as a pointer, so the structure has the wrong size and when it's given to a libpci API function, it causes the segfault. So basically, whatever you do, it will always crash because the pci_dev structure has the wrong size in pcidev.c. I'm going to assume that it would still crash regardless of the ich100 code. I think I didn't see it before because on BDW I was using flashrom from the apt repository instead of compiling it myself on a different computer/system. This is the diff I had locally which fixed the crash for me : https://ghostbin.com/paste/6hd26 (this was against patchset 1) Storing the pci_acc in dev->access is because trying to access it doesn't work (it's seen as -1) and without it, I get the error of can't find /sys/class/pci.../1f.5/... I didn't want to show this patch before because it felt like an ugly hack, and that's why I said before "I don't know how it should be fixed", but I think it's correct, at least, partially, we need to store a pci_dev pointer instead of a structure in the rcpi callback data, if we use the pci_get_dev, then we lose the accessor, if we store the pointer as given to us, then we risk using a freed device when the callback is called. My suggestion is, what if instead of creating a new pci_access and setting its method, what if in the case of ich100, we simply change the method of the global 'pacc' ? Will it affect anything? will pci devices get created or the accessor needed after we identify it as pch100 ? If not, then it would be safe to change the method of the global pci_access, and that would resolve the rcpi_ issue if we use pci_get_dev and simply use pacc. -- To view, visit https://review.coreboot.org/18925 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: I000819aff25fbe9764f33df85f040093b82cd948 Gerrit-Change-Number: 18925 Gerrit-PatchSet: 8 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Jul 2017 19:12:46 +0000 Gerrit-HasComments: No

1 0

Change in flashrom[staging]: ich_descriptors: Pretty print an assumed chipset
by build bot (Jenkins) (Code Review) July 13, 2017

July 13, 2017

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20247 ) Change subject: ich_descriptors: Pretty print an assumed chipset ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom_gerrit/438/ : SUCCESS https://qa.coreboot.org/job/flashrom-customrules/467/ : SUCCESS -- To view, visit https://review.coreboot.org/20247 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: Id28cb3abc45c6e7f4c4accfc019579c7448c45d7 Gerrit-Change-Number: 20247 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Jul 2017 16:30:04 +0000 Gerrit-HasComments: No

1 0

Change in flashrom[staging]: ich_descriptors: Update for Intel Skylake
by build bot (Jenkins) (Code Review) July 13, 2017

July 13, 2017

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18973 ) Change subject: ich_descriptors: Update for Intel Skylake ...................................................................... Patch Set 12: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom_gerrit/436/ : SUCCESS https://qa.coreboot.org/job/flashrom-customrules/466/ : SUCCESS -- To view, visit https://review.coreboot.org/18973 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Gerrit-Change-Number: 18973 Gerrit-PatchSet: 12 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Jul 2017 16:29:58 +0000 Gerrit-HasComments: No

1 0

Change in flashrom[staging]: chipset_enable: Set 100 series chipsets to NT
by build bot (Jenkins) (Code Review) July 13, 2017

July 13, 2017

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19047 ) Change subject: chipset_enable: Set 100 series chipsets to NT ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom_gerrit/437/ : SUCCESS https://qa.coreboot.org/job/flashrom-customrules/465/ : SUCCESS -- To view, visit https://review.coreboot.org/19047 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: I9376a0c180b7e73751fbd3c8c37b693d358cbfb8 Gerrit-Change-Number: 19047 Gerrit-PatchSet: 8 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Jul 2017 16:29:56 +0000 Gerrit-HasComments: No

1 0

Change in flashrom[staging]: ich_descriptors: Add function to guess chipset version
by build bot (Jenkins) (Code Review) July 13, 2017

July 13, 2017

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20246 ) Change subject: ich_descriptors: Add function to guess chipset version ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom_gerrit/435/ : SUCCESS https://qa.coreboot.org/job/flashrom-customrules/464/ : SUCCESS -- To view, visit https://review.coreboot.org/20246 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: Ie1736663dc33801b19d3e695c072c61a6c6345a2 Gerrit-Change-Number: 20246 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Jul 2017 16:29:55 +0000 Gerrit-HasComments: No

1 0

Change in flashrom[staging]: ich_descriptors: Draw +0xfff into ICH_FREG_LIMIT()
by build bot (Jenkins) (Code Review) July 13, 2017

July 13, 2017

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19046 ) Change subject: ich_descriptors: Draw +0xfff into ICH_FREG_LIMIT() ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom_gerrit/433/ : SUCCESS https://qa.coreboot.org/job/flashrom-customrules/462/ : SUCCESS -- To view, visit https://review.coreboot.org/19046 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: I11ac0a50b3f32f47879e7cfb7a26068cd0572ede Gerrit-Change-Number: 19046 Gerrit-PatchSet: 8 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Jul 2017 16:29:50 +0000 Gerrit-HasComments: No

1 0

Change in flashrom[staging]: ichspi: Add support for Intel Skylake
by build bot (Jenkins) (Code Review) July 13, 2017

July 13, 2017

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18962 ) Change subject: ichspi: Add support for Intel Skylake ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom_gerrit/434/ : SUCCESS https://qa.coreboot.org/job/flashrom-customrules/463/ : SUCCESS -- To view, visit https://review.coreboot.org/18962 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Gerrit-Change-Number: 18962 Gerrit-PatchSet: 9 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Jul 2017 16:29:49 +0000 Gerrit-HasComments: No

1 0

Change in flashrom[staging]: chipset_enable: Add support for Intel Skylake / Kabylake
by build bot (Jenkins) (Code Review) July 13, 2017

July 13, 2017

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18925 ) Change subject: chipset_enable: Add support for Intel Skylake / Kabylake ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom_gerrit/432/ : SUCCESS https://qa.coreboot.org/job/flashrom-customrules/461/ : SUCCESS -- To view, visit https://review.coreboot.org/18925 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: I000819aff25fbe9764f33df85f040093b82cd948 Gerrit-Change-Number: 18925 Gerrit-PatchSet: 8 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Jul 2017 16:29:44 +0000 Gerrit-HasComments: No

1 0

Change in flashrom[staging]: ichspi: Add support for Intel Skylake
by Nico Huber (Code Review) July 13, 2017

July 13, 2017

Hello Stefan Tauner, Youness Alaoui, David Hendricks, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18962 to look at the new patch set (#9). Change subject: ichspi: Add support for Intel Skylake ...................................................................... ichspi: Add support for Intel Skylake The Sunrise Point PCH, paired with Skylake, has some minor changes in the HW sequencing interface: * Support for more flash regions moved PR* registers * Only 4KiB erase blocks are supported by the primary erase command * A second erase command for 64KiB pages was added * More commands were added for status register access etc. * A "Dedicated Lock Bits" register was added No support for the new commands was added. The SW sequencing interface seems to have moved register location and is not supported any more officially. It's also untested. Changes are loosely based on the Skylake support commit in Chromium OS by Ramya Vijaykumar: commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1 Author: Ramya Vijaykumar <ramya.vijaykumar(a)intel.com> flashrom: Add Skylake platform support Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c M ich_descriptors.h M ichspi.c 3 files changed, 227 insertions(+), 87 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/18962/9 -- To view, visit https://review.coreboot.org/18962 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Gerrit-Change-Number: 18962 Gerrit-PatchSet: 9 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in flashrom[staging]: Drop redundant `enum msglevel`
by Nico Huber (Code Review) July 13, 2017

July 13, 2017

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/20268 ) Change subject: Drop redundant `enum msglevel` ...................................................................... Drop redundant `enum msglevel` Use `enum flashrom_log_level` instead to avoid further confusion. Change-Id: I1895cb8f60da3abf70c9c2953f52414cd2cc10a9 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/20268 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M cli_classic.c M cli_output.c M flash.h M ichspi.c M libflashrom.c M libflashrom.h 6 files changed, 38 insertions(+), 45 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Philippe Mathieu-Daudé: Looks good to me, but someone else must approve Stefan Reinauer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/cli_classic.c b/cli_classic.c index 4c3db4d..441fc91 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -203,7 +203,7 @@ break; case 'V': verbose_screen++; - if (verbose_screen > MSG_DEBUG2) + if (verbose_screen > FLASHROM_MSG_DEBUG2) verbose_logfile = verbose_screen; break; case 'E': diff --git a/cli_output.c b/cli_output.c index e697985..61a9af6 100644 --- a/cli_output.c +++ b/cli_output.c @@ -25,8 +25,8 @@ #include <errno.h> #include "flash.h" -int verbose_screen = MSG_INFO; -int verbose_logfile = MSG_DEBUG2; +enum flashrom_log_level verbose_screen = FLASHROM_MSG_INFO; +enum flashrom_log_level verbose_logfile = FLASHROM_MSG_DEBUG2; #ifndef STANDALONE static FILE *logfile = NULL; @@ -61,17 +61,17 @@ void start_logging(void) { - enum msglevel oldverbose_screen = verbose_screen; + enum flashrom_log_level oldverbose_screen = verbose_screen; /* Shut up the console. */ - verbose_screen = MSG_ERROR; + verbose_screen = FLASHROM_MSG_ERROR; print_version(); verbose_screen = oldverbose_screen; } #endif /* !STANDALONE */ /* Please note that level is the verbosity, not the importance of the message. */ -int flashrom_print_cb(enum msglevel level, const char *fmt, va_list ap) +int flashrom_print_cb(enum flashrom_log_level level, const char *fmt, va_list ap) { int ret = 0; FILE *output_type = stdout; @@ -79,20 +79,20 @@ va_list logfile_args; va_copy(logfile_args, ap); - if (level < MSG_INFO) + if (level < FLASHROM_MSG_INFO) output_type = stderr; if (level <= verbose_screen) { ret = vfprintf(output_type, fmt, ap); /* msg_*spew often happens inside chip accessors in possibly * time-critical operations. Don't slow them down by flushing. */ - if (level != MSG_SPEW) + if (level != FLASHROM_MSG_SPEW) fflush(output_type); } #ifndef STANDALONE if ((level <= verbose_logfile) && logfile) { ret = vfprintf(logfile, fmt, logfile_args); - if (level != MSG_SPEW) + if (level != FLASHROM_MSG_SPEW) fflush(logfile); } #endif /* !STANDALONE */ diff --git a/flash.h b/flash.h index b5eb99b..67c7d20 100644 --- a/flash.h +++ b/flash.h @@ -38,6 +38,7 @@ #undef max #endif +#include "libflashrom.h" #include "layout.h" #define ERROR_PTR ((void*)-1) @@ -312,47 +313,39 @@ void print_chip_support_status(const struct flashchip *chip); /* cli_output.c */ -extern int verbose_screen; -extern int verbose_logfile; +extern enum flashrom_log_level verbose_screen; +extern enum flashrom_log_level verbose_logfile; #ifndef STANDALONE int open_logfile(const char * const filename); int close_logfile(void); void start_logging(void); #endif -enum msglevel { - MSG_ERROR = 0, - MSG_WARN = 1, - MSG_INFO = 2, - MSG_DEBUG = 3, - MSG_DEBUG2 = 4, - MSG_SPEW = 5, -}; -int flashrom_print_cb(enum msglevel level, const char *fmt, va_list ap); +int flashrom_print_cb(enum flashrom_log_level level, const char *fmt, va_list ap); /* Let gcc and clang check for correct printf-style format strings. */ -int print(enum msglevel level, const char *fmt, ...) +int print(enum flashrom_log_level level, const char *fmt, ...) #ifdef __MINGW32__ __attribute__((format(gnu_printf, 2, 3))); #else __attribute__((format(printf, 2, 3))); #endif -#define msg_gerr(...) print(MSG_ERROR, __VA_ARGS__) /* general errors */ -#define msg_perr(...) print(MSG_ERROR, __VA_ARGS__) /* programmer errors */ -#define msg_cerr(...) print(MSG_ERROR, __VA_ARGS__) /* chip errors */ -#define msg_gwarn(...) print(MSG_WARN, __VA_ARGS__) /* general warnings */ -#define msg_pwarn(...) print(MSG_WARN, __VA_ARGS__) /* programmer warnings */ -#define msg_cwarn(...) print(MSG_WARN, __VA_ARGS__) /* chip warnings */ -#define msg_ginfo(...) print(MSG_INFO, __VA_ARGS__) /* general info */ -#define msg_pinfo(...) print(MSG_INFO, __VA_ARGS__) /* programmer info */ -#define msg_cinfo(...) print(MSG_INFO, __VA_ARGS__) /* chip info */ -#define msg_gdbg(...) print(MSG_DEBUG, __VA_ARGS__) /* general debug */ -#define msg_pdbg(...) print(MSG_DEBUG, __VA_ARGS__) /* programmer debug */ -#define msg_cdbg(...) print(MSG_DEBUG, __VA_ARGS__) /* chip debug */ -#define msg_gdbg2(...) print(MSG_DEBUG2, __VA_ARGS__) /* general debug2 */ -#define msg_pdbg2(...) print(MSG_DEBUG2, __VA_ARGS__) /* programmer debug2 */ -#define msg_cdbg2(...) print(MSG_DEBUG2, __VA_ARGS__) /* chip debug2 */ -#define msg_gspew(...) print(MSG_SPEW, __VA_ARGS__) /* general debug spew */ -#define msg_pspew(...) print(MSG_SPEW, __VA_ARGS__) /* programmer debug spew */ -#define msg_cspew(...) print(MSG_SPEW, __VA_ARGS__) /* chip debug spew */ +#define msg_gerr(...) print(FLASHROM_MSG_ERROR, __VA_ARGS__) /* general errors */ +#define msg_perr(...) print(FLASHROM_MSG_ERROR, __VA_ARGS__) /* programmer errors */ +#define msg_cerr(...) print(FLASHROM_MSG_ERROR, __VA_ARGS__) /* chip errors */ +#define msg_gwarn(...) print(FLASHROM_MSG_WARN, __VA_ARGS__) /* general warnings */ +#define msg_pwarn(...) print(FLASHROM_MSG_WARN, __VA_ARGS__) /* programmer warnings */ +#define msg_cwarn(...) print(FLASHROM_MSG_WARN, __VA_ARGS__) /* chip warnings */ +#define msg_ginfo(...) print(FLASHROM_MSG_INFO, __VA_ARGS__) /* general info */ +#define msg_pinfo(...) print(FLASHROM_MSG_INFO, __VA_ARGS__) /* programmer info */ +#define msg_cinfo(...) print(FLASHROM_MSG_INFO, __VA_ARGS__) /* chip info */ +#define msg_gdbg(...) print(FLASHROM_MSG_DEBUG, __VA_ARGS__) /* general debug */ +#define msg_pdbg(...) print(FLASHROM_MSG_DEBUG, __VA_ARGS__) /* programmer debug */ +#define msg_cdbg(...) print(FLASHROM_MSG_DEBUG, __VA_ARGS__) /* chip debug */ +#define msg_gdbg2(...) print(FLASHROM_MSG_DEBUG2, __VA_ARGS__) /* general debug2 */ +#define msg_pdbg2(...) print(FLASHROM_MSG_DEBUG2, __VA_ARGS__) /* programmer debug2 */ +#define msg_cdbg2(...) print(FLASHROM_MSG_DEBUG2, __VA_ARGS__) /* chip debug2 */ +#define msg_gspew(...) print(FLASHROM_MSG_SPEW, __VA_ARGS__) /* general debug spew */ +#define msg_pspew(...) print(FLASHROM_MSG_SPEW, __VA_ARGS__) /* programmer debug spew */ +#define msg_cspew(...) print(FLASHROM_MSG_SPEW, __VA_ARGS__) /* chip debug spew */ /* layout.c */ int register_include_arg(char *name); diff --git a/ichspi.c b/ichspi.c index 218e3b1..be13f91 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1738,7 +1738,7 @@ tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); msg_pdbg("VSCC: "); - prettyprint_ich_reg_vscc(tmp, MSG_DEBUG, true); + prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); } else { if (ich_generation != CHIPSET_BAYTRAIL && desc_valid) { ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); @@ -1751,12 +1751,12 @@ tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); msg_pdbg("LVSCC: "); - prettyprint_ich_reg_vscc(tmp, MSG_DEBUG, true); + prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); msg_pdbg("UVSCC: "); - prettyprint_ich_reg_vscc(tmp, MSG_DEBUG, false); + prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, false); tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); diff --git a/libflashrom.c b/libflashrom.c index 962e96f..6e0f42c 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -84,13 +84,13 @@ global_log_callback = log_callback; } /** @private */ -int print(const enum msglevel level, const char *const fmt, ...) +int print(const enum flashrom_log_level level, const char *const fmt, ...) { if (global_log_callback) { int ret; va_list args; va_start(args, fmt); - ret = global_log_callback((enum flashrom_log_level)level, fmt, args); + ret = global_log_callback(level, fmt, args); va_end(args); return ret; } diff --git a/libflashrom.h b/libflashrom.h index c5d972e..d3f3ded 100644 --- a/libflashrom.h +++ b/libflashrom.h @@ -27,7 +27,7 @@ int flashrom_init(int perform_selfcheck); int flashrom_shutdown(void); /** @ingroup flashrom-general */ -enum flashrom_log_level { /* This has to match enum msglevel. */ +enum flashrom_log_level { FLASHROM_MSG_ERROR = 0, FLASHROM_MSG_WARN = 1, FLASHROM_MSG_INFO = 2, -- To view, visit https://review.coreboot.org/20268 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: merged Gerrit-Change-Id: I1895cb8f60da3abf70c9c2953f52414cd2cc10a9 Gerrit-Change-Number: 20268 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0