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[PATCH] Intel chip id fix-up (ver 2)
by Mattias Mattsson 14 Sep '10

14 Sep '10

This is a new version of an earlier patch. Strip package prefix in constant names (everything before "28F"). Prefix every constant name with INTEL_ Sort intel chip constants by id. Rename the following constants to their "canonical" name: P28F400BT (0x70) -> INTEL_28F400T (28F400BV/BX/CE/CV-T) P28F400BB (0x71) -> INTEL_28F400B (28F400BV/BX/CE/CV-B) P28F004BT (0x78) -> INTEL_28F004T (28F004B5/BE/BV/BX-T) P28F004BB (0x79) -> INTEL_28F004B (28F004B5/BE/BV/BX-B) E_28F008S5 (0xA6) -> INTEL_28F008S3 (28F008S3/S5/SC) E_28F004S5 (0xA7) -> INTEL_28F004S3 (28F008S3/S5/SC) P28F001BXT (0x94) -> INTEL_28F001T (28F001BN/BX-T) P28F001BXB (0x95) -> INTEL_28F001B (28F001BN/BX-B) E_28F016S5 (0xAA) -> INTEL_28F016S3 (28F016S3/S5/SC) Also add chip ids for the following chips: 28F320J5 28F640J5 28F320J3 28F640J3 28F128J3 28F256J3 28F200BL/BV/BX/CV-T 28F200BL/BV/BX/CV-B 28F002BL/BV/BX-B 28F008BE/BV-T 28F008BE/BV-B 28F800B5/BV/CE/CV-T 28F800B5/BV/CE/CV-B 28F016SA/SV 28F008SA 28F008S3/S5/SC 28F008S3/S5/SC 28F016XS 28F010 28F512 28F256A 28F020 28F016B3-T 28F016B3-B 28F008B3-T 28F008B3-B 28F004B3-T 28F004B3-B Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com>

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[PATCH] Winbond chip id fix-up (ver 2)
by Mattias Mattsson 14 Sep '10

14 Sep '10

Hi, This is an updated version of an earlier patch. Now additionally changes all constants: W_nnnn -> WINBOND_Wnnnn W_25nnn -> WINBOND_NEX_W25nnn Kill incorrect ASD chip and vendor id. Group Winbond SPI and Parallell chips separately (they have different vendor ids). Change constant names to the "canonical" chip name for the following ids: W_29C020C (0x45) -> WINBOND_W29C020 (Same as W29C020C, W29C022 and ASD AE29F2008) W_29C040P (0x46) -> WINBOND_W29C040 ("P" is for package type [32-pin PLCC], irrelevant) W_29C011 + W_29EE011 (0xC1) -> WINBOND_W29C010M (Same as W29C011A, W29EE011, W29EE012, and ASD AE29F1008) Also add ids for the following Winbond chips: W25Q40 W25Q128 W19B160BB W19B160BT W19B320SB/W19L320SB W19B320ST/W19L320ST W19B322MB W19B322MT W19B323MB W19B323MT W19B324MB W19B324MT W29C512A/W29EE512 W39L010 W39L040A W39L512 W49F002/W49F002B Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com>

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[PATCH] Nvidia MCP SPI speedup
by Carl-Daniel Hailfinger 14 Sep '10

14 Sep '10

Use caching for Nvidia MCP SPI GPIO accesses. Reduce clock delay to zero. Should result in a 2x speedup, maybe more. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-bitbang_spi_nvidia_mcp_faster/mcp6x_spi.c =================================================================== --- flashrom-bitbang_spi_nvidia_mcp_faster/mcp6x_spi.c (Revision 1130) +++ flashrom-bitbang_spi_nvidia_mcp_faster/mcp6x_spi.c (Arbeitskopie) @@ -42,41 +42,39 @@ void *mcp6x_spibar = NULL; +/* Cached value of last GPIO state. */ +static uint8_t mcp_gpiostate; + static void mcp6x_request_spibus(void) { - uint8_t tmp; + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + mcp_gpiostate |= 1 << MCP6X_SPI_REQUEST; + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp |= 1 << MCP6X_SPI_REQUEST; - mmio_writeb(tmp, mcp6x_spibar + 0x530); - /* Wait until we are allowed to use the SPI bus. */ while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) ; + + /* Update the cache. */ + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); } static void mcp6x_release_spibus(void) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_REQUEST); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_REQUEST); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } static void mcp6x_bitbang_set_cs(int val) { - uint8_t tmp; - /* Requesting and releasing the SPI bus is handled in here to allow the * chipset to use its own SPI engine for native reads. */ if (val == 0) mcp6x_request_spibus(); - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_CS); - tmp |= (val << MCP6X_SPI_CS); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_CS); + mcp_gpiostate |= (val << MCP6X_SPI_CS); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); if (val == 1) mcp6x_release_spibus(); @@ -84,31 +82,22 @@ static void mcp6x_bitbang_set_sck(int val) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_SCK); - tmp |= (val << MCP6X_SPI_SCK); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_SCK); + mcp_gpiostate |= (val << MCP6X_SPI_SCK); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } static void mcp6x_bitbang_set_mosi(int val) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_MOSI); - tmp |= (val << MCP6X_SPI_MOSI); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_MOSI); + mcp_gpiostate |= (val << MCP6X_SPI_MOSI); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } static int mcp6x_bitbang_get_miso(void) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp = (tmp >> MCP6X_SPI_MISO) & 0x1; - return tmp; + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + return (mcp_gpiostate >> MCP6X_SPI_MISO) & 0x1; } static const struct bitbang_spi_master bitbang_spi_master_mcp6x = { @@ -176,9 +165,10 @@ msg_pdbg("SPI control is 0x%04x, req=%i, gnt=%i\n", status, (status >> MCP6X_SPI_REQUEST) & 0x1, (status >> MCP6X_SPI_GRANT) & 0x1); + mcp_gpiostate = status & 0xff; - /* 1 usec halfperiod delay for now. */ - if (bitbang_spi_init(&bitbang_spi_master_mcp6x, 1)) { + /* Zero halfperiod delay. */ + if (bitbang_spi_init(&bitbang_spi_master_mcp6x, 0)) { /* This should never happen. */ msg_perr("MCP6X bitbang SPI master init failed!\n"); return 1; -- http://www.hailfinger.org/

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[commit] r1164 - trunk
by repository service 14 Sep '10

14 Sep '10

Author: hailfinger Date: Tue Sep 14 03:29:49 2010 New Revision: 1164 URL: http://flashrom.org/trac/flashrom/changeset/1164 Log: Use caching for Nvidia MCP SPI GPIO accesses. Reduce clock delay to zero. Tests show more than 2x speedup. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested-by: Andrew Morgan <ziltro(a)ziltro.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/mcp6x_spi.c Modified: trunk/mcp6x_spi.c ============================================================================== --- trunk/mcp6x_spi.c Tue Sep 14 01:00:57 2010 (r1163) +++ trunk/mcp6x_spi.c Tue Sep 14 03:29:49 2010 (r1164) @@ -42,41 +42,39 @@ void *mcp6x_spibar = NULL; +/* Cached value of last GPIO state. */ +static uint8_t mcp_gpiostate; + static void mcp6x_request_spibus(void) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp |= 1 << MCP6X_SPI_REQUEST; - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + mcp_gpiostate |= 1 << MCP6X_SPI_REQUEST; + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); /* Wait until we are allowed to use the SPI bus. */ while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) ; + + /* Update the cache. */ + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); } static void mcp6x_release_spibus(void) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_REQUEST); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_REQUEST); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } static void mcp6x_bitbang_set_cs(int val) { - uint8_t tmp; - /* Requesting and releasing the SPI bus is handled in here to allow the * chipset to use its own SPI engine for native reads. */ if (val == 0) mcp6x_request_spibus(); - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_CS); - tmp |= (val << MCP6X_SPI_CS); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_CS); + mcp_gpiostate |= (val << MCP6X_SPI_CS); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); if (val == 1) mcp6x_release_spibus(); @@ -84,31 +82,22 @@ static void mcp6x_bitbang_set_sck(int val) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_SCK); - tmp |= (val << MCP6X_SPI_SCK); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_SCK); + mcp_gpiostate |= (val << MCP6X_SPI_SCK); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } static void mcp6x_bitbang_set_mosi(int val) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp &= ~(1 << MCP6X_SPI_MOSI); - tmp |= (val << MCP6X_SPI_MOSI); - mmio_writeb(tmp, mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_MOSI); + mcp_gpiostate |= (val << MCP6X_SPI_MOSI); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } static int mcp6x_bitbang_get_miso(void) { - uint8_t tmp; - - tmp = mmio_readb(mcp6x_spibar + 0x530); - tmp = (tmp >> MCP6X_SPI_MISO) & 0x1; - return tmp; + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + return (mcp_gpiostate >> MCP6X_SPI_MISO) & 0x1; } static const struct bitbang_spi_master bitbang_spi_master_mcp6x = { @@ -176,9 +165,10 @@ msg_pdbg("SPI control is 0x%04x, req=%i, gnt=%i\n", status, (status >> MCP6X_SPI_REQUEST) & 0x1, (status >> MCP6X_SPI_GRANT) & 0x1); + mcp_gpiostate = status & 0xff; - /* 1 usec halfperiod delay for now. */ - if (bitbang_spi_init(&bitbang_spi_master_mcp6x, 1)) { + /* Zero halfperiod delay. */ + if (bitbang_spi_init(&bitbang_spi_master_mcp6x, 0)) { /* This should never happen. */ msg_perr("MCP6X bitbang SPI master init failed!\n"); return 1;

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ASUS P5GD2 Premium
by Roberto Malinverni 14 Sep '10

14 Sep '10

Base Board Information from DMIDECODE: Manufacturer: ASUSTeK Computer INC. Product Name: P5GD2-Premium Version: Rev 1.xx Link to official firmware: I can't provide it due to the way Asus's site works... (I can upload my copy somewhere if you want) You have to search here http://support.asus.com/download/download.aspx?SLanguage=en-us filling the 3 search fields with: "motherboard" "socket 775" "p5gd2 premium" Attached are the requested logs.

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Re: [flashrom] ST M25PX32 and M25PX64 flash chip support
by Jason Shriver 14 Sep '10

14 Sep '10

Attached are the test results for the M25PX32 and M25PX64 flash chips. -----Original Message----- From: Jason Shriver [mailto:J.Shriver@F5.com] Sent: Monday, September 13, 2010 11:51 AM To: 'flashrom(a)flashrom.org' Subject: [flashrom] ST M25PX32 and M25PX64 flash chip support Add support for ST M25PX32 and M25PX64 flash chips. Probe, read, erase and write have been tested and all are functional. Signed-off-by: Jason Shriver <j.shriver(a)f5.com>

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[Patch] Reduce usage of w836xx_memw
by David Borg 14 Sep '10

14 Sep '10

Patch reduces usage of w836xx_memw functions and board enables, which would become redundant after "[PATCH] W83697xx superio flash enable" is hooked up to generic superio detection. Signed-off-by: David Borg <borg.db(a)gmail.com> Regards, David

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[commit] r1163 - trunk
by repository service 14 Sep '10

14 Sep '10

Author: uwe Date: Tue Sep 14 01:00:57 2010 New Revision: 1163 URL: http://flashrom.org/trac/flashrom/changeset/1163 Log: Add support for the abit BM6 board. Signed-off-by: Tim ter Laak <timl(a)scintilla.utwente.nl> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Mon Sep 13 21:59:28 2010 (r1162) +++ trunk/board_enable.c Tue Sep 14 01:00:57 2010 (r1163) @@ -1155,6 +1155,15 @@ /* * Suited for: + * - abit BM6 + */ +static int intel_piix4_gpo26_lower(void) +{ + return intel_piix4_gpo_set(26, 0); +} + +/* + * Suited for: * - Intel SE440BX-2 */ static int intel_piix4_gpo27_lower(void) @@ -1828,6 +1837,7 @@ /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ #if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, + {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower}, {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, "abit", "IC7", 0, NT, intel_ich_gpio23_raise}, {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Mon Sep 13 21:59:28 2010 (r1162) +++ trunk/print.c Tue Sep 14 01:00:57 2010 (r1163) @@ -283,6 +283,7 @@ B("A-Trend", "ATC-6220", 1, "http://www.motherboard.cz/mb/atrend/atc6220.htm", NULL), B("abit", "AN-M2", 1, "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), B("abit", "AX8", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), + B("abit", "BM6", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), B("abit", "Fatal1ty F-I90HD", 1, "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), B("abit", "IC7", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), B("abit", "IP35", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=LG…", NULL),

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Re: [coreboot] flashrom patch: add support for Abit AB-BM6 board
by Carl-Daniel Hailfinger 14 Sep '10

14 Sep '10

Hi Tim, it seems your flashrom patch from exactly two years ago slipped through the cracks until now. I'm very sorry about that. Do you still own the board? If yes, could you please run download latest flashrom (at least 0.9.2, preferably latest svn) and provide the output of the following commands (as root): flashrom -V superiotool -deV flashrom supports DMI matching since a few months, so it may be possible to identify your board that way. And with superiotool output, we could perhaps improve matching a bit more. You already provided full lspci -nnvvxx output at http://marc.info/?l=linuxbios&m=122276697617977&w=2 so I'm not going to request that again. (I couldn't link to the coreboot.org mailing list archives because that message is corrupt). On 03.09.2008 11:42, Tim ter Laak wrote: > This patch adds support for the Abit AB-BM6 mainboard to flashrom. > > The biggest part is a generic function to lower a GPIO line on the > PIIX4E southbridge, copied and adapted from its ich_gpio_raise() > counterpart (mostly lower instead of raise, followed names from the > PIIX4E datasheet). The board specific function then uses this to lower > GPO 26. > > Signed-off-by: Tim ter Laak <timl(a)scintilla.utwente.nl> > > +/** > + * Suited for Abit AB-BM6. > + */ > +static int piix4_gpio26_lower(const char *name) > +{ > + return piix4_gpio_lower(name, 0x8086, 0x7113, 0x40, 0x34, 0xffc0, 26); With current flashrom, the line above would look like this: return intel_piix4_gpo_set(26, 0); > +} > + > + > + > +/** > * Suited for Acorp 6A815EPD. > */ > static int board_acorp_6a815epd(const char *name) > @@ -672,6 +724,8 @@ > NULL, NULL, "GIGABYTE GA-7VT600", board_biostar_p4m80_m4}, > {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, > NULL, NULL, "MSI K8T Neo2", w83627thf_gpio4_4_raise_2e}, > + {0x8086, 0x7190, 0x0000, 0x0000, 0x8086, 0x7110, 0x0000, 0x0000, > + "abit", "ab-bm6", "Abit AB-BM6", piix4_gpio26_lower}, > {0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */ > }; If DMI is useful on your board, we could try to match the DMI strings and avoid the -m abit:ab-bm6 parameter for flashrom. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH] support for MX251635E
by Stephan GUILLOUX 13 Sep '10

13 Sep '10

Hello, Below, a patch to allow MX25L1635E support, as discussed with Carldani. It is also available in attachment. This one is working fine on our system, with flashrom 0.9.2 Sorry for the patch, but I do not have svn anymore. I had to use a standard diff -c. Make good use of it;-) Stephan. Signed-off-by: Stephan Guilloux<stephan.guilloux(a)free.fr> --- ./flashrom-0.9.2.org/flashchips.h 2010-04-20 21:34:31.000000000 +0200 +++ ./flashrom-0.9.2.new/flashchips.h 2010-09-03 09:37:39.386013000 +0200 @@ -284,7 +284,8 @@ #define MX_25L6405 0x2017 /* MX25L3205{,D} */ #define MX_25L12805 0x2018 /* MX25L12805 */ #define MX_25L1635D 0x2415 +#define MX_25L1635E 0x2515 /* MX25L1635{E} */ #define MX_25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */ #define MX_29F001B 0x19 #define MX_29F001T 0x18 --- ./flashrom-0.9.2.org/flashchips.c 2010-04-20 21:34:31.000000000 +0200 +++ ./flashrom-0.9.2.new/flashchips.c 2010-09-03 09:38:44.637466000 +0200 @@ -2775,6 +2775,37 @@ { .vendor = "Macronix", + .name = "MX25L1635E", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = MX_ID, + .model_id = MX_25L1635E, + .total_size = 2048, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Macronix", .name = "MX25L3205", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = MX_ID,

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