flashrom

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[PATCH] Mark SST49LF160C tested for erase
by Ed Swierk 06 Oct '10

06 Oct '10

I have tested the erase operation with the SST49LF160C LPC flash chip. Signed-off-by: Ed Swierk <eswierk(a)aristanetworks.com> --- Index: flashrom-0.9.2-r1057/flashchips.c =================================================================== --- flashrom-0.9.2-r1057.orig/flashchips.c +++ flashrom-0.9.2-r1057/flashchips.c @@ -4582,7 +4582,7 @@ struct flashchip flashchips[] = { .total_size = 2048, .page_size = 4 * 1024, .feature_bits = FEATURE_REGISTERMAP, - .tested = TEST_OK_PRW, + .tested = TEST_OK_PREW, .probe = probe_82802ab, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (sst49lfxxxc.c) */ .block_erasers =

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[PATCH] DJGPP: Avoid leak on lowmem mapping error
by Carl-Daniel Hailfinger 06 Oct '10

06 Oct '10

DJGPP: Avoid leaking memory on lowmem mapping error. Add a clarifying comment about why low memory is never unmapped. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-djgpp_physmap_noleaks/physmap.c =================================================================== --- flashrom-djgpp_physmap_noleaks/physmap.c (Revision 1194) +++ flashrom-djgpp_physmap_noleaks/physmap.c (Arbeitskopie) @@ -56,6 +56,8 @@ } if (__djgpp_map_physical_memory(realmem_map, (1024 * 1024), 0)) { + free(realmem_map); + realmem_map = NULL; return ERROR_PTR; } @@ -95,7 +97,9 @@ { __dpmi_meminfo mi; - /* we ignore unmaps for our first 1MB */ + /* There is no known way to unmap the first 1 MB. The DPMI server will + * do this for us on exit. + */ if ((virt_addr >= realmem_map) && ((virt_addr + len) <= (realmem_map + (1024 * 1024)))) { return; } -- http://www.hailfinger.org/

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[commit] r1195 - trunk
by repository service 06 Oct '10

06 Oct '10

Author: hailfinger Date: Wed Oct 6 01:21:51 2010 New Revision: 1195 URL: http://flashrom.org/trac/flashrom/changeset/1195 Log: DJGPP: Avoid leaking memory on lowmem mapping error. Add a clarifying comment about why low memory is never unmapped. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/physmap.c Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Wed Oct 6 00:29:08 2010 (r1194) +++ trunk/physmap.c Wed Oct 6 01:21:51 2010 (r1195) @@ -56,6 +56,8 @@ } if (__djgpp_map_physical_memory(realmem_map, (1024 * 1024), 0)) { + free(realmem_map); + realmem_map = NULL; return ERROR_PTR; } @@ -95,7 +97,9 @@ { __dpmi_meminfo mi; - /* we ignore unmaps for our first 1MB */ + /* There is no known way to unmap the first 1 MB. The DPMI server will + * do this for us on exit. + */ if ((virt_addr >= realmem_map) && ((virt_addr + len) <= (realmem_map + (1024 * 1024)))) { return; }

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flash log of a LENOVO A57 - 97048HG
by Maurizio Pedrazzi 06 Oct '10

06 Oct '10

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Re: [flashrom] Speedup SST 25VF032B and 25VF064C programming
by Carl-Daniel Hailfinger 06 Oct '10

06 Oct '10

Hi Helge, I'm very sorry, it seems that the patch repeatedly slipped through the cracks because patchwork didn't pick it up (application/octet-stream for the attachment may have been the reason, but that is fixed now). On 06.08.2010 15:28, Wagner, Helge (GE Intelligent Platforms) wrote: > I have tested both SST 25VF032B and SST 25VF064C on a QM57 (IbexPeak) > system and found that the reprogramming of these chips is very slow. > > So i have changed the programming engine for the 25VF064C from > "spi_chip_write_1" to "spi_chip_write_256". > I have tested the 25VF064C with the new engine and it works fine. > > For the 25VF032B i have changed the programming engine from > "spi_chip_write_1" to "spi_aai_write". > I have tested this engine, too, and found it working (speedup was from > 228 to 113 seconds). > > While testing i found that some commands needed by some of the > algorithms are not in the OPCODE table. So i have implemented the > on-the-fly reprogramming of the OPCODE table (in the ICH engine). > > Signed-off-by: Helge Wagner <helge.wagner(a)ge.com> > > Speedup for new 25VF032B programming algorithm: from 3091 [sic!] to 123 > seconds > This patch is a huge step forward for many Intel chipsets. Thank you! > diff -urN flashrom-0.9.2/ichspi.c flashrom/ichspi.c > --- flashrom-0.9.2/ichspi.c 2010-07-28 00:41:39.000000000 +0200 > +++ flashrom/ichspi.c 2010-08-06 14:46:47.000000000 +0200 > @@ -708,11 +777,11 @@ > /* find cmd in opcodes-table */ > opcode_index = find_opcode(curopcodes, cmd); > if (opcode_index == -1) { > - /* FIXME: Reprogram opcodes if possible. Autodetect type of > - * opcode by checking readcnt/writecnt. > - */ > - msg_pdbg("Invalid OPCODE 0x%02x\n", cmd); > - return SPI_INVALID_OPCODE; > + opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt); > This line should be conditional on !ichspi_lock. I have changed that in the commit. > + if (opcode_index == -1) { > + msg_pdbg("Invalid OPCODE 0x%02x\n", cmd); > + return SPI_INVALID_OPCODE; > + } > } > > opcode = &(curopcodes->opcode[opcode_index]); > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> ICH dynamic opcode reprogramming patch committed in r1193. AAI write for SST25VF032B and page write for SST25VF064C committed in r1194. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1194 - trunk
by repository service 06 Oct '10

06 Oct '10

Author: hailfinger Date: Wed Oct 6 00:29:08 2010 New Revision: 1194 URL: http://flashrom.org/trac/flashrom/changeset/1194 Log: Use AAI write for SST SST25VF032B. Speedup from 228 to 113 seconds. Use page (256 byte) write for SST SST25VF064C. Speedup from 3091 to 123 seconds. Signed-off-by: Helge Wagner <helge.wagner(a)ge.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipdrivers.h trunk/flashchips.c trunk/spi25.c Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Wed Oct 6 00:06:05 2010 (r1193) +++ trunk/chipdrivers.h Wed Oct 6 00:29:08 2010 (r1194) @@ -63,7 +63,8 @@ int spi_nbyte_read(int addr, uint8_t *bytes, int len); int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); -int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); +int spi_aai_write_new(struct flashchip *flash, uint8_t *buf, int start, int len); +int spi_aai_write(struct flashchip *flash, uint8_t *buf); /* 82802ab.c */ uint8_t wait_82802ab(chipaddr bios); Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Wed Oct 6 00:06:05 2010 (r1193) +++ trunk/flashchips.c Wed Oct 6 00:29:08 2010 (r1194) @@ -4860,7 +4860,7 @@ .model_id = SST_SST25VF032B, .total_size = 4096, .page_size = 256, - .tested = TEST_OK_PRW, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -4883,7 +4883,7 @@ }, }, .unlock = spi_disable_blockprotect, - .write = spi_chip_write_1, + .write = spi_aai_write, .read = spi_chip_read, }, @@ -4918,7 +4918,7 @@ }, }, .unlock = spi_disable_blockprotect, - .write = spi_chip_write_1, + .write = spi_chip_write_256, .read = spi_chip_read, }, Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Wed Oct 6 00:06:05 2010 (r1193) +++ trunk/spi25.c Wed Oct 6 00:29:08 2010 (r1194) @@ -1300,7 +1300,7 @@ return spi_chip_write_1_new(flash, buf, 0, flash->total_size * 1024); } -int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len) +int spi_aai_write_new(struct flashchip *flash, uint8_t *buf, int start, int len) { uint32_t pos = start; int result; @@ -1391,3 +1391,17 @@ spi_write_disable(); return 0; } + +int spi_aai_write(struct flashchip *flash, uint8_t *buf) +{ + /* Erase first */ + msg_cinfo("Erasing flash before programming... "); + if (erase_flash(flash)) { + msg_cerr("ERASE FAILED!\n"); + return -1; + } + msg_cinfo("done.\n"); + + return spi_aai_write_new(flash, buf, 0, flash->total_size * 1024); +} +

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Flashrom Tutorial
by Kyle Wood 06 Oct '10

06 Oct '10

I am Interested in exploring the uses of this software with my Bus Pirate. Have you made a tutorial for using this? I have looked over the Wiki and have found no explanation on how to use this and a severe lack of documentation. A valid tutorial would really help the vast majority of potential users and donators. Sincerely, Kyle D Wood

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[commit] r1193 - trunk
by repository service 06 Oct '10

06 Oct '10

Author: hailfinger Date: Wed Oct 6 00:06:05 2010 New Revision: 1193 URL: http://flashrom.org/trac/flashrom/changeset/1193 Log: Implement on-the-fly reprogramming of the ICH SPI OPCODE table. Signed-off-by: Helge Wagner <helge.wagner(a)ge.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Tue Oct 5 23:48:43 2010 (r1192) +++ trunk/ichspi.c Wed Oct 6 00:06:05 2010 (r1193) @@ -30,6 +30,7 @@ * ST M25P32 already tested * ST M25P64 * AT 25DF321 already tested + * ... and many more SPI flash devices * */ @@ -197,8 +198,76 @@ } }; +/* List of opcodes with their corresponding spi_type + * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode + * is needed which is currently not in the chipset OPCODE table + */ +static OPCODE POSSIBLE_OPCODES[] = { + {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte + {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data + {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector + {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg + {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature + {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register + {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID + {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase + {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase + {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase + {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment +}; + static OPCODES O_EXISTING = {}; +static uint8_t lookup_spi_type(uint8_t opcode) +{ + int a; + + for (a = 0; a < sizeof(POSSIBLE_OPCODES)/sizeof(POSSIBLE_OPCODES[0]); a++) { + if (POSSIBLE_OPCODES[a].opcode == opcode) + return POSSIBLE_OPCODES[a].spi_type; + } + + return 0xFF; +} + +static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt) +{ + uint8_t spi_type; + + spi_type = lookup_spi_type(opcode); + if (spi_type > 3) { + /* Try to guess spi type from read/write sizes. + * The following valid writecnt/readcnt combinations exist: + * writecnt = 4, readcnt >= 0 + * writecnt = 1, readcnt >= 0 + * writecnt >= 4, readcnt = 0 + * writecnt >= 1, readcnt = 0 + * writecnt >= 1 is guaranteed for all commands. + */ + if (readcnt == 0) + /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS + * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data + * bytes are actual the address, they go to the bus anyhow + */ + spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; + else if (writecnt == 1) // and readcnt is > 0 + spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; + else if (writecnt == 4) // and readcnt is > 0 + spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + // else we have an invalid case, will be handled below + } + if (spi_type <= 3) { + int oppos=2; // use original JEDEC_BE_D8 offset + curopcodes->opcode[oppos].opcode = opcode; + curopcodes->opcode[oppos].spi_type = spi_type; + program_opcodes(curopcodes); + oppos = find_opcode(curopcodes, opcode); + msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); + return oppos; + } + return -1; +} + static int find_opcode(OPCODES *op, uint8_t opcode) { int a; @@ -710,11 +779,12 @@ /* find cmd in opcodes-table */ opcode_index = find_opcode(curopcodes, cmd); if (opcode_index == -1) { - /* FIXME: Reprogram opcodes if possible. Autodetect type of - * opcode by checking readcnt/writecnt. - */ - msg_pdbg("Invalid OPCODE 0x%02x\n", cmd); - return SPI_INVALID_OPCODE; + if (!ichspi_lock) + opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt); + if (opcode_index == -1) { + msg_pdbg("Invalid OPCODE 0x%02x\n", cmd); + return SPI_INVALID_OPCODE; + } } opcode = &(curopcodes->opcode[opcode_index]); @@ -827,21 +897,10 @@ * No need to bother with fixups. */ if (!ichspi_lock) { - msg_pdbg("%s: FIXME: Add on-the-fly" - " reprogramming of the " - "chipset opcode list.\n", - __func__); - /* FIXME: Reprogram opcode menu. - * Find a less-useful opcode, replace it - * with the wanted opcode, detect optype - * and reprogram the opcode menu. - * Update oppos so the next if-statement - * can do something useful. - */ - //curopcodes.opcode[lessusefulindex] = (cmds + 1)->writearr[0]); - //update_optypes(curopcodes); - //program_opcodes(curopcodes); - //oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]); + oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt); + if (oppos == -1) + continue; + curopcodes->opcode[oppos].atomic = preoppos + 1; continue; } }

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[PATCH] Add a board-enable for the ASRock K7S41, chipset-enable for SiS 741
by Uwe Hermann 05 Oct '10

05 Oct '10

See patch. I literally guessed this board-enable and was lucky at the very first try :) Not sure if DMI matching is required (I guess it is), please let me know if I should change that. lspci/superiotool/flashrom -w are attached. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1192 - trunk
by repository service 05 Oct '10

05 Oct '10

Author: uwe Date: Tue Oct 5 23:48:43 2010 New Revision: 1192 URL: http://flashrom.org/trac/flashrom/changeset/1192 Log: Add a board-enable for the ASRock K7S41, chipset-enable for SiS 741. This also adds (and marks as tested) a chipset-enable for the SiS 741. All operations successfully tested on hardware. lspci/superiotool: http://www.flashrom.org/pipermail/flashrom/2010-September/004710.html Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/chipset_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Tue Oct 5 23:32:29 2010 (r1191) +++ trunk/board_enable.c Tue Oct 5 23:48:43 2010 (r1192) @@ -390,6 +390,7 @@ * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237 * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235 + * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF */ static int w836xx_memw_enable_2e(void) { @@ -1885,6 +1886,7 @@ {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, + {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Tue Oct 5 23:32:29 2010 (r1191) +++ trunk/chipset_enable.c Tue Oct 5 23:48:43 2010 (r1192) @@ -1153,6 +1153,7 @@ {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540}, {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540}, {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540}, + {0x1039, 0x0741, OK, "SiS", "741", enable_flash_sis540}, {0x1039, 0x0745, OK, "SiS", "745", enable_flash_sis540}, {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540}, {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Tue Oct 5 23:32:29 2010 (r1191) +++ trunk/print.c Tue Oct 5 23:48:43 2010 (r1192) @@ -307,6 +307,7 @@ B("ASRock", "A330GC", 1, "http://www.asrock.com/mb/overview.asp?Model=A330GC", NULL), B("ASRock", "A770CrossFire", 1, "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2\%2b", NULL), B("ASRock", "ALiveNF6G-DVI", 1, "http://www.asrock.com/mb/overview.asp?Model=ALiveNF6G-DVI", NULL), + B("ASRock", "K7S41", 1, "http://www.asrock.com/mb/overview.asp?Model=K7S41", NULL), B("ASRock", "K7VT4A+", 0, "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=", "No chip found, probably due to flash translation. http://www.flashrom.org/pipermail/flashrom/2009-August/000393.html"), B("ASRock", "K8S8X", 1, "http://www.asrock.com/mb/overview.asp?Model=K8S8X", NULL), B("ASRock", "M3A790GXH/128M", 1, "http://www.asrock.com/MB/overview.asp?Model=M3A790GXH/128M", NULL),

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