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[PATCH] Board enable for Dell OptiPlex GX1 (try 2)
by Mattias Mattsson 05 Oct '10

05 Oct '10

Add board enable for Dell OptiPlex GX1. This is a new version of an earlier patch. - Change matching PCI ID:s to ethernet and north bridge. - Truncate board name to "OptiPlex GX1" as this patch probably apply to the whole series (they share the same vendor BIOS download). - Add URL to print.c - Marked board as OK. This was tested with an earlier version of flashrom (r1092), but nothing has changed that affects this patch (GPO30 is still always available on PIIX4). lspci output: http://www.flashrom.org/pipermail/flashrom/2010-July/004042.html Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com> Thanks! -mattias

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[commit] r1191 - trunk
by repository service 05 Oct '10

05 Oct '10

Author: mhm Date: Tue Oct 5 23:32:29 2010 New Revision: 1191 URL: http://flashrom.org/trac/flashrom/changeset/1191 Log: Add board enable for Dell OptiPlex GX1 and mark Intel 28F002BC/BL/BV/BX-T as tested. Match on ethernet and north bridge. This is tested on an OptiPlex GX1 400L+ but will probably work for the whole GX1 series as they all share the same vendor BIOS. lspci/flashrom output http://www.flashrom.org/pipermail/flashrom/2010-July/004042.html lspci output (OptiPlex GX1 unknown model) http://www.coreboot.org/pipermail/coreboot/2010-May/058040.html superiotool output (OptiPlex GX1 266L+) http://www.flashrom.org/pipermail/flashrom/2009-July/000207.html lspci/dmidecode output (OptiPlex GX1 266L+) http://www.coreboot.org/pipermail/coreboot/2009-July/050958.html Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/flashchips.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Tue Oct 5 23:21:09 2010 (r1190) +++ trunk/board_enable.c Tue Oct 5 23:32:29 2010 (r1191) @@ -1195,6 +1195,15 @@ } /* + * Suited for: + * - Dell OptiPlex GX1 + */ +static int intel_piix4_gpo30_lower(void) +{ + return intel_piix4_gpo_set(30, 0); +} + +/* * Set a GPIO line on a given Intel ICH LPC controller. */ static int intel_ich_gpio_set(int gpio, int raise) @@ -1904,6 +1913,7 @@ {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, + {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, NULL}, Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Tue Oct 5 23:21:09 2010 (r1190) +++ trunk/flashchips.c Tue Oct 5 23:32:29 2010 (r1191) @@ -3196,7 +3196,7 @@ .model_id = INTEL_28F002T, .total_size = 256, .page_size = 256 * 1024, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_82802ab, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .block_erasers = Modified: trunk/print.c ============================================================================== --- trunk/print.c Tue Oct 5 23:21:09 2010 (r1190) +++ trunk/print.c Tue Oct 5 23:32:29 2010 (r1191) @@ -390,6 +390,7 @@ B("Biostar", "TA780G M2+", 1, "http://www.biostar.com.tw/app/en/t-series/content.php?S_ID=344", NULL), B("Boser", "HS-6637", 0, "http://www.boser.com.tw/manual/HS-62376637v3.4.pdf", "Reported by Mark Robinson <mark(a)zl2tod.net> to flashrom(a)coreboot.org, no public archive. Missing board enable and/or F29C51002T unlocking. May work now."), B("Congatec", "conga-X852", 1, "http://www.congatec.com/single_news+M57715f6263d.html?&L=1", NULL), + B("Dell", "OptiPlex GX1", 1, "http://support.dell.com/support/edocs/systems/ban_gx1/en/index.htm", NULL), B("Dell", "PowerEdge 1850", 1, "http://support.dell.com/support/edocs/systems/pe1850/en/index.htm", NULL), B("DFI", "855GME-MGF", 0, "http://www.dfi.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWindow?…", "Probably needs a board enable. http://www.coreboot.org/pipermail/coreboot/2009-May/048549.html"), B("DFI", "Blood-Iron P35 T2RL", 1, "http://lp.lanparty.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWin…", NULL),

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Quickfix for broken writes on FT2232H based programmers
by Uwe Hermann 05 Oct '10

05 Oct '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1190 - trunk
by repository service 05 Oct '10

05 Oct '10

Author: uwe Date: Tue Oct 5 23:21:09 2010 New Revision: 1190 URL: http://flashrom.org/trac/flashrom/changeset/1190 Log: Quickfix for broken writes on FT2232H based programmers. Not sure if this is the final/correct fix, but for now it definately fixes writes on FT2232H hardware. I have tested this on both, the DLP Design DLP-USB1232H, and the openbiosprog-spi hardware. Thanks to Joshua Roys <roysjosh(a)gmail.com> for the hint on IRC. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ft2232_spi.c Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Tue Oct 5 22:28:36 2010 (r1189) +++ trunk/ft2232_spi.c Tue Oct 5 23:21:09 2010 (r1190) @@ -195,7 +195,7 @@ msg_perr("Unable to set latency timer\n"); } - if (ftdi_write_data_set_chunksize(ftdic, 512)) { + if (ftdi_write_data_set_chunksize(ftdic, 256)) { msg_perr("Unable to set chunk size\n"); }

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[PATCH] Intel chip id fix-up (ver 3)
by Mattias Mattsson 05 Oct '10

05 Oct '10

This is a new version of an earlier patch. Make sure all chip variants are present in .name strings in flashchips.c Strip package prefix in constant names (everything before "28F"). Prefix every constant name with INTEL_ Sort intel chip constants by id. Rename the following constants to their "canonical" name: P28F400BT (0x70) -> INTEL_28F400T (28F400BV/BX/CE/CV-T) P28F400BB (0x71) -> INTEL_28F400B (28F400BV/BX/CE/CV-B) P28F004BT (0x78) -> INTEL_28F004T (28F004B5/BE/BV/BX-T) P28F004BB (0x79) -> INTEL_28F004B (28F004B5/BE/BV/BX-B) E_28F008S5 (0xA6) -> INTEL_28F008S3 (28F008S3/S5/SC) E_28F004S5 (0xA7) -> INTEL_28F004S3 (28F008S3/S5/SC) P28F001BXT (0x94) -> INTEL_28F001T (28F001BN/BX-T) P28F001BXB (0x95) -> INTEL_28F001B (28F001BN/BX-B) E_28F016S5 (0xAA) -> INTEL_28F016S3 (28F016S3/S5/SC) Also add chip ids for the following chips: 28F320J5 28F640J5 28F320J3 28F640J3 28F128J3 28F256J3 28F200BL/BV/BX/CV-T 28F200BL/BV/BX/CV-B 28F002BL/BV/BX-B 28F008BE/BV-T 28F008BE/BV-B 28F800B5/BV/CE/CV-T 28F800B5/BV/CE/CV-B 28F016SA/SV 28F008SA 28F008S3/S5/SC 28F008S3/S5/SC 28F016XS 28F010 28F512 28F256A 28F020 28F016B3-T 28F016B3-B 28F008B3-T 28F008B3-B 28F004B3-T 28F004B3-B Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com>

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MSI MS-6163 Pro / Winbond W29C020C
by Mattias Mattsson 05 Oct '10

05 Oct '10

Hi, I have tested flashrom r1143 patched with board enable (raise GPO14) on an MSI MS-6163 with Winbond W29C020C flash. Probe, read, erase, write all work. Logs attached. Thanks, -mattias

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[PATCH] Board enable for MSI MS-6163 (MS-6163 Pro/BX Master)
by Mattias Mattsson 05 Oct '10

05 Oct '10

Tested on an MS-6163 Pro. This board has the same DMI-string and board enable as the "BX Master". (Confirmed by downloading and taking apart the vendor BIOS.) lspci output: http://www.flashrom.org/pipermail/flashrom/2010-August/004461.html Thanks, -mattias

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[commit] r1189 - trunk
by repository service 05 Oct '10

05 Oct '10

Author: mhm Date: Tue Oct 5 22:28:36 2010 New Revision: 1189 URL: http://flashrom.org/trac/flashrom/changeset/1189 Log: Make sure all chip variants are present in .name strings in flashchips.c Strip package prefix in constant names (everything before "28F"). Prefix every constant name with INTEL_ Sort intel chip constants by ID. Rename the following constants to their "canonical" name: P28F400BT (0x70 -> INTEL_28F400T (28F400BV/BX/CE/CV-T) P28F400BB (0x71) -> INTEL_28F400B (28F400BV/BX/CE/CV-B) P28F004BT (0x78) -> INTEL_28F004T (28F004B5/BE/BV/BX-T) P28F004BB (0x79) -> INTEL_28F004B (28F004B5/BE/BV/BX-B) E_28F008S5 (0xA6) -> INTEL_28F008S3 (28F008S3/S5/SC) E_28F004S5 (0xA7) -> INTEL_28F004S3 (28F008S3/S5/SC) P28F001BXT (0x94) -> INTEL_28F001T (28F001BN/BX-T) P28F001BXB (0x95) -> INTEL_28F001B (28F001BN/BX-B) E_28F016S5 (0xAA) -> INTEL_28F016S3 (28F016S3/S5/SC) Add chip IDs for the following chips: 28F320J5 28F640J5 28F320J3 28F640J3 28F128J3 28F256J3 28F200BL/BV/BX/CV-T 28F200BL/BV/BX/CV-B 28F002BL/BV/BX-B 28F008BE/BV-T 28F008BE/BV-B 28F800B5/BV/CE/CV-T 28F800B5/BV/CE/CV-B 28F016SA/SV 28F008SA 28F008S3/S5/SC 28F008S3/S5/SC 28F016XS 28F010 28F512 28F256A 28F020 28F016B3-T 28F016B3-B 28F008B3-T 28F008B3-B 28F004B3-T 28F004B3-B Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Tue Oct 5 21:19:48 2010 (r1188) +++ trunk/flashchips.c Tue Oct 5 22:28:36 2010 (r1189) @@ -3138,10 +3138,10 @@ { .vendor = "Intel", - .name = "28F001BX-B", + .name = "28F001BN/BX-B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F001BXB, + .model_id = INTEL_28F001B, .total_size = 128, .page_size = 128 * 1024, /* 8k + 2x4k + 112k */ .tested = TEST_UNTESTED, @@ -3164,10 +3164,10 @@ { .vendor = "Intel", - .name = "28F001BX-T", + .name = "28F001BN/BX-T", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F001BXT, + .model_id = INTEL_28F001T, .total_size = 128, .page_size = 128 * 1024, /* 112k + 2x4k + 8k */ .tested = TEST_UNTESTED, @@ -3190,10 +3190,10 @@ { .vendor = "Intel", - .name = "28F002BC-T", + .name = "28F002BC/BL/BV/BX-T", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F002BC, + .model_id = INTEL_28F002T, .total_size = 256, .page_size = 256 * 1024, .tested = TEST_UNTESTED, @@ -3217,10 +3217,10 @@ { .vendor = "Intel", - .name = "28F004S5", + .name = "28F008S3/S5/SC", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = E_28F004S5, + .model_id = INTEL_28F004S3, .total_size = 512, .page_size = 256, .tested = TEST_UNTESTED, @@ -3240,10 +3240,10 @@ { .vendor = "Intel", - .name = "28F004BV/BE-B", + .name = "28F004B5/BE/BV/BX-B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F004BB, + .model_id = INTEL_28F004B, .total_size = 512, .page_size = 128 * 1024, /* maximal block size */ .tested = TEST_UNTESTED, @@ -3267,10 +3267,10 @@ { .vendor = "Intel", - .name = "28F004BV/BE-T", + .name = "28F004B5/BE/BV/BX-T", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F004BT, + .model_id = INTEL_28F004T, .total_size = 512, .page_size = 128 * 1024, /* maximal block size */ .tested = TEST_UNTESTED, @@ -3294,10 +3294,10 @@ { .vendor = "Intel", - .name = "28F400BV/CV/CE-B", + .name = "28F400BV/BX/CE/CV-B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F400BB, + .model_id = INTEL_28F400B, .total_size = 512, .page_size = 128 * 1024, /* maximal block size */ .feature_bits = FEATURE_ADDR_SHIFTED, @@ -3322,10 +3322,10 @@ { .vendor = "Intel", - .name = "28F400BV/CV/CE-T", + .name = "28F400BV/BX/CE/CV-T", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F400BT, + .model_id = INTEL_28F400T, .total_size = 512, .page_size = 128 * 1024, /* maximal block size */ .feature_bits = FEATURE_ADDR_SHIFTED, @@ -3353,7 +3353,7 @@ .name = "82802AB", .bustype = CHIP_BUSTYPE_FWH, .manufacture_id = INTEL_ID, - .model_id = I_82802AB, + .model_id = INTEL_82802AB, .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP, @@ -3377,7 +3377,7 @@ .name = "82802AC", .bustype = CHIP_BUSTYPE_FWH, .manufacture_id = INTEL_ID, - .model_id = I_82802AC, + .model_id = INTEL_82802AC, .total_size = 1024, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Tue Oct 5 21:19:48 2010 (r1188) +++ trunk/flashchips.h Tue Oct 5 22:28:36 2010 (r1189) @@ -296,18 +296,45 @@ #define IMT_IM29F004T 0xAF #define INTEL_ID 0x89 /* Intel */ -#define I_82802AB 0xAD -#define I_82802AC 0xAC -#define E_28F004S5 0xA7 -#define E_28F008S5 0xA6 -#define E_28F016S5 0xAA -#define P28F001BXT 0x94 /* 28F001BX-T */ -#define P28F001BXB 0x95 /* 28F001BX-B */ -#define P28F002BC 0x7C /* 28F002BC-T */ -#define P28F004BT 0x78 /* 28F004BV/BE-T */ -#define P28F004BB 0x79 /* 28F004BV/BE-B */ -#define P28F400BT 0x70 /* 28F400BV/CV/CE-T */ -#define P28F400BB 0x71 /* 28F400BV/CV/CE-B */ +#define INTEL_28F320J5 0x14 +#define INTEL_28F640J5 0x15 +#define INTEL_28F320J3 0x16 +#define INTEL_28F640J3 0x17 +#define INTEL_28F128J3 0x18 +#define INTEL_28F256J3 0x1D +#define INTEL_28F400T 0x70 /* 28F400BV/BX/CE/CV-T */ +#define INTEL_28F400B 0x71 /* 28F400BV/BX/CE/CV-B */ +#define INTEL_28F200T 0x74 /* 28F200BL/BV/BX/CV-T */ +#define INTEL_28F200B 0x75 /* 28F200BL/BV/BX/CV-B */ +#define INTEL_28F004T 0x78 /* 28F004B5/BE/BV/BX-T */ +#define INTEL_28F004B 0x79 /* 28F004B5/BE/BV/BX-B */ +#define INTEL_28F002T 0x7C /* 28F002BC/BL/BV/BX-T */ +#define INTEL_28F002B 0x7D /* 28F002BL/BV/BX-B */ +#define INTEL_28F001T 0x94 /* 28F001BN/BX-T */ +#define INTEL_28F001B 0x95 /* 28F001BN/BX-B */ +#define INTEL_28F008T 0x98 /* 28F008BE/BV-T */ +#define INTEL_28F008B 0x99 /* 28F008BE/BV-B */ +#define INTEL_28F800T 0x9C /* 28F800B5/BV/CE/CV-T */ +#define INTEL_28F800B 0x9D /* 28F800B5/BV/CE/CV-B */ +#define INTEL_28F016SV 0xA0 /* 28F016SA/SV */ +#define INTEL_28F008SA 0xA2 +#define INTEL_28F008S3 0xA6 /* 28F008S3/S5/SC */ +#define INTEL_28F004S3 0xA7 /* 28F008S3/S5/SC */ +#define INTEL_28F016XS 0xA8 +#define INTEL_28F016S3 0xAA /* 28F016S3/S5/SC */ +#define INTEL_82802AC 0xAC +#define INTEL_82802AB 0xAD +#define INTEL_28F010 0xB4 +#define INTEL_28F512 0xB8 +#define INTEL_28F256A 0xB9 +#define INTEL_28F020 0xBD +#define INTEL_28F016B3T 0xD0 /* 28F016B3-T */ +#define INTEL_28F016B3B 0xD1 /* 28F016B3-B */ +#define INTEL_28F008B3T 0xD2 /* 28F008B3-T */ +#define INTEL_28F008B3B 0xD3 /* 28F008B3-B */ +#define INTEL_28F004B3T 0xD4 /* 28F004B3-T */ +#define INTEL_28F004B3B 0xD5 /* 28F004B3-B */ + #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */

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Re: [flashrom] [PATCH] RayeR speedups, variable port
by RayeR 05 Oct '10

05 Oct '10

Hi, I did some speed test on 4MB SPI flash: read: spipgm 2:41 flashrom 2:44 erase spipgm 0:21 flashrom 3:34 So you can see the read speed has improved :) Martin > > Great. Please note that the parameter changed from > > -p rayer_bitbang_spi > > to > > -p rayer_spi > > because the short form is faster to type, and users do not care at all > > about bitbanging.

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[commit] r1188 - trunk
by repository service 05 Oct '10

05 Oct '10

Author: hailfinger Date: Tue Oct 5 21:19:48 2010 New Revision: 1188 URL: http://flashrom.org/trac/flashrom/changeset/1188 Log: Speed up RayeR SPIPGM driver in flashrom by a factor of 2. Allow specification of an alternate base address with flashrom -p rayer_spi:iobase=0x278 Any base address is allowed as long as it is nonzero, below 65536 and a multiple of four. Read speed is now on par with original spipgm.exe. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested-by: Martin Rehak <rayer(a)seznam.cz> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/flashrom.8 trunk/rayer_spi.c Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Tue Oct 5 19:29:35 2010 (r1187) +++ trunk/flashrom.8 Tue Oct 5 21:19:48 2010 (r1188) @@ -397,7 +397,19 @@ (in Hz). The default is the maximum frequency of 8 MHz. .TP .BR "rayer_spi " programmer -No parameters defined yet. More information about the hardware is available at +The default I/O base address used for the parallel port is 0x378 and you can use +the optional +.B iobase +parameter to specify an alternate base I/O address with the +.sp +.B " flashrom \-p rayer_spi:iobase=baseaddr" +.sp +syntax where +.B baseaddr +is base I/O port address of the parallel port, which must be a multiple of +four. Make sure to not forget the "0x" prefix for hexadecimal port addresses. +.sp +More information about the hardware is available at http://rayer.ic.cz/elektro/spipgm.htm .SH EXIT STATUS flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem Modified: trunk/rayer_spi.c ============================================================================== --- trunk/rayer_spi.c Tue Oct 5 19:29:35 2010 (r1187) +++ trunk/rayer_spi.c Tue Oct 5 21:19:48 2010 (r1188) @@ -30,6 +30,7 @@ */ #if defined(__i386__) || defined(__x86_64__) +#include <stdlib.h> #include "flash.h" #include "programmer.h" @@ -43,45 +44,33 @@ /* Pins for slave->master direction */ #define SPI_MISO_PIN 6 -static int lpt_iobase; +static uint16_t lpt_iobase; -/* FIXME: All rayer_bitbang_set_* functions could use caching of the value - * stored at port lpt_iobase to avoid unnecessary INB. In theory, only one - * INB(lpt_iobase) would be needed on programmer init to get the initial - * value. - */ +/* Cached value of last byte sent. */ +static uint8_t lpt_outbyte; -void rayer_bitbang_set_cs(int val) +static void rayer_bitbang_set_cs(int val) { - uint8_t tmp; - - tmp = INB(lpt_iobase); - tmp &= ~(1 << SPI_CS_PIN); - tmp |= (val << SPI_CS_PIN); - OUTB(tmp, lpt_iobase); + lpt_outbyte &= ~(1 << SPI_CS_PIN); + lpt_outbyte |= (val << SPI_CS_PIN); + OUTB(lpt_outbyte, lpt_iobase); } -void rayer_bitbang_set_sck(int val) +static void rayer_bitbang_set_sck(int val) { - uint8_t tmp; - - tmp = INB(lpt_iobase); - tmp &= ~(1 << SPI_SCK_PIN); - tmp |= (val << SPI_SCK_PIN); - OUTB(tmp, lpt_iobase); + lpt_outbyte &= ~(1 << SPI_SCK_PIN); + lpt_outbyte |= (val << SPI_SCK_PIN); + OUTB(lpt_outbyte, lpt_iobase); } -void rayer_bitbang_set_mosi(int val) +static void rayer_bitbang_set_mosi(int val) { - uint8_t tmp; - - tmp = INB(lpt_iobase); - tmp &= ~(1 << SPI_MOSI_PIN); - tmp |= (val << SPI_MOSI_PIN); - OUTB(tmp, lpt_iobase); + lpt_outbyte &= ~(1 << SPI_MOSI_PIN); + lpt_outbyte |= (val << SPI_MOSI_PIN); + OUTB(lpt_outbyte, lpt_iobase); } -int rayer_bitbang_get_miso(void) +static int rayer_bitbang_get_miso(void) { uint8_t tmp; @@ -100,16 +89,49 @@ int rayer_spi_init(void) { - /* Pick a default value for now. */ - lpt_iobase = 0x378; + char *portpos = NULL; - msg_pdbg("Using port 0x%x as I/O base for parallel port access.\n", + /* Non-default port requested? */ + portpos = extract_programmer_param("iobase"); + if (portpos) { + char *endptr = NULL; + unsigned long tmp; + tmp = strtoul(portpos, &endptr, 0); + /* Port 0, port >0x10000, unaligned ports and garbage strings + * are rejected. + */ + if (!tmp || (tmp >= 0x10000) || (tmp & 0x3) || + (*endptr != '\0')) { + /* Using ports below 0x100 is a really bad idea, and + * should only be done if no port between 0x100 and + * 0xfffc works due to routing issues. + */ + msg_perr("Error: iobase= specified, but the I/O base " + "given was invalid.\nIt must be a multiple of " + "0x4 and lie between 0x100 and 0xfffc.\n"); + free(portpos); + return 1; + } else { + lpt_iobase = (uint16_t)tmp; + msg_pinfo("Non-default I/O base requested. This will " + "not change the hardware settings.\n"); + } + } else { + /* Pick a default value for the I/O base. */ + lpt_iobase = 0x378; + } + free(portpos); + + msg_pdbg("Using address 0x%x as I/O base for parallel port access.\n", lpt_iobase); get_io_perms(); - /* 1 usec halfperiod delay for now. */ - if (bitbang_spi_init(&bitbang_spi_master_rayer, 1)) + /* Get the initial value before writing to any line. */ + lpt_outbyte = INB(lpt_iobase); + + /* Zero halfperiod delay. */ + if (bitbang_spi_init(&bitbang_spi_master_rayer, 0)) return 1; buses_supported = CHIP_BUSTYPE_SPI;

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