flashrom

flashrom@flashrom.org

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9161 discussions

Flashrom Tutorial
by Kyle Wood 06 Oct '10

06 Oct '10

I am Interested in exploring the uses of this software with my Bus Pirate. Have you made a tutorial for using this? I have looked over the Wiki and have found no explanation on how to use this and a severe lack of documentation. A valid tutorial would really help the vast majority of potential users and donators. Sincerely, Kyle D Wood

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[commit] r1193 - trunk
by repository service 06 Oct '10

06 Oct '10

Author: hailfinger Date: Wed Oct 6 00:06:05 2010 New Revision: 1193 URL: http://flashrom.org/trac/flashrom/changeset/1193 Log: Implement on-the-fly reprogramming of the ICH SPI OPCODE table. Signed-off-by: Helge Wagner <helge.wagner(a)ge.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Tue Oct 5 23:48:43 2010 (r1192) +++ trunk/ichspi.c Wed Oct 6 00:06:05 2010 (r1193) @@ -30,6 +30,7 @@ * ST M25P32 already tested * ST M25P64 * AT 25DF321 already tested + * ... and many more SPI flash devices * */ @@ -197,8 +198,76 @@ } }; +/* List of opcodes with their corresponding spi_type + * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode + * is needed which is currently not in the chipset OPCODE table + */ +static OPCODE POSSIBLE_OPCODES[] = { + {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte + {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data + {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector + {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg + {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature + {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register + {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID + {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase + {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase + {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase + {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment +}; + static OPCODES O_EXISTING = {}; +static uint8_t lookup_spi_type(uint8_t opcode) +{ + int a; + + for (a = 0; a < sizeof(POSSIBLE_OPCODES)/sizeof(POSSIBLE_OPCODES[0]); a++) { + if (POSSIBLE_OPCODES[a].opcode == opcode) + return POSSIBLE_OPCODES[a].spi_type; + } + + return 0xFF; +} + +static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt) +{ + uint8_t spi_type; + + spi_type = lookup_spi_type(opcode); + if (spi_type > 3) { + /* Try to guess spi type from read/write sizes. + * The following valid writecnt/readcnt combinations exist: + * writecnt = 4, readcnt >= 0 + * writecnt = 1, readcnt >= 0 + * writecnt >= 4, readcnt = 0 + * writecnt >= 1, readcnt = 0 + * writecnt >= 1 is guaranteed for all commands. + */ + if (readcnt == 0) + /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS + * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data + * bytes are actual the address, they go to the bus anyhow + */ + spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; + else if (writecnt == 1) // and readcnt is > 0 + spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; + else if (writecnt == 4) // and readcnt is > 0 + spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + // else we have an invalid case, will be handled below + } + if (spi_type <= 3) { + int oppos=2; // use original JEDEC_BE_D8 offset + curopcodes->opcode[oppos].opcode = opcode; + curopcodes->opcode[oppos].spi_type = spi_type; + program_opcodes(curopcodes); + oppos = find_opcode(curopcodes, opcode); + msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); + return oppos; + } + return -1; +} + static int find_opcode(OPCODES *op, uint8_t opcode) { int a; @@ -710,11 +779,12 @@ /* find cmd in opcodes-table */ opcode_index = find_opcode(curopcodes, cmd); if (opcode_index == -1) { - /* FIXME: Reprogram opcodes if possible. Autodetect type of - * opcode by checking readcnt/writecnt. - */ - msg_pdbg("Invalid OPCODE 0x%02x\n", cmd); - return SPI_INVALID_OPCODE; + if (!ichspi_lock) + opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt); + if (opcode_index == -1) { + msg_pdbg("Invalid OPCODE 0x%02x\n", cmd); + return SPI_INVALID_OPCODE; + } } opcode = &(curopcodes->opcode[opcode_index]); @@ -827,21 +897,10 @@ * No need to bother with fixups. */ if (!ichspi_lock) { - msg_pdbg("%s: FIXME: Add on-the-fly" - " reprogramming of the " - "chipset opcode list.\n", - __func__); - /* FIXME: Reprogram opcode menu. - * Find a less-useful opcode, replace it - * with the wanted opcode, detect optype - * and reprogram the opcode menu. - * Update oppos so the next if-statement - * can do something useful. - */ - //curopcodes.opcode[lessusefulindex] = (cmds + 1)->writearr[0]); - //update_optypes(curopcodes); - //program_opcodes(curopcodes); - //oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]); + oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt); + if (oppos == -1) + continue; + curopcodes->opcode[oppos].atomic = preoppos + 1; continue; } }

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[PATCH] Add a board-enable for the ASRock K7S41, chipset-enable for SiS 741
by Uwe Hermann 05 Oct '10

05 Oct '10

See patch. I literally guessed this board-enable and was lucky at the very first try :) Not sure if DMI matching is required (I guess it is), please let me know if I should change that. lspci/superiotool/flashrom -w are attached. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

3 3

[commit] r1192 - trunk
by repository service 05 Oct '10

05 Oct '10

Author: uwe Date: Tue Oct 5 23:48:43 2010 New Revision: 1192 URL: http://flashrom.org/trac/flashrom/changeset/1192 Log: Add a board-enable for the ASRock K7S41, chipset-enable for SiS 741. This also adds (and marks as tested) a chipset-enable for the SiS 741. All operations successfully tested on hardware. lspci/superiotool: http://www.flashrom.org/pipermail/flashrom/2010-September/004710.html Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/chipset_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Tue Oct 5 23:32:29 2010 (r1191) +++ trunk/board_enable.c Tue Oct 5 23:48:43 2010 (r1192) @@ -390,6 +390,7 @@ * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237 * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235 + * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF */ static int w836xx_memw_enable_2e(void) { @@ -1885,6 +1886,7 @@ {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, + {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Tue Oct 5 23:32:29 2010 (r1191) +++ trunk/chipset_enable.c Tue Oct 5 23:48:43 2010 (r1192) @@ -1153,6 +1153,7 @@ {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540}, {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540}, {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540}, + {0x1039, 0x0741, OK, "SiS", "741", enable_flash_sis540}, {0x1039, 0x0745, OK, "SiS", "745", enable_flash_sis540}, {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540}, {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Tue Oct 5 23:32:29 2010 (r1191) +++ trunk/print.c Tue Oct 5 23:48:43 2010 (r1192) @@ -307,6 +307,7 @@ B("ASRock", "A330GC", 1, "http://www.asrock.com/mb/overview.asp?Model=A330GC", NULL), B("ASRock", "A770CrossFire", 1, "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2\%2b", NULL), B("ASRock", "ALiveNF6G-DVI", 1, "http://www.asrock.com/mb/overview.asp?Model=ALiveNF6G-DVI", NULL), + B("ASRock", "K7S41", 1, "http://www.asrock.com/mb/overview.asp?Model=K7S41", NULL), B("ASRock", "K7VT4A+", 0, "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=", "No chip found, probably due to flash translation. http://www.flashrom.org/pipermail/flashrom/2009-August/000393.html"), B("ASRock", "K8S8X", 1, "http://www.asrock.com/mb/overview.asp?Model=K8S8X", NULL), B("ASRock", "M3A790GXH/128M", 1, "http://www.asrock.com/MB/overview.asp?Model=M3A790GXH/128M", NULL),

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[PATCH] Board enable for Dell OptiPlex GX1 (try 2)
by Mattias Mattsson 05 Oct '10

05 Oct '10

Add board enable for Dell OptiPlex GX1. This is a new version of an earlier patch. - Change matching PCI ID:s to ethernet and north bridge. - Truncate board name to "OptiPlex GX1" as this patch probably apply to the whole series (they share the same vendor BIOS download). - Add URL to print.c - Marked board as OK. This was tested with an earlier version of flashrom (r1092), but nothing has changed that affects this patch (GPO30 is still always available on PIIX4). lspci output: http://www.flashrom.org/pipermail/flashrom/2010-July/004042.html Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com> Thanks! -mattias

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[commit] r1191 - trunk
by repository service 05 Oct '10

05 Oct '10

Author: mhm Date: Tue Oct 5 23:32:29 2010 New Revision: 1191 URL: http://flashrom.org/trac/flashrom/changeset/1191 Log: Add board enable for Dell OptiPlex GX1 and mark Intel 28F002BC/BL/BV/BX-T as tested. Match on ethernet and north bridge. This is tested on an OptiPlex GX1 400L+ but will probably work for the whole GX1 series as they all share the same vendor BIOS. lspci/flashrom output http://www.flashrom.org/pipermail/flashrom/2010-July/004042.html lspci output (OptiPlex GX1 unknown model) http://www.coreboot.org/pipermail/coreboot/2010-May/058040.html superiotool output (OptiPlex GX1 266L+) http://www.flashrom.org/pipermail/flashrom/2009-July/000207.html lspci/dmidecode output (OptiPlex GX1 266L+) http://www.coreboot.org/pipermail/coreboot/2009-July/050958.html Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/flashchips.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Tue Oct 5 23:21:09 2010 (r1190) +++ trunk/board_enable.c Tue Oct 5 23:32:29 2010 (r1191) @@ -1195,6 +1195,15 @@ } /* + * Suited for: + * - Dell OptiPlex GX1 + */ +static int intel_piix4_gpo30_lower(void) +{ + return intel_piix4_gpo_set(30, 0); +} + +/* * Set a GPIO line on a given Intel ICH LPC controller. */ static int intel_ich_gpio_set(int gpio, int raise) @@ -1904,6 +1913,7 @@ {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, + {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, NULL}, Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Tue Oct 5 23:21:09 2010 (r1190) +++ trunk/flashchips.c Tue Oct 5 23:32:29 2010 (r1191) @@ -3196,7 +3196,7 @@ .model_id = INTEL_28F002T, .total_size = 256, .page_size = 256 * 1024, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_82802ab, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .block_erasers = Modified: trunk/print.c ============================================================================== --- trunk/print.c Tue Oct 5 23:21:09 2010 (r1190) +++ trunk/print.c Tue Oct 5 23:32:29 2010 (r1191) @@ -390,6 +390,7 @@ B("Biostar", "TA780G M2+", 1, "http://www.biostar.com.tw/app/en/t-series/content.php?S_ID=344", NULL), B("Boser", "HS-6637", 0, "http://www.boser.com.tw/manual/HS-62376637v3.4.pdf", "Reported by Mark Robinson <mark(a)zl2tod.net> to flashrom(a)coreboot.org, no public archive. Missing board enable and/or F29C51002T unlocking. May work now."), B("Congatec", "conga-X852", 1, "http://www.congatec.com/single_news+M57715f6263d.html?&L=1", NULL), + B("Dell", "OptiPlex GX1", 1, "http://support.dell.com/support/edocs/systems/ban_gx1/en/index.htm", NULL), B("Dell", "PowerEdge 1850", 1, "http://support.dell.com/support/edocs/systems/pe1850/en/index.htm", NULL), B("DFI", "855GME-MGF", 0, "http://www.dfi.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWindow?…", "Probably needs a board enable. http://www.coreboot.org/pipermail/coreboot/2009-May/048549.html"), B("DFI", "Blood-Iron P35 T2RL", 1, "http://lp.lanparty.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWin…", NULL),

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Quickfix for broken writes on FT2232H based programmers
by Uwe Hermann 05 Oct '10

05 Oct '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1190 - trunk
by repository service 05 Oct '10

05 Oct '10

Author: uwe Date: Tue Oct 5 23:21:09 2010 New Revision: 1190 URL: http://flashrom.org/trac/flashrom/changeset/1190 Log: Quickfix for broken writes on FT2232H based programmers. Not sure if this is the final/correct fix, but for now it definately fixes writes on FT2232H hardware. I have tested this on both, the DLP Design DLP-USB1232H, and the openbiosprog-spi hardware. Thanks to Joshua Roys <roysjosh(a)gmail.com> for the hint on IRC. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ft2232_spi.c Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Tue Oct 5 22:28:36 2010 (r1189) +++ trunk/ft2232_spi.c Tue Oct 5 23:21:09 2010 (r1190) @@ -195,7 +195,7 @@ msg_perr("Unable to set latency timer\n"); } - if (ftdi_write_data_set_chunksize(ftdic, 512)) { + if (ftdi_write_data_set_chunksize(ftdic, 256)) { msg_perr("Unable to set chunk size\n"); }

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[PATCH] Intel chip id fix-up (ver 3)
by Mattias Mattsson 05 Oct '10

05 Oct '10

This is a new version of an earlier patch. Make sure all chip variants are present in .name strings in flashchips.c Strip package prefix in constant names (everything before "28F"). Prefix every constant name with INTEL_ Sort intel chip constants by id. Rename the following constants to their "canonical" name: P28F400BT (0x70) -> INTEL_28F400T (28F400BV/BX/CE/CV-T) P28F400BB (0x71) -> INTEL_28F400B (28F400BV/BX/CE/CV-B) P28F004BT (0x78) -> INTEL_28F004T (28F004B5/BE/BV/BX-T) P28F004BB (0x79) -> INTEL_28F004B (28F004B5/BE/BV/BX-B) E_28F008S5 (0xA6) -> INTEL_28F008S3 (28F008S3/S5/SC) E_28F004S5 (0xA7) -> INTEL_28F004S3 (28F008S3/S5/SC) P28F001BXT (0x94) -> INTEL_28F001T (28F001BN/BX-T) P28F001BXB (0x95) -> INTEL_28F001B (28F001BN/BX-B) E_28F016S5 (0xAA) -> INTEL_28F016S3 (28F016S3/S5/SC) Also add chip ids for the following chips: 28F320J5 28F640J5 28F320J3 28F640J3 28F128J3 28F256J3 28F200BL/BV/BX/CV-T 28F200BL/BV/BX/CV-B 28F002BL/BV/BX-B 28F008BE/BV-T 28F008BE/BV-B 28F800B5/BV/CE/CV-T 28F800B5/BV/CE/CV-B 28F016SA/SV 28F008SA 28F008S3/S5/SC 28F008S3/S5/SC 28F016XS 28F010 28F512 28F256A 28F020 28F016B3-T 28F016B3-B 28F008B3-T 28F008B3-B 28F004B3-T 28F004B3-B Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com>

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MSI MS-6163 Pro / Winbond W29C020C
by Mattias Mattsson 05 Oct '10

05 Oct '10

Hi, I have tested flashrom r1143 patched with board enable (raise GPO14) on an MSI MS-6163 with Winbond W29C020C flash. Probe, read, erase, write all work. Logs attached. Thanks, -mattias

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