flashrom

flashrom@flashrom.org

5 participants
9161 discussions

Re: [flashrom] [PATCH] kill central list of SPI programmers
by Carl-Daniel Hailfinger 09 Mar '11

09 Mar '11

Auf 18.07.2010 17:20, Michael Karcher schrieb: > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > Go ahead. Your code is an improvement over the current state, and I can send a followup patch with the changes I suggested in my review. Please compile-test before committing. You can activate all drivers (on a machine with libftdi) with make CONFIG_ATAHPT=yes CONFIG_NICNATSEMI=yes CONFIG_DEDIPROG=yes Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

[PATCH]Improve libpayload support, provide libflashrom.a target
by Georgi, Patrick 08 Mar '11

08 Mar '11

Hi, attached patch contains a couple of build fixes for libpayload builds, adds a "libpayload" OS_ARCH (which disables serial and usb programmers and sets up the build to use lpgcc), and provides a new make target "libflashrom.a" which combines all object files except the CLI_OBJS class into libflashrom.a. For a successful build you also need the libpayload patches on the coreboot mailing list until they're checked in. libflashrom.a still suffers from a variety of exit(1)s here and there, so it's not quite a librarified flashrom yet, but it's a start. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> -- Patrick Georgi SINA-Development - High Security secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com Sitz: Kronprinzenstraße 30, 45128 Essen / Amtsgericht Essen HRB 13615 Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg

2 2

[patch] improve termios settings on some OSes
by Jonathan A. Kollasch 08 Mar '11

08 Mar '11

Fix termios settings on, at least, NetBSD. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net>

1 0

[commit] r1280 - trunk
by repository service 08 Mar '11

08 Mar '11

Author: oxygene Date: Tue Mar 8 08:17:44 2011 New Revision: 1280 URL: http://flashrom.org/trac/flashrom/changeset/1280 Log: Fix and improve libpayload platform support - Fix various minor compile issues (eg. include necessary standard headers) - Fix compilation of libpayload code paths - Provide libpayload support in Makefile - Add make target "libflashrom.a" which links non-CLI code to static library Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Tested-with-DOS-crosscompiler-by: Idwer Vollering <vidwer(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/Makefile trunk/physmap.c trunk/spi.c trunk/udelay.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Tue Mar 8 01:23:49 2011 (r1279) +++ trunk/Makefile Tue Mar 8 08:17:44 2011 (r1280) @@ -28,6 +28,8 @@ MANDIR ?= $(PREFIX)/share/man CFLAGS ?= -Os -Wall -Wshadow EXPORTDIR ?= . +AR ?= ar +RANLIB ?= ranlib WARNERROR ?= yes @@ -82,6 +84,39 @@ endif endif +ifeq ($(OS_ARCH), libpayload) +CC:=CC=i386-elf-gcc lpgcc +AR:=i386-elf-ar +RANLIB:=i386-elf-ranlib +CPPFLAGS += -DSTANDALONE +ifeq ($(CONFIG_DUMMY), yes) +UNSUPPORTED_FEATURES += CONFIG_DUMMY=yes +else +override CONFIG_DUMMY = no +endif +ifeq ($(CONFIG_BUSPIRATE_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_BUSPIRATE_SPI=yes +else +override CONFIG_BUSPIRATE_SPI = no +endif +ifeq ($(CONFIG_SERPROG), yes) +UNSUPPORTED_FEATURES += CONFIG_SERPROG=yes +else +override CONFIG_SERPROG = no +endif +# Dediprog and FT2232 are not supported with libpayload (missing libusb support) +ifeq ($(CONFIG_DEDIPROG), yes) +UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes +else +override CONFIG_DEDIPROG = no +endif +ifeq ($(CONFIG_FT2232_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_FT2232_SPI=yes +else +override CONFIG_FT2232_SPI = no +endif +endif + CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o @@ -335,11 +370,16 @@ # We could use PULLED_IN_LIBS, but that would be ugly. FEATURE_LIBS += $(shell LC_ALL=C grep -q "NEEDLIBZ := yes" .libdeps && printf "%s" "-lz") -OBJS = $(CHIP_OBJS) $(CLI_OBJS) $(PROGRAMMER_OBJS) $(LIB_OBJS) +LIBFLASHROM_OBJS = $(CHIP_OBJS) $(PROGRAMMER_OBJS) $(LIB_OBJS) +OBJS = $(CLI_OBJS) $(LIBFLASHROM_OBJS) $(PROGRAM)$(EXEC_SUFFIX): $(OBJS) $(CC) $(LDFLAGS) -o $(PROGRAM)$(EXEC_SUFFIX) $(OBJS) $(FEATURE_LIBS) $(LIBS) +libflashrom.a: $(LIBFLASHROM_OBJS) + $(AR) rcs $@ $^ + $(RANLIB) $@ + # TAROPTIONS reduces information leakage from the packager's system. # If other tar programs support command line arguments for setting uid/gid of # stored files, they can be handled here as well. @@ -352,7 +392,7 @@ # This includes all frontends and libflashrom. # We don't use EXEC_SUFFIX here because we want to clean everything. clean: - rm -f $(PROGRAM) $(PROGRAM).exe *.o *.d + rm -f $(PROGRAM) $(PROGRAM).exe libflashrom.a *.o *.d distclean: clean rm -f .features .libdeps Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Tue Mar 8 01:23:49 2011 (r1279) +++ trunk/physmap.c Tue Mar 8 08:17:44 2011 (r1280) @@ -492,6 +492,7 @@ int libpayload_wrmsr(int addr, msr_t msr) { _wrmsr(addr, msr.lo | ((unsigned long long)msr.hi << 32)); + return 0; } #else msr_t rdmsr(int addr) Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Tue Mar 8 01:23:49 2011 (r1279) +++ trunk/spi.c Tue Mar 8 08:17:44 2011 (r1280) @@ -22,6 +22,7 @@ * Contains the generic SPI framework */ +#include <strings.h> #include <string.h> #include "flash.h" #include "flashchips.h" Modified: trunk/udelay.c ============================================================================== --- trunk/udelay.c Tue Mar 8 01:23:49 2011 (r1279) +++ trunk/udelay.c Tue Mar 8 08:17:44 2011 (r1280) @@ -182,6 +182,7 @@ } #else +#include <libpayload.h> void myusec_calibrate_delay(void) {

1 0

[PATCH] IT85* cleanups/fixes
by Carl-Daniel Hailfinger 08 Mar '11

08 Mar '11

Various IT85* cleanups and fixes. Fix a few typos. Change the EC memory region mapping name. Drop unused function parameter. Use mmio_writeb()/mmio_readb() to get reliable access to volatile memory locations instead of plain pointer access which gets optimized away by gcc. Use own it85_* SPI high-level chip read/write functions instead of relying on unrelated ICH functions. AFAICS this should be mergeable both in the chromium tree and vanilla flashrom. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-it85spi_cleanup/it85spi.c =================================================================== --- flashrom-it85spi_cleanup/it85spi.c (Revision 1263) +++ flashrom-it85spi_cleanup/it85spi.c (Arbeitskopie) @@ -37,7 +37,7 @@ #define MAX_TIMEOUT 100000 #define MAX_TRY 5 -/* Constans for I/O ports */ +/* Constants for I/O ports */ #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e @@ -52,13 +52,14 @@ #define CHIP_CHIP_VER_REG 0x22 /* These are standard Super I/O 16-bit base address registers */ -#define SHM_IO_BAD0 0x60 /* big-endian, this is high bits */ -#define SHM_IO_BAD1 0x61 +#define SHM_IO_BAR0 0x60 /* big-endian, this is high bits */ +#define SHM_IO_BAR1 0x61 -/* 8042 keyboard controller uses an input buffer and an output buffer to - * communicate with host CPU. Both buffers are 1-byte depth. That means the - * IBF is set to 1 when host CPU sends a command to input buffer (standing on - * the EC side). IBF is cleared to 0 once the command is read by EC. */ +/* The 8042 keyboard controller uses an input buffer and an output buffer to + * communicate with the host CPU. Both buffers are 1-byte depth. That means + * IBF is set to 1 when the host CPU sends a command to the input buffer + * of the EC. IBF is cleared to 0 once the command is read by the EC. + */ #define KB_IBF (1 << 1) /* Input Buffer Full */ #define KB_OBF (1 << 0) /* Output Buffer Full */ @@ -278,8 +279,8 @@ #ifdef LPC_IO /* Get LPCPNP of SHM. That's big-endian */ sio_write(superio.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */ - shm_io_base = (sio_read(superio.port, SHM_IO_BAD0) << 8) + - sio_read(superio.port, SHM_IO_BAD1); + shm_io_base = (sio_read(superio.port, SHM_IO_BAR0) << 8) + + sio_read(superio.port, SHM_IO_BAR1); msg_pdbg("%s():%d shm_io_base=0x%04x\n", __func__, __LINE__, shm_io_base); @@ -296,8 +297,8 @@ INDIRECT_A3(shm_io_base, (base >> 24)); #endif #ifdef LPC_MEMORY - base = (chipaddr)programmer_map_flash_region("flash base", 0xFFFFF000, - 0x1000); + base = (chipaddr)programmer_map_flash_region("it85 communication", + 0xFFFFF000, 0x1000); msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, (unsigned int)base); ce_high = (unsigned char*)(base + 0xE00); /* 0xFFFFFE00 */ @@ -328,7 +329,7 @@ } /* Called by internal_init() */ -int it85xx_probe_spi_flash(const char *name) +int it85xx_probe_spi_flash(void) { int ret; @@ -377,14 +378,14 @@ INDIRECT_A1(shm_io_base, (((unsigned long int)ce_low) >> 8) & 0xff); #endif #ifdef LPC_MEMORY - *ce_high = 0; + mmio_writeb(0, ce_high); #endif for (i = 0; i < writecnt; ++i) { #ifdef LPC_IO INDIRECT_WRITE(shm_io_base, writearr[i]); #endif #ifdef LPC_MEMORY - *ce_low = writearr[i]; + mmio_writeb(writearr[i], ce_low); #endif } for (i = 0; i < readcnt; ++i) { @@ -392,7 +393,7 @@ readarr[i] = INDIRECT_READ(shm_io_base); #endif #ifdef LPC_MEMORY - readarr[i] = *ce_low; + readarr[i] = mmio_readb(ce_low); #endif } #ifdef LPC_IO @@ -400,10 +401,20 @@ INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ #endif #ifdef LPC_MEMORY - *ce_high = 0; + mmio_writeb(0, ce_high); #endif return 0; } +int it85_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) +{ + return spi_read_chunked(flash, buf, start, len, 64); +} + +int it85_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) +{ + return spi_write_chunked(flash, buf, start, len, 64); +} + #endif Index: flashrom-it85spi_cleanup/spi.c =================================================================== --- flashrom-it85spi_cleanup/spi.c (Revision 1263) +++ flashrom-it85spi_cleanup/spi.c (Arbeitskopie) @@ -58,8 +58,8 @@ { /* SPI_CONTROLLER_IT85XX */ .command = it85xx_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, + .read = it85_spi_read, + .write_256 = it85_spi_write_256, }, { /* SPI_CONTROLLER_IT87XX */ Index: flashrom-it85spi_cleanup/programmer.h =================================================================== --- flashrom-it85spi_cleanup/programmer.h (Revision 1263) +++ flashrom-it85spi_cleanup/programmer.h (Arbeitskopie) @@ -588,9 +588,11 @@ struct superio probe_superio_ite85xx(void); int it85xx_spi_init(void); int it85xx_shutdown(void); -int it85xx_probe_spi_flash(const char *name); +int it85xx_probe_spi_flash(void); int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int it85_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len); +int it85_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); /* it87spi.c */ void enter_conf_mode_ite(uint16_t port); -- http://www.hailfinger.org/

2 4

flashrom -E
by Eric Konesky 08 Mar '11

08 Mar '11

I accidently erased my bios does this erase the boot block?

2 1

[PATCH] Initial ITE IT8500 EC support (second try)
by David Hendricks 08 Mar '11

08 Mar '11

A few months ago, ITE open sourced the initial IT8500 EC patch on this mailing list ( http://www.flashrom.org/pipermail/flashrom/2010-August/004382.html) so that we could check it in to the Chromium OS branch. It didn't quite make it upstream, and has been updated since then. The attached patch basically does the same thing and has been deployed and tested to work on the Cr-48. There are a few caveats, though: - The boot BIOS straps register must be modified to select LPC. This can be done with the attached "select_bbs.sh" script (Install iotools ( http://code.google.com/p/iotools/) before using select_bbs). We worked around this in the Chromium OS branch by adding a bus argument to the programmer option, ie "flashrom -p internal:bus=lpc". - It is very important to disable power management daemons before running Flashrom on this EC. I commented out the brute force method we use in the Chromium OS branch that disables powerd, since IIRC Carl-Daniel has a better approach in the works. - Due to dependencies which may be introduced by the OEM/ODM EC firmware, the code is not guaranteed to work for anything other than the Cr-48. - Carl-Daniel pointed out that the code might ignore the result of it87 init code. I've attempted to mitigate this in the patch (see internal.c), but I think it's just the symptom of a larger problem with how we detect and initialize IO bridges, and should probably be dealt with in a separate patch. *Here is the text from the original patch submission: The attached patch adds generalized support for IT8500/IT8502 embedded controllers. The patch was developed by Google for Flashrom r1082, but applies cleanly against r1130. It was tested for IT8500E on a Chrome OS platform and may require modification depending on ODM/OEM customization and EC firmware version. This patch is not officially supported by ITE Tech Inc.* Signed-off-by: David Hendricks <dhendrix(a)google.com> (The original patch also included a sign-off from Yung-chieh Lo @ Google and Donald Huang @ ITE). -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

2 5

[commit] r1279 - trunk
by repository service 08 Mar '11

08 Mar '11

Author: hailfinger Date: Tue Mar 8 01:23:49 2011 New Revision: 1279 URL: http://flashrom.org/trac/flashrom/changeset/1279 Log: Various IT85* cleanups and fixes. Fix a few typos. Change the EC memory region mapping name. Drop unused function parameter. Use mmio_writeb()/mmio_readb() to get reliable access to volatile memory locations instead of plain pointer access which is optimized away by gcc. Use own it85_* SPI high-level chip read/write functions instead of relying on unrelated ICH functions. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> David writes: I applied the patch against the Chromium OS branch and successfully tested read and write operations on a Cr48. Acked-by: David Hendricks <dhendrix(a)google.com> Modified: trunk/it85spi.c trunk/programmer.h trunk/spi.c Modified: trunk/it85spi.c ============================================================================== --- trunk/it85spi.c Tue Mar 8 01:09:11 2011 (r1278) +++ trunk/it85spi.c Tue Mar 8 01:23:49 2011 (r1279) @@ -37,7 +37,7 @@ #define MAX_TIMEOUT 100000 #define MAX_TRY 5 -/* Constans for I/O ports */ +/* Constants for I/O ports */ #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e @@ -52,13 +52,14 @@ #define CHIP_CHIP_VER_REG 0x22 /* These are standard Super I/O 16-bit base address registers */ -#define SHM_IO_BAD0 0x60 /* big-endian, this is high bits */ -#define SHM_IO_BAD1 0x61 +#define SHM_IO_BAR0 0x60 /* big-endian, this is high bits */ +#define SHM_IO_BAR1 0x61 -/* 8042 keyboard controller uses an input buffer and an output buffer to - * communicate with host CPU. Both buffers are 1-byte depth. That means the - * IBF is set to 1 when host CPU sends a command to input buffer (standing on - * the EC side). IBF is cleared to 0 once the command is read by EC. */ +/* The 8042 keyboard controller uses an input buffer and an output buffer to + * communicate with the host CPU. Both buffers are 1-byte depth. That means + * IBF is set to 1 when the host CPU sends a command to the input buffer + * of the EC. IBF is cleared to 0 once the command is read by the EC. + */ #define KB_IBF (1 << 1) /* Input Buffer Full */ #define KB_OBF (1 << 0) /* Output Buffer Full */ @@ -278,8 +279,8 @@ #ifdef LPC_IO /* Get LPCPNP of SHM. That's big-endian */ sio_write(superio.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */ - shm_io_base = (sio_read(superio.port, SHM_IO_BAD0) << 8) + - sio_read(superio.port, SHM_IO_BAD1); + shm_io_base = (sio_read(superio.port, SHM_IO_BAR0) << 8) + + sio_read(superio.port, SHM_IO_BAR1); msg_pdbg("%s():%d shm_io_base=0x%04x\n", __func__, __LINE__, shm_io_base); @@ -296,8 +297,8 @@ INDIRECT_A3(shm_io_base, (base >> 24)); #endif #ifdef LPC_MEMORY - base = (chipaddr)programmer_map_flash_region("flash base", 0xFFFFF000, - 0x1000); + base = (chipaddr)programmer_map_flash_region("it85 communication", + 0xFFFFF000, 0x1000); msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, (unsigned int)base); ce_high = (unsigned char*)(base + 0xE00); /* 0xFFFFFE00 */ @@ -328,7 +329,7 @@ } /* Called by internal_init() */ -int it85xx_probe_spi_flash(const char *name) +int it85xx_probe_spi_flash(void) { int ret; @@ -377,14 +378,14 @@ INDIRECT_A1(shm_io_base, (((unsigned long int)ce_low) >> 8) & 0xff); #endif #ifdef LPC_MEMORY - *ce_high = 0; + mmio_writeb(0, ce_high); #endif for (i = 0; i < writecnt; ++i) { #ifdef LPC_IO INDIRECT_WRITE(shm_io_base, writearr[i]); #endif #ifdef LPC_MEMORY - *ce_low = writearr[i]; + mmio_writeb(writearr[i], ce_low); #endif } for (i = 0; i < readcnt; ++i) { @@ -392,7 +393,7 @@ readarr[i] = INDIRECT_READ(shm_io_base); #endif #ifdef LPC_MEMORY - readarr[i] = *ce_low; + readarr[i] = mmio_readb(ce_low); #endif } #ifdef LPC_IO @@ -400,10 +401,20 @@ INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ #endif #ifdef LPC_MEMORY - *ce_high = 0; + mmio_writeb(0, ce_high); #endif return 0; } +int it85_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) +{ + return spi_read_chunked(flash, buf, start, len, 64); +} + +int it85_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) +{ + return spi_write_chunked(flash, buf, start, len, 64); +} + #endif Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Tue Mar 8 01:09:11 2011 (r1278) +++ trunk/programmer.h Tue Mar 8 01:23:49 2011 (r1279) @@ -585,9 +585,11 @@ struct superio probe_superio_ite85xx(void); int it85xx_spi_init(void); int it85xx_shutdown(void); -int it85xx_probe_spi_flash(const char *name); +int it85xx_probe_spi_flash(void); int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int it85_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len); +int it85_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); /* it87spi.c */ void enter_conf_mode_ite(uint16_t port); Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Tue Mar 8 01:09:11 2011 (r1278) +++ trunk/spi.c Tue Mar 8 01:23:49 2011 (r1279) @@ -58,8 +58,8 @@ { /* SPI_CONTROLLER_IT85XX */ .command = it85xx_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, + .read = it85_spi_read, + .write_256 = it85_spi_write_256, }, { /* SPI_CONTROLLER_IT87XX */

1 0

[PATCH] Compile fixes
by Carl-Daniel Hailfinger 08 Mar '11

08 Mar '11

Fix compilation if CONFIG_INTERNAL=no. Fix compilation if everything except CONFIG_SATAMV is no. Do not compile in PCI support for wiki printing if no PCI devices are supported. Note: The flashrom.c hunk is ugly. Suggestions how to solve the ugliness are appreciated. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-compilefixes/print_wiki.c =================================================================== --- flashrom-compilefixes/print_wiki.c (Revision 1275) +++ flashrom-compilefixes/print_wiki.c (Arbeitskopie) @@ -246,6 +246,8 @@ printf("\n|}\n\n|}\n"); } +/* Not needed for CONFIG_INTERNAL, but for all other PCI-based programmers. */ +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1 static void print_supported_pcidevs_wiki(const struct pcidev_status *devs) { int i = 0; @@ -262,6 +264,7 @@ (devs[i].status == NT) ? "?3" : "OK"); } } +#endif void print_supported_wiki(void) { Index: flashrom-compilefixes/flashrom.c =================================================================== --- flashrom-compilefixes/flashrom.c (Revision 1275) +++ flashrom-compilefixes/flashrom.c (Arbeitskopie) @@ -1186,9 +1186,12 @@ if (!flash || !flash->name) return NULL; +#if CONFIG_INTERNAL == 1 if (programmer_table[programmer].map_flash_region == physmap) { snprintf(location, sizeof(location), "at physical address 0x%lx", base); - } else { + } else +#endif + { snprintf(location, sizeof(location), "on %s", programmer_table[programmer].name); } Index: flashrom-compilefixes/programmer.h =================================================================== --- flashrom-compilefixes/programmer.h (Revision 1275) +++ flashrom-compilefixes/programmer.h (Arbeitskopie) @@ -229,7 +229,7 @@ #endif /* print.c */ -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI >= 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1 void print_supported_pcidevs(const struct pcidev_status *devs); #endif -- http://www.hailfinger.org/

2 2

[commit] r1278 - trunk
by repository service 08 Mar '11

08 Mar '11

Author: hailfinger Date: Tue Mar 8 01:09:11 2011 New Revision: 1278 URL: http://flashrom.org/trac/flashrom/changeset/1278 Log: Fix compilation if CONFIG_INTERNAL=no. Fix compilation if everything except CONFIG_SATAMV is no. Do not compile in PCI support for wiki printing if no PCI devices are supported. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/flashrom.c trunk/print_wiki.c trunk/programmer.h Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Mon Mar 7 16:32:58 2011 (r1277) +++ trunk/flashrom.c Tue Mar 8 01:09:11 2011 (r1278) @@ -1186,11 +1186,12 @@ if (!flash || !flash->name) return NULL; - if (programmer_table[programmer].map_flash_region == physmap) { +#if CONFIG_INTERNAL == 1 + if (programmer_table[programmer].map_flash_region == physmap) snprintf(location, sizeof(location), "at physical address 0x%lx", base); - } else { + else +#endif snprintf(location, sizeof(location), "on %s", programmer_table[programmer].name); - } msg_cinfo("%s chip \"%s %s\" (%d KB, %s) %s.\n", force ? "Assuming" : "Found", Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Mon Mar 7 16:32:58 2011 (r1277) +++ trunk/print_wiki.c Tue Mar 8 01:09:11 2011 (r1278) @@ -246,6 +246,8 @@ printf("\n|}\n\n|}\n"); } +/* Not needed for CONFIG_INTERNAL, but for all other PCI-based programmers. */ +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1 static void print_supported_pcidevs_wiki(const struct pcidev_status *devs) { int i = 0; @@ -262,6 +264,7 @@ (devs[i].status == NT) ? "?3" : "OK"); } } +#endif void print_supported_wiki(void) { Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Mon Mar 7 16:32:58 2011 (r1277) +++ trunk/programmer.h Tue Mar 8 01:09:11 2011 (r1278) @@ -229,7 +229,7 @@ #endif /* print.c */ -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI >= 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV >= 1 void print_supported_pcidevs(const struct pcidev_status *devs); #endif

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

flashrom